Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openeuler
Kernel
提交
e9ebb68b
K
Kernel
项目概览
openeuler
/
Kernel
接近 2 年 前同步成功
通知
8
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
K
Kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
提交
e9ebb68b
编写于
4月 28, 2010
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nv50: support fractional feedback divider on newer chips
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
7e99a9b2
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
120 addition
and
24 deletion
+120
-24
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/Makefile
+2
-1
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_drv.h
+6
-0
drivers/gpu/drm/nouveau/nv50_calc.c
drivers/gpu/drm/nouveau/nv50_calc.c
+87
-0
drivers/gpu/drm/nouveau/nv50_crtc.c
drivers/gpu/drm/nouveau/nv50_crtc.c
+25
-23
未找到文件。
drivers/gpu/drm/nouveau/Makefile
浏览文件 @
e9ebb68b
...
@@ -22,7 +22,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
...
@@ -22,7 +22,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
nv50_cursor.o nv50_display.o nv50_fbcon.o
\
nv50_cursor.o nv50_display.o nv50_fbcon.o
\
nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o
\
nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o
\
nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o
\
nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o
\
nv17_gpio.o nv50_gpio.o
nv17_gpio.o nv50_gpio.o
\
nv50_calc.o
nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG)
+=
nouveau_debugfs.o
nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG)
+=
nouveau_debugfs.o
nouveau-$(CONFIG_COMPAT)
+=
nouveau_ioc32.o
nouveau-$(CONFIG_COMPAT)
+=
nouveau_ioc32.o
...
...
drivers/gpu/drm/nouveau/nouveau_drv.h
浏览文件 @
e9ebb68b
...
@@ -1170,6 +1170,12 @@ int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
...
@@ -1170,6 +1170,12 @@ int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
int
nv50_gpio_get
(
struct
drm_device
*
dev
,
enum
dcb_gpio_tag
tag
);
int
nv50_gpio_get
(
struct
drm_device
*
dev
,
enum
dcb_gpio_tag
tag
);
int
nv50_gpio_set
(
struct
drm_device
*
dev
,
enum
dcb_gpio_tag
tag
,
int
state
);
int
nv50_gpio_set
(
struct
drm_device
*
dev
,
enum
dcb_gpio_tag
tag
,
int
state
);
/* nv50_calc. */
int
nv50_calc_pll
(
struct
drm_device
*
,
struct
pll_lims
*
,
int
clk
,
int
*
N1
,
int
*
M1
,
int
*
N2
,
int
*
M2
,
int
*
P
);
int
nv50_calc_pll2
(
struct
drm_device
*
,
struct
pll_lims
*
,
int
clk
,
int
*
N
,
int
*
fN
,
int
*
M
,
int
*
P
);
#ifndef ioread32_native
#ifndef ioread32_native
#ifdef __BIG_ENDIAN
#ifdef __BIG_ENDIAN
#define ioread16_native ioread16be
#define ioread16_native ioread16be
...
...
drivers/gpu/drm/nouveau/nv50_calc.c
0 → 100644
浏览文件 @
e9ebb68b
/*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "drmP.h"
#include "drm_fixed.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
int
nv50_calc_pll
(
struct
drm_device
*
dev
,
struct
pll_lims
*
pll
,
int
clk
,
int
*
N1
,
int
*
M1
,
int
*
N2
,
int
*
M2
,
int
*
P
)
{
struct
nouveau_pll_vals
pll_vals
;
int
ret
;
ret
=
nouveau_calc_pll_mnp
(
dev
,
pll
,
clk
,
&
pll_vals
);
if
(
ret
<=
0
)
return
ret
;
*
N1
=
pll_vals
.
N1
;
*
M1
=
pll_vals
.
M1
;
*
N2
=
pll_vals
.
N2
;
*
M2
=
pll_vals
.
M2
;
*
P
=
pll_vals
.
log2P
;
return
ret
;
}
int
nv50_calc_pll2
(
struct
drm_device
*
dev
,
struct
pll_lims
*
pll
,
int
clk
,
int
*
N
,
int
*
fN
,
int
*
M
,
int
*
P
)
{
fixed20_12
fb_div
,
a
,
b
;
*
P
=
pll
->
vco1
.
maxfreq
/
clk
;
if
(
*
P
>
pll
->
max_p
)
*
P
=
pll
->
max_p
;
if
(
*
P
<
pll
->
min_p
)
*
P
=
pll
->
min_p
;
/* *M = ceil(refclk / pll->vco.max_inputfreq); */
a
.
full
=
dfixed_const
(
pll
->
refclk
);
b
.
full
=
dfixed_const
(
pll
->
vco1
.
max_inputfreq
);
a
.
full
=
dfixed_div
(
a
,
b
);
a
.
full
=
dfixed_ceil
(
a
);
*
M
=
dfixed_trunc
(
a
);
/* fb_div = (vco * *M) / refclk; */
fb_div
.
full
=
dfixed_const
(
clk
*
*
P
);
fb_div
.
full
=
dfixed_mul
(
fb_div
,
a
);
a
.
full
=
dfixed_const
(
pll
->
refclk
);
fb_div
.
full
=
dfixed_div
(
fb_div
,
a
);
/* *N = floor(fb_div); */
a
.
full
=
dfixed_floor
(
fb_div
);
*
N
=
dfixed_trunc
(
fb_div
);
/* *fN = (fmod(fb_div, 1.0) * 8192) - 4096; */
b
.
full
=
dfixed_const
(
8192
);
a
.
full
=
dfixed_mul
(
a
,
b
);
fb_div
.
full
=
dfixed_mul
(
fb_div
,
b
);
fb_div
.
full
=
fb_div
.
full
-
a
.
full
;
*
fN
=
dfixed_trunc
(
fb_div
)
-
4096
;
*
fN
&=
0xffff
;
return
clk
;
}
drivers/gpu/drm/nouveau/nv50_crtc.c
浏览文件 @
e9ebb68b
...
@@ -264,38 +264,40 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
...
@@ -264,38 +264,40 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
int
int
nv50_crtc_set_clock
(
struct
drm_device
*
dev
,
int
head
,
int
pclk
)
nv50_crtc_set_clock
(
struct
drm_device
*
dev
,
int
head
,
int
pclk
)
{
{
uint32_t
pll_reg
=
NV50_PDISPLAY_CRTC_CLK_CTRL1
(
head
);
uint32_t
reg
=
NV50_PDISPLAY_CRTC_CLK_CTRL1
(
head
);
struct
nouveau_pll_vals
pll
;
struct
pll_lims
pll
;
struct
pll_lims
limits
;
uint32_t
reg1
,
reg2
;
uint32_t
reg1
,
reg2
;
int
ret
;
int
ret
,
N1
,
M1
,
N2
,
M2
,
P
;
ret
=
get_pll_limits
(
dev
,
pll_reg
,
&
limits
);
ret
=
get_pll_limits
(
dev
,
reg
,
&
pll
);
if
(
ret
)
if
(
ret
)
return
ret
;
return
ret
;
ret
=
nouveau_calc_pll_mnp
(
dev
,
&
limits
,
pclk
,
&
pll
);
if
(
pll
.
vco2
.
maxfreq
)
{
if
(
ret
<=
0
)
ret
=
nv50_calc_pll
(
dev
,
&
pll
,
pclk
,
&
N1
,
&
M1
,
&
N2
,
&
M2
,
&
P
);
return
ret
;
if
(
ret
<=
0
)
return
0
;
if
(
limits
.
vco2
.
maxfreq
)
{
NV_DEBUG
(
dev
,
"pclk %d out %d NM1 %d %d NM2 %d %d P %d
\n
"
,
NV_DEBUG
(
dev
,
"pclk %d out %d NM1 %d %d NM2 %d %d P %d
\n
"
,
pclk
,
ret
,
pll
.
N1
,
pll
.
M1
,
pll
.
N2
,
pll
.
M2
,
pll
.
log2P
);
pclk
,
ret
,
N1
,
M1
,
N2
,
M2
,
P
);
reg1
=
nv_rd32
(
dev
,
pll_reg
+
4
)
&
0xff00ff00
;
reg1
=
nv_rd32
(
dev
,
reg
+
4
)
&
0xff00ff00
;
reg2
=
nv_rd32
(
dev
,
pll_reg
+
8
)
&
0x8000ff00
;
reg2
=
nv_rd32
(
dev
,
reg
+
8
)
&
0x8000ff00
;
nv_wr32
(
dev
,
pll_reg
,
0x10000611
);
nv_wr32
(
dev
,
reg
,
0x10000611
);
nv_wr32
(
dev
,
pll_reg
+
4
,
reg1
|
(
pll
.
M1
<<
16
)
|
pll
.
N1
);
nv_wr32
(
dev
,
reg
+
4
,
reg1
|
(
M1
<<
16
)
|
N1
);
nv_wr32
(
dev
,
pll_reg
+
8
,
nv_wr32
(
dev
,
reg
+
8
,
reg2
|
(
P
<<
28
)
|
(
M2
<<
16
)
|
N2
);
reg2
|
(
pll
.
log2P
<<
28
)
|
(
pll
.
M2
<<
16
)
|
pll
.
N2
);
}
else
{
}
else
{
NV_DEBUG
(
dev
,
"pclk %d out %d NM %d %d P %d
\n
"
,
ret
=
nv50_calc_pll2
(
dev
,
&
pll
,
pclk
,
&
N1
,
&
N2
,
&
M1
,
&
P
);
pclk
,
ret
,
pll
.
N1
,
pll
.
M1
,
pll
.
log2P
);
if
(
ret
<=
0
)
return
0
;
NV_DEBUG
(
dev
,
"pclk %d out %d N %d fN 0x%04x M %d P %d
\n
"
,
pclk
,
ret
,
N1
,
N2
,
M1
,
P
);
reg1
=
nv_rd32
(
dev
,
pll_
reg
+
4
)
&
0xffc00000
;
reg1
=
nv_rd32
(
dev
,
reg
+
4
)
&
0xffc00000
;
nv_wr32
(
dev
,
pll_
reg
,
0x50000610
);
nv_wr32
(
dev
,
reg
,
0x50000610
);
nv_wr32
(
dev
,
pll_reg
+
4
,
reg1
|
nv_wr32
(
dev
,
reg
+
4
,
reg1
|
(
P
<<
16
)
|
(
M1
<<
8
)
|
N1
);
(
pll
.
log2P
<<
16
)
|
(
pll
.
M1
<<
8
)
|
pll
.
N1
);
nv_wr32
(
dev
,
reg
+
8
,
N2
);
}
}
return
0
;
return
0
;
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录