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提交 e7569e4a 编写于 作者: L Lijun Fang 提交者： Xie XiuQi
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Revert "iommu/arm-smmu-v3: Add support for PCI ATS" 

hulk inclusion
category: feature
bugzilla: 14369
CVE: NA

-------------------

The ATS is not used, and it will cause its
performance degradation, so revert it.

This reverts commit a0081bd606bbcd4b525ef137cc370e2109d1b8b1.
Signed-off-by: NLijun Fang <fanglijun3@huawei.com>
Reviewed-by: NZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 f4e41b69
隐藏空白更改
内联 并排
Showing with 6 addition and 219 deletion
drivers/iommu/arm-smmu-v3.c
浏览文件 @ e7569e4a
......@@ -40,7 +40,6 @@
#include <linux/of_iommu.h>
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/pci-ats.h>
#include <linux/platform_device.h>
#include <linux/sched/mm.h>
......@@ -105,7 +104,6 @@
#define IDR5_VAX_52_BIT 1
#define ARM_SMMU_CR0 0x20
#define CR0_ATSCHK (1 << 4)
#define CR0_CMDQEN (1 << 3)
#define CR0_EVTQEN (1 << 2)
#define CR0_PRIQEN (1 << 1)
......@@ -280,7 +278,6 @@
#define CMDQ_ERR_CERROR_NONE_IDX 0
#define CMDQ_ERR_CERROR_ILL_IDX 1
#define CMDQ_ERR_CERROR_ABT_IDX 2
#define CMDQ_ERR_CERROR_ATC_INV_IDX 3
#define CMDQ_0_OP GENMASK_ULL(7, 0)
#define CMDQ_0_SSV (1UL << 11)
......@@ -300,12 +297,6 @@
#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12)
#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32)
#define CMDQ_ATC_0_GLOBAL (1UL << 9)
#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0)
#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12)
#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12)
#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32)
#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0)
......@@ -378,11 +369,6 @@ module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
"Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
static bool disable_ats_check;
module_param_named(disable_ats_check, disable_ats_check, bool, S_IRUGO);
MODULE_PARM_DESC(disable_ats_check,
"By default, the SMMU checks whether each incoming transaction marked as translated is allowed by the stream configuration. This option disables the check.");
enum pri_resp {
PRI_RESP_DENY = 0,
PRI_RESP_FAIL = 1,
......@@ -456,16 +442,6 @@ struct arm_smmu_cmdq_ent {
u64 addr;
} tlbi;
#define CMDQ_OP_ATC_INV 0x40
#define ATC_INV_SIZE_ALL 52
struct {
u32 sid;
u32 ssid;
u64 addr;
u8 size;
bool global;
} atc;
#define CMDQ_OP_PRI_RESP 0x41
struct {
u32 sid;
......@@ -917,14 +893,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
case CMDQ_OP_TLBI_EL2_ASID:
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
break;
case CMDQ_OP_ATC_INV:
cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);
cmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global);
cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid);
cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid);
cmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size);
cmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK;
break;
case CMDQ_OP_PRI_RESP:
cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);
cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid);
......@@ -984,7 +952,6 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
[CMDQ_ERR_CERROR_NONE_IDX] = "No error",
[CMDQ_ERR_CERROR_ILL_IDX] = "Illegal command",
[CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch",
[CMDQ_ERR_CERROR_ATC_INV_IDX] = "ATC invalidate timeout",
};
int i;
......@@ -1004,14 +971,6 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
dev_err(smmu->dev, "retrying command fetch\n");
case CMDQ_ERR_CERROR_NONE_IDX:
return;
case CMDQ_ERR_CERROR_ATC_INV_IDX:
/*
* ATC Invalidation Completion timeout. CONS is still pointing
* at the CMD_SYNC. Attempt to complete other pending commands
* by repeating the CMD_SYNC, though we might well end up back
* here since the ATC invalidation may still be pending.
*/
return;
case CMDQ_ERR_CERROR_ILL_IDX:
/* Fallthrough */
default:
......@@ -1272,6 +1231,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
#ifdef CONFIG_PCI_ATS
FIELD_PREP(STRTAB_STE_1_EATS, STRTAB_STE_1_EATS_TRANS) |
#endif
FIELD_PREP(STRTAB_STE_1_STRW, strw));
if (smmu->features & ARM_SMMU_FEAT_STALLS &&
......@@ -1301,10 +1263,6 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
}
if (IS_ENABLED(CONFIG_PCI_ATS))
dst[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,
STRTAB_STE_1_EATS_TRANS));
arm_smmu_sync_ste_for_sid(smmu, sid);
dst[0] = cpu_to_le64(val);
arm_smmu_sync_ste_for_sid(smmu, sid);
......@@ -1695,104 +1653,6 @@ static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)
return IRQ_WAKE_THREAD;
}
/* ATS invalidation */
static bool arm_smmu_master_has_ats(struct arm_smmu_master_data *master)
{
return dev_is_pci(master->dev) && to_pci_dev(master->dev)->ats_enabled;
}
static void
arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
struct arm_smmu_cmdq_ent *cmd)
{
size_t log2_span;
size_t span_mask;
/* ATC invalidates are always on 4096 bytes pages */
size_t inval_grain_shift = 12;
unsigned long page_start, page_end;
*cmd = (struct arm_smmu_cmdq_ent) {
.opcode = CMDQ_OP_ATC_INV,
.substream_valid = !!ssid,
.atc.ssid = ssid,
};
if (!size) {
cmd->atc.size = ATC_INV_SIZE_ALL;
return;
}
page_start = iova >> inval_grain_shift;
page_end = (iova + size - 1) >> inval_grain_shift;
/*
* Find the smallest power of two that covers the range. Most
* significant differing bit between start and end address indicates the
* required span, ie. fls(start ^ end). For example:
*
* We want to invalidate pages [8; 11]. This is already the ideal range:
* x = 0b1000 ^ 0b1011 = 0b11
* span = 1 << fls(x) = 4
*
* To invalidate pages [7; 10], we need to invalidate [0; 15]:
* x = 0b0111 ^ 0b1010 = 0b1101
* span = 1 << fls(x) = 16
*/
log2_span = fls_long(page_start ^ page_end);
span_mask = (1ULL << log2_span) - 1;
page_start &= ~span_mask;
cmd->atc.addr = page_start << inval_grain_shift;
cmd->atc.size = log2_span;
}
static int arm_smmu_atc_inv_master(struct arm_smmu_master_data *master,
struct arm_smmu_cmdq_ent *cmd)
{
int i;
struct iommu_fwspec *fwspec = master->dev->iommu_fwspec;
if (!arm_smmu_master_has_ats(master))
return 0;
for (i = 0; i < fwspec->num_ids; i++) {
cmd->atc.sid = fwspec->ids[i];
arm_smmu_cmdq_issue_cmd(master->smmu, cmd);
}
arm_smmu_cmdq_issue_sync(master->smmu);
return 0;
}
static int arm_smmu_atc_inv_master_all(struct arm_smmu_master_data *master,
int ssid)
{
struct arm_smmu_cmdq_ent cmd;
arm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd);
return arm_smmu_atc_inv_master(master, &cmd);
}
static size_t
arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid,
unsigned long iova, size_t size)
{
unsigned long flags;
struct arm_smmu_cmdq_ent cmd;
struct arm_smmu_master_data *master;
arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd);
spin_lock_irqsave(&smmu_domain->devices_lock, flags);
list_for_each_entry(master, &smmu_domain->devices, list)
arm_smmu_atc_inv_master(master, &cmd);
spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
return size;
}
/* IO_PGTABLE API */
static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
{
......@@ -2216,8 +2076,6 @@ static void arm_smmu_detach_dev(struct device *dev)
if (smmu_domain) {
__iommu_sva_unbind_dev_all(dev);
arm_smmu_atc_inv_master_all(master, 0);
spin_lock_irqsave(&smmu_domain->devices_lock, flags);
list_del(&master->list);
spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
......@@ -2305,19 +2163,12 @@ static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
static size_t
arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
{
int ret;
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops;
if (!ops)
return 0;
ret = ops->unmap(ops, iova, size);
if (ret && smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)
ret = arm_smmu_atc_inv_domain(smmu_domain, 0, iova, size);
return ret;
return ops->unmap(ops, iova, size);
}
static void arm_smmu_flush_iotlb_all(struct iommu_domain *domain)
......@@ -2491,54 +2342,6 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
return sid < limit;
}
static int arm_smmu_enable_ats(struct arm_smmu_master_data *master)
{
size_t stu;
int ret, pos;
struct pci_dev *pdev;
struct arm_smmu_device *smmu = master->smmu;
struct iommu_fwspec *fwspec = master->dev->iommu_fwspec;
if (!(smmu->features & ARM_SMMU_FEAT_ATS) || !dev_is_pci(master->dev) ||
(fwspec->flags & IOMMU_FWSPEC_PCI_NO_ATS))
return -ENOSYS;
pdev = to_pci_dev(master->dev);
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
if (!pos)
return -ENOSYS;
/* Smallest Translation Unit: log2 of the smallest supported granule */
stu = __ffs(smmu->pgsize_bitmap);
ret = pci_enable_ats(pdev, stu);
if (ret) {
dev_err(&pdev->dev, "could not enable ATS: %d\n", ret);
return ret;
}
dev_dbg(&pdev->dev, "enabled ATS (STU=%zu, QDEP=%d)\n", stu,
pci_ats_queue_depth(pdev));
return 0;
}
static void arm_smmu_disable_ats(struct arm_smmu_master_data *master)
{
struct pci_dev *pdev;
if (!dev_is_pci(master->dev))
return;
pdev = to_pci_dev(master->dev);
if (!pdev->ats_enabled)
return;
pci_disable_ats(pdev);
}
static int arm_smmu_insert_master(struct arm_smmu_device *smmu,
struct arm_smmu_master_data *master)
{
......@@ -2661,11 +2464,9 @@ static int arm_smmu_add_device(struct device *dev)
master->ste.can_stall = true;
}
arm_smmu_enable_ats(master);
ret = iommu_device_link(&smmu->iommu, dev);
if (ret)
goto err_disable_ats;
goto err_free_master;
group = iommu_group_get_for_dev(dev);
if (IS_ERR(group)) {
......@@ -2682,9 +2483,6 @@ static int arm_smmu_add_device(struct device *dev)
arm_smmu_remove_master(smmu, master);
iommu_device_unlink(&smmu->iommu, dev);
err_disable_ats:
arm_smmu_disable_ats(master);
err_free_master:
kfree(master);
fwspec->iommu_priv = NULL;
......@@ -2712,7 +2510,6 @@ static void arm_smmu_remove_device(struct device *dev)
iommu_group_remove_device(dev);
arm_smmu_remove_master(smmu, master);
iommu_device_unlink(&smmu->iommu, dev);
arm_smmu_disable_ats(master);
kfree(master);
iommu_fwspec_free(dev);
}
......@@ -3353,16 +3150,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
}
}
if (smmu->features & ARM_SMMU_FEAT_ATS && !disable_ats_check) {
enables |= CR0_ATSCHK;
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
ARM_SMMU_CR0ACK);
if (ret) {
dev_err(smmu->dev, "failed to enable ATS check\n");
return ret;
}
}
ret = arm_smmu_setup_irqs(smmu);
if (ret) {
dev_err(smmu->dev, "failed to setup irqs\n");
......
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