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提交 e1ab4d02 编写于 作者: D denglei 提交者： Zheng Zengkai
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scsi/hifc: add io module of hifc driver 

driver inclusion
category: feature
bugzilla: 21

-----------------------------------------------------------------------

This module is mainly used to process I/O commands from the SCSI layer
and the exception mechanism.
1.read/write IO to chip.
2.Handling I/O Exceptions.
Signed-off-by: Ndenglei <denglei25@huawei.com>
Reviewed-by: Nchenguangli <chenguangli2@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
上级 825fba35
展开全部 隐藏空白更改
内联 并排
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drivers/scsi/huawei/hifc/hifc_io.c 0 → 100644
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此差异已折叠。
drivers/scsi/huawei/hifc/hifc_io.h 0 → 100644
浏览文件 @ e1ab4d02
/* SPDX-License-Identifier: GPL-2.0 */
/* Huawei Hifc PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
*/
#ifndef __HIFC_IO_H__
#define __HIFC_IO_H__
enum dif_mode_e {
DIF_MODE_NONE = 0x0,
DIF_MODE_INSERT = 0x1,
DIF_MODE_REMOVE = 0x2,
DIF_MODE_FORWARD_OR_REPLACE = 0x3
};
enum ref_tag_mode_e {
BOTH_NONE = 0x0,
RECEIVE_INCREASE = 0x1,
REPLACE_INCREASE = 0x2,
BOTH_INCREASE = 0x3
};
#define HIFC_DIF_DISABLE 0
#define HIFC_DIF_ENABLE 1
#define HIFC_DIF_SECTOR_512B_MODE 0
#define HIFC_DIF_SECTOR_4KB_MODE 1
#define HIFC_DIF_GUARD_VERIFY_ALGORITHM_CTL_T10_CRC16 0x0
#define HIFC_DIF_GUARD_VERIFY_CRC16_REPLACE_IP_CHECKSUM 0x1
#define HIFC_DIF_GUARD_VERIFY_IP_CHECKSUM_REPLACE_CRC16 0x2
#define HIFC_DIF_GUARD_VERIFY_ALGORITHM_CTL_IP_CHECKSUM 0x3
#define HIFC_DIF_CRC_CS_INITIAL_CONFIG_BY_REGISTER 0
#define HIFC_DIF_CRC_CS_INITIAL_CONFIG_BY_BIT0_1 0x4
#define HIFC_DIF_GARD_REF_APP_CTRL_VERIFY 0x4
#define HIFC_DIF_GARD_REF_APP_CTRL_NOT_VERIFY 0x0
#define HIFC_DIF_GARD_REF_APP_CTRL_INSERT 0x0
#define HIFC_DIF_GARD_REF_APP_CTRL_DELETE 0x1
#define HIFC_DIF_GARD_REF_APP_CTRL_FORWARD 0x2
#define HIFC_DIF_GARD_REF_APP_CTRL_REPLACE 0x3
#define HIFC_DIF_ERROR_CODE_MASK 0xe
#define HIFC_DIF_ERROR_CODE_CRC 0x2
#define HIFC_DIF_ERROR_CODE_REF 0x4
#define HIFC_DIF_ERROR_CODE_APP 0x8
#define HIFC_DIF_SEND_DIFERR_PAYLOAD 0
#define HIFC_DIF_SEND_DIFERR_CRC 1
#define HIFC_DIF_SEND_DIFERR_APP 2
#define HIFC_DIF_SEND_DIFERR_REF 3
#define HIFC_DIF_RECV_DIFERR_ALL 4
#define HIFC_DIF_RECV_DIFERR_CRC 5
#define HIFC_DIF_RECV_DIFERR_APP 6
#define HIFC_DIF_RECV_DIFERR_REF 7
#define HIFC_SECT_SIZE_512 512
#define HIFC_SECT_SIZE_4096 4096
#define HIFC_SECT_SIZE_512_8 520
#define HIFC_SECT_SIZE_4096_8 4104
#define HIFC_CTRL_MASK 0x1f
unsigned int hifc_send_scsi_cmnd(void *v_hba, struct unf_frame_pkg_s *v_pkg);
unsigned int hifc_scq_recv_iresp(struct hifc_hba_s *v_hba,
union hifcoe_scqe_u *v_wqe);
#endif /* __HIFC_IO_H__ */
drivers/scsi/huawei/hifc/hifc_wqe.c 0 → 100644
浏览文件 @ e1ab4d02
此差异已折叠。
drivers/scsi/huawei/hifc/hifc_wqe.h 0 → 100644
浏览文件 @ e1ab4d02
/* SPDX-License-Identifier: GPL-2.0 */
/* Huawei Hifc PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
*/
#ifndef __HIFC_WQE_H__
#define __HIFC_WQE_H__
#include "hifcoe_wqe.h"
#include "hifcoe_parent_context.h"
/* TGT WQE type */
/* DRV->uCode via Root or Parent SQ */
#define HIFC_SQE_FCP_TRD HIFCOE_TASK_T_TREAD
#define HIFC_SQE_FCP_TWR HIFCOE_TASK_T_TWRITE
#define HIFC_SQE_FCP_TRSP HIFCOE_TASK_T_TRESP
#define HIFC_SQE_FCP_TACK HIFCOE_TASK_T_TACK
#define HIFC_SQE_ELS_CMND HIFCOE_TASK_T_ELS
#define HIFC_SQE_ELS_RSP HIFCOE_TASK_T_ELS_RSP
#define HIFC_SQE_GS_CMND HIFCOE_TASK_T_GS
#define HIFC_SQE_BLS_CMND HIFCOE_TASK_T_ABTS
#define HIFC_SQE_FCP_IREAD HIFCOE_TASK_T_IREAD
#define HIFC_SQE_FCP_IWRITE HIFCOE_TASK_T_IWRITE
#define HIFC_SQE_FCP_ITMF HIFCOE_TASK_T_ITMF
#define HIFC_SQE_SESS_RST HIFCOE_TASK_T_SESS_RESET
#define HIFC_SQE_FCP_TMF_TRSP HIFCOE_TASK_T_TMF_RESP
/* DRV->uCode Via CMDQ */
#define HIFC_CMDQE_ABTS_RSP HIFCOE_TASK_T_ABTS_RSP
#define HIFC_CMDQE_ABORT HIFCOE_TASK_T_ABORT
#define HIFC_CMDQE_SESS_DIS HIFCOE_TASK_T_SESS_DIS
#define HIFC_CMDQE_SESS_DEL HIFCOE_TASK_T_SESS_DEL
/* uCode->Drv Via CMD SCQ */
#define HIFC_SCQE_FCP_TCMND HIFCOE_TASK_T_RCV_TCMND
#define HIFC_SCQE_ELS_CMND HIFCOE_TASK_T_RCV_ELS_CMD
#define HIFC_SCQE_ABTS_CMD HIFCOE_TASK_T_RCV_ABTS_CMD
#define HIFC_SCQE_FCP_IRSP HIFCOE_TASK_T_IRESP
#define HIFC_SCQE_FCP_ITMF_RSP HIFCOE_TASK_T_ITMF_RESP
/* uCode->Drv Via STS SCQ */
#define HIFC_SCQE_FCP_TSTS HIFCOE_TASK_T_TSTS
#define HIFC_SCQE_GS_RSP HIFCOE_TASK_T_RCV_GS_RSP
#define HIFC_SCQE_ELS_RSP HIFCOE_TASK_T_RCV_ELS_RSP
#define HIFC_SCQE_ABTS_RSP HIFCOE_TASK_T_RCV_ABTS_RSP
#define HIFC_SCQE_ELS_RSP_STS HIFCOE_TASK_T_ELS_RSP_STS
#define HIFC_SCQE_ABTS_RSP_STS HIFCOE_TASK_T_ABTS_RSP_STS
#define HIFC_SCQE_ABORT_STS HIFCOE_TASK_T_ABORT_STS
#define HIFC_SCQE_SESS_EN_STS HIFCOE_TASK_T_SESS_EN_STS
#define HIFC_SCQE_SESS_DIS_STS HIFCOE_TASK_T_SESS_DIS_STS
#define HIFC_SCQE_SESS_DEL_STS HIFCOE_TASK_T_SESS_DEL_STS
#define HIFC_SCQE_SESS_RST_STS HIFCOE_TASK_T_SESS_RESET_STS
#define HIFC_SCQE_ITMF_MARKER_STS HIFCOE_TASK_T_ITMF_MARKER_STS
#define HIFC_SCQE_ABTS_MARKER_STS HIFCOE_TASK_T_ABTS_MARKER_STS
#define HIFC_SCQE_FLUSH_SQ_STS HIFCOE_TASK_T_FLUSH_SQ_STS
#define HIFC_SCQE_BUF_CLEAR_STS HIFCOE_TASK_T_BUFFER_CLEAR_STS
#define HIFC_SCQE_CLEAR_SRQ_STS HIFCOE_TASK_T_CLEAR_SRQ_STS
#define HIFC_LOW_32_BITS(__addr) \
((unsigned int)((unsigned long long)(__addr) & 0xffffffff))
#define HIFC_HIGH_32_BITS(__addr)\
((unsigned int)(((unsigned long long)(__addr) >> 32) & 0xffffffff))
/* Error Code from SCQ */
#define HIFC_COMPLETION_STATUS_SUCCESS FCOE_CQE_COMPLETED
#define HIFC_COMPLETION_STATUS_ABORTED_SETUP_FAIL FCOE_IMMI_CMDPKT_SETUP_FAIL
#define HIFC_COMPLETION_STATUS_TIMEOUT FCOE_ERROR_CODE_E_D_TIMER_EXPIRE
#define HIFC_COMPLETION_STATUS_DIF_ERROR FCOE_ERROR_CODE_DATA_DIFX_FAILED
#define HIFC_COMPLETION_STATUS_DATA_OOO FCOE_ERROR_CODE_DATA_OOO_RO
#define HIFC_COMPLETION_STATUS_DATA_OVERFLOW \
FCOE_ERROR_CODE_DATA_EXCEEDS_DATA2TRNS
#define HIFC_SCQE_INVALID_CONN_ID 0xffff
#define HIFC_GET_SCQE_TYPE(scqe) ((scqe)->common.ch.wd0.task_type)
#define HIFC_GET_SCQE_STATUS(scqe) ((scqe)->common.ch.wd0.err_code)
#define HIFC_GET_SCQE_REMAIN_CNT(scqe) ((scqe)->common.ch.wd0.cqe_remain_cnt)
#define HIFC_GET_SCQE_CONN_ID(scqe) ((scqe)->common.conn_id)
#define HIFC_GET_WQE_TYPE(wqe) ((wqe)->ts_sl.task_type)
#define HIFC_WQE_IS_IO(wqe) \
(HIFC_GET_WQE_TYPE(wqe) != HIFC_SQE_SESS_RST)
#define HIFC_SCQE_HAS_ERRCODE(scqe) \
(HIFC_GET_SCQE_STATUS(scqe) != HIFC_COMPLETION_STATUS_SUCCESS)
#define HIFC_SCQE_ERR_TO_CM(scqe)\
(HIFC_GET_SCQE_STATUS(scqe) != FCOE_ELS_GS_RSP_EXCH_CHECK_FAIL)
#define HIFC_SCQE_CONN_ID_VALID(scqe) \
(HIFC_GET_SCQE_CONN_ID(scqe) != HIFC_SCQE_INVALID_CONN_ID)
#define HIFC_WQE_SECTION_CHUNK_SIZE 8 /* 8 bytes' chunk */
#define HIFC_T_RESP_WQE_CTR_TSL_SIZE 15 /* 8 bytes' chunk */
#define HIFC_T_RD_WR_WQE_CTR_TSL_SIZE 9 /* 8 bytes' chunk */
#define HIFC_T_RD_WR_WQE_CTR_BDSL_SIZE 4 /* 8 bytes' chunk */
#define HIFC_T_RD_WR_WQE_CTR_CTRLSL_SIZE 1 /* 8 bytes' chunk */
#define HIFC_WQE_SGE_ENTRY_NUM 2 /* BD SGE and DIF SGE count */
#define HIFC_WQE_SGE_DIF_ENTRY_NUM 1 /* DIF SGE count */
#define HIFC_WQE_SGE_LAST_FLAG 1
#define HIFC_WQE_SGE_NOT_LAST_FLAG 0
#define HIFC_WQE_SGE_EXTEND_FLAG 1
#define HIFC_WQE_SGE_NOT_EXTEND_FLAG 0
#define HIFC_FCP_TMF_PORT_RESET 0
#define HIFC_FCP_TMF_LUN_RESET 1
#define HIFC_FCP_TMF_TGT_RESET 2
#define HIFC_FCP_TMF_RSVD 3
#define HIFC_NO_OFFLOAD 0
#define HIFC_HAVE_OFFLOAD 1
#define HIFC_QID_SQ 0
#define HIFC_ADJUST_DATA(old_val, new_val) ((old_val) = (new_val))
#define HIFC_GET_RESET_TYPE(tmf_flag, reset_flag) \
do { \
switch (tmf_flag) { \
case UNF_FCP_TM_ABORT_TASK_SET: \
case UNF_FCP_TM_LOGICAL_UNIT_RESET: \
reset_flag = HIFC_FCP_TMF_LUN_RESET; \
break; \
case UNF_FCP_TM_TARGET_RESET: \
reset_flag = HIFC_FCP_TMF_TGT_RESET; \
break; \
case UNF_FCP_TM_CLEAR_TASK_SET: \
reset_flag = HIFC_FCP_TMF_PORT_RESET; \
break; \
default: \
reset_flag = HIFC_FCP_TMF_RSVD; \
} \
} while (0)
/*
* nic_wqe_ctrl_sec table define
*/
struct nic_wqe_ctrl_sec {
union {
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
/* marks ownership of WQE */
u32 owner : 1;
/* Control Section Length */
u32 ctrl_sec_len : 2;
/* Completion Section Length */
u32 completion_sec_len : 2;
/* DIF Section Length */
u32 dif_sec_len : 3;
/*
* Completion is Required - marks CQE generation request
* per WQE
*/
u32 cr : 1;
/* Data Format - format of BDS */
u32 df : 1;
/* Virtual Address */
u32 va : 1;
/* Task Section Length */
u32 task_sec_len : 5;
/* Completion Format */
u32 cf : 1;
u32 wf : 1;
/* reserved */
u32 rsvd : 4;
/* Driver Section Length */
u32 drv_sec_len : 2;
/* Buffer Descriptors Section Length */
u32 buf_desc_sec_len : 8;
#else
/* Buffer Descriptors Section Length */
u32 buf_desc_sec_len : 8;
/* Driver Section Length */
u32 drv_sec_len : 2;
/* reserved */
u32 rsvd : 4;
u32 wf : 1;
/* Completion Format */
u32 cf : 1;
/* Task Section Length */
u32 task_sec_len : 5;
/* Virtual Address */
u32 va : 1;
/* Data Format - format of BDS */
u32 df : 1;
/*
* Completion is Required - marks CQE generation request
* per WQE
*/
u32 cr : 1;
/* DIF Section Length */
u32 dif_sec_len : 3;
/* Completion Section Length */
u32 completion_sec_len : 2;
/* Control Section Length */
u32 ctrl_sec_len : 2;
/* marks ownership of WQE */
u32 owner : 1;
#endif
} bs;
u32 dw;
};
};
/*
* nic_rq_sge_sec table define
*/
struct nic_rq_sge_sec {
/* packet buffer address high */
u32 wb_addr_high;
/* packet buffer address low */
u32 wb_addr_low;
union {
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 rsvd : 1;
/* SGE length */
u32 length : 31;
#else
/* SGE length */
u32 length : 31;
u32 rsvd : 1;
#endif
} bs0;
u32 dw0;
};
union {
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
/* 0:list,1:last */
u32 list : 1;
/* 0:normal,1:pointer to next SGE */
u32 extension : 1;
/* key or unsed */
u32 key : 30;
#else
/* key or unsed */
u32 key : 30;
/* 0:normal,1:pointer to next SGE */
u32 extension : 1;
/* 0:list,1:last */
u32 list : 1;
#endif
} bs1;
u32 dw1;
};
};
/*
* nic_rq_bd_sec table define
*/
struct nic_rq_bd_sec {
/* packet buffer address high */
u32 pkt_buf_addr_high;
/* packet buffer address low */
u32 pkt_buf_addr_low;
};
/*
* nic_rq_wqe table define
*/
struct nic_rq_wqe {
struct nic_wqe_ctrl_sec rq_wqe_ctrl_sec;
u32 rsvd;
struct nic_rq_sge_sec rx_sge;
struct nic_rq_bd_sec pkt_buf_addr;
};
/* Link WQE structure */
struct hifc_link_wqe_s {
union {
struct {
unsigned int rsv1 : 14;
unsigned int wf : 1;
unsigned int rsv2 : 14;
unsigned int ctrlsl : 2;
unsigned int o : 1;
} wd0;
u32 val_wd0;
};
union {
struct {
unsigned int msn : 16;
unsigned int dump_msn : 15;
/* lp means whether O bit is overturn */
unsigned int lp : 1;
} wd1;
unsigned int val_wd1;
};
unsigned int next_page_addr_hi;
unsigned int next_page_addr_lo;
};
struct hifc_root_rq_complet_info_s {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned int done : 1; /* done bit,ucode will set to 1 */
unsigned int rsvd1 : 6;
unsigned int fc_pkt : 1; /* Marks whether the packet is fc type */
unsigned int rsvd2 : 24;
#else
unsigned int rsvd2 : 24;
unsigned int fc_pkt : 1; /* Marks whether the packet is fc type */
unsigned int rsvd1 : 6;
unsigned int done : 1; /* done bit,ucode will set to 1 */
#endif
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned short buf_length;
unsigned short exch_id;
#else
unsigned short exch_id;
unsigned short buf_length;
#endif
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned short sts_only; /* If only CMPL SECTION */
unsigned short status; /* 0:no err;!0:others */
#else
unsigned short status; /* 0:no err;!0:others */
unsigned short sts_only; /* If only CMPL SECTION */
#endif
unsigned int magic_num;
unsigned int rsvd[4];
};
/* Parent SQ WQE */
struct hifc_root_sge_s {
unsigned int buf_addr_hi;
unsigned int buf_addr_lo;
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned int ext_flag : 1;
unsigned int buf_len : 31;
#else
unsigned int buf_len : 31;
unsigned int ext_flag : 1;
#endif
} wd0;
struct {
unsigned int rsvd;
} wd1;
};
/* Root SQ WQE Task Section structure for FC */
struct hifc_root_sqe_task_section_s {
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned int task_type : 8;
/* 1:offload enable,0:offload disable. */
unsigned int off_load : 1;
unsigned int port_id : 4;
unsigned int host_id : 2;
unsigned int rsvd1 : 1;
unsigned int exch_id : 16;
#else
unsigned int exch_id : 16;
unsigned int rsvd1 : 1;
unsigned int host_id : 2;
unsigned int port_id : 4;
unsigned int off_load : 1;
unsigned int task_type : 8;
#endif
} fc_dw0;
union {
unsigned int context_gpa_hi;
unsigned int magic_num;
} fc_dw1;
struct {
unsigned int context_gpa_lo;
} fc_dw2;
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned short scq_num; /* SCQ num */
unsigned short rport_index; /* RPort */
#else
unsigned short rport_index; /* RPort */
unsigned short scq_num; /* SCQ num */
#endif
} fc_dw3;
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
unsigned int pkt_type : 1; /* pkt type 0:ETH, 1:FC */
unsigned int pkt_cos : 3;
unsigned int rsvd2 : 1;
unsigned int csize : 2;
unsigned int service_type : 5;
unsigned int parent_xid : 20;
#else
unsigned int parent_xid : 20;
unsigned int service_type : 5;
unsigned int csize : 2;
unsigned int rsvd2 : 1;
unsigned int pkt_cos : 3; /* pkt cos,4:ETH, 0:FC */
unsigned int pkt_type : 1; /* pkt type 0:ETH, 1:FC */
#endif
} fc_dw4;
struct {
unsigned int rsvd;
} fc_dw5;
};
/* Root SQ WQE */
struct hifc_root_sqe_s {
/* Control Section */
struct hifcoe_wqe_ctrl_s ctrl_section;
struct hifc_root_sqe_task_section_s task_section;
struct hifc_root_sge_s sge;
struct hifc_root_sge_s ctx_sge;
};
/* Parent SQ WQE and Root SQ WQE Related function */
void hifc_build_service_wqe_ctrl_section(struct hifcoe_wqe_ctrl_s *v_wqe_cs,
unsigned int ts_size,
unsigned int bdsl);
void hifc_build_service_wqe_ts_common(struct hifcoe_sqe_ts_s *v_sqe_ts,
unsigned int rport_index,
unsigned short local_xid,
unsigned short remote_xid,
unsigned short data_len);
void hifc_build_els_gs_wqe_sge(struct hifcoe_sqe_s *v_sqe, void *v_buf_addr,
unsigned long long v_phyaddr,
unsigned int buf_len,
unsigned int xid, void *v_hba);
void hifc_build_els_wqe_ts_req(struct hifcoe_sqe_s *v_sqe,
void *v_sq_info, unsigned short cmnd,
unsigned int v_scqn, void *v_frame_pld);
void hifc_build_els_wqe_ts_rsp(struct hifcoe_sqe_s *v_sqe, void *v_sq_info,
void *v_frame_pld, unsigned short type,
unsigned short cmnd, unsigned int v_scqn);
void hifc_build_els_wqe_ts_magic_num(struct hifcoe_sqe_s *v_sqe,
unsigned short els_cmnd_type,
unsigned int v_magic_num);
void hifc_build_gs_wqe_ts_req(struct hifcoe_sqe_s *v_sqe,
unsigned int magic_num);
void hifc_build_bls_wqe_ts_req(struct hifcoe_sqe_s *v_sqe,
unsigned int abts_param,
unsigned int magic_num);
void hifc_build_service_wqe_root_ts(void *v_hba,
struct hifc_root_sqe_s *v_rt_sqe,
unsigned int rx_id, unsigned int rport_id,
unsigned int scq_num);
void hifc_build_service_wqe_root_sge(struct hifc_root_sqe_s *v_rt_sqe,
void *v_buf_addr,
unsigned long long v_phyaddr,
unsigned int buf_len,
void *v_hba);
void hifc_build_els_wqe_root_offload(struct hifc_root_sqe_s *v_rt_sqe,
dma_addr_t ctx_addr,
unsigned int xid);
void hifc_build_wqe_owner_pmsn(struct hifcoe_wqe_ctrl_s *v_wqe_cs,
unsigned short owner,
unsigned short pmsn);
void hifc_convert_parent_wqe_to_big_endian(struct hifcoe_sqe_s *v_sqe);
void hifc_convert_root_wqe_to_big_endian(struct hifc_root_sqe_s *v_sqe);
void hifc_build_icmnd_wqe_ts(void *v_hba, struct unf_frame_pkg_s *v_pkg,
struct hifcoe_sqe_ts_s *v_sqe_ts);
void hifc_build_icmnd_wqe_ts_header(struct unf_frame_pkg_s *v_pkg,
struct hifcoe_sqe_s *v_sqe,
unsigned char v_task_type,
unsigned short v_exi_base,
unsigned char v_port_idx);
void hifc_build_cmdqe_common(union hifc_cmdqe_u *cmdqe,
enum hifcoe_task_type_e task_type,
unsigned short rx_id);
void hifc_build_srq_wqe_ctrls(struct hifcoe_rqe_s *v_rqe, unsigned short owner,
unsigned short pmsn);
void hifc_build_common_wqe_ctrls(struct hifcoe_wqe_ctrl_s *v_ctrl_sl,
unsigned char v_task_len);
void hifc_build_service_wqe_ctx_sge(struct hifc_root_sqe_s *v_rt_sqe,
unsigned long long v_ctx_addr,
unsigned int buf_len);
void hifc_build_trd_twr_wqe_ctrls(struct unf_frame_pkg_s *v_pkg,
struct hifcoe_sqe_s *v_sqe);
#endif
drivers/scsi/huawei/hifc/hifcoe_parent_context.h 0 → 100644
浏览文件 @ e1ab4d02
/* SPDX-License-Identifier: GPL-2.0 */
/* Huawei Hifc PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
*/
#ifndef __HIFCOE_PARENT_CONTEXT_H__
#define __HIFCOE_PARENT_CONTEXT_H__
enum fc_parent_status_e {
FCOE_PARENT_STATUS_INVALID = 0,
FCOE_PARENT_STATUS_NORMAL,
FCOE_PARENT_STATUS_CLOSING
};
#define HIFCOE_DOUBLE_SGL (1)
#define HIFCOE_SINGLE_SGL (0)
#define HIFCOE_DIX_ALGORITHM_IP (1)
#define HIFCOE_DIX_ALGORITHM_CRC (0)
#define HIFCOE_PARENT_CONTEXT_KEY_ALIGN_SIZE (48)
#define HIFCOE_PARENT_CONTEXT_SRQ_QINFO_SIZE (8)
#define HIFCOE_PARENT_CONTEXT_TIMER_SIZE (32) /* 24+2*N,N=timer count */
#define HIFCOE_RQ_FILLED_OFFSET \
((u8)(u32)& \
(((struct hifcoe_sw_section_s *)0x0)->occupy_by_rqe_filled_flag))
#define HIFCOE_RW_LOCK_AREA_OFFSET \
((u8)(u32)&\
(((struct hifcoe_sw_section_s *)0x0)->occupy_by_rw_lock_area))
/* "fqg_level_eventiq_info_s" should be care if MAX_EVENTIQ_LEVEL is larger
* than 4
*/
#define MAX_EVENTIQ_LEVEL 4
#define MAX_EVENTIQ_LEVEL_SHIFT 2
#define SP_FEATRUE_EDTR 0x1
#define SP_FEATRUE_SEQ_CNT 0x2
#define MAX_PKT_SIZE_PER_DISPATCH (FC_PARENT_P->per_xmit_data_size)
#define MAX_PKT_SIZE_PER_DISPATCH_DIF_4K \
(MAX_PKT_SIZE_PER_DISPATCH + ((MAX_PKT_SIZE_PER_DISPATCH >> 12) << 3))
#define MAX_PKT_SIZE_PER_DISPATCH_DIF_512B \
(MAX_PKT_SIZE_PER_DISPATCH + ((MAX_PKT_SIZE_PER_DISPATCH >> 9) << 3))
#define MAX_PKT_SIZE_PER_DISPATCH_DIF(shift) \
(MAX_PKT_SIZE_PER_DISPATCH +\
((u32)((MAX_PKT_SIZE_PER_DISPATCH >> 9) >> (shift)) << 3))
/* immidiate data DIF info definition in parent context */
struct immi_dif_info_s {
union {
u32 value;
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 pdu_difx_cnt :8;
u32 sct_size :1;/* Sector size, 1: 4K; 0: 512 */
u32 dif_verify_type :2; /* verify type */
u32 dif_ins_rep_type:2; /* ins&rep type */
u32 io_1st_pdu :1;
/* Check blocks whose application tag contains
* 0xFFFF flag
*/
u32 difx_app_esc :1;
u32 difx_ref_esc :1;
/*
* Check blocks whose reference tag contains 0xFFFF flag
*/
u32 grd_ctrl :3; /* The DIF/DIX Guard control */
/* Bit 0: DIF/DIX guard verify algorithm control */
u32 grd_agm_ctrl :2;
/*
* Bit 1: DIF/DIX guard replace or insert algorithm
* control
*/
u32 grd_agm_ini_ctrl :3;
/* The DIF/DIX Reference tag control */
u32 ref_tag_ctrl :3;
/* Bit 0: scenario of the reference tag verify mode */
u32 ref_tag_mode :2;
/*
* Bit 1: scenario of the reference tag insert/replace
* mode
*/
/* 0: fixed; 1: increasement;*/
u32 app_tag_ctrl :3; /* DIF/DIX APP TAG Control */
#else
u32 app_tag_ctrl :3; /* DIF/DIX APP TAG Control */
/* Bit 0: scenario of the reference tag verify mode */
u32 ref_tag_mode :2;
/*
* Bit 1: scenario of the reference tag insert/replace
* mode
*/
/* 0: fixed; 1: increasement;*/
/* The DIF/DIX Reference tag control */
u32 ref_tag_ctrl :3;
u32 grd_agm_ini_ctrl :3;
/* Bit 0: DIF/DIX guard verify algorithm control */
u32 grd_agm_ctrl :2;
/*
* Bit 1: DIF/DIX guard replace or insert algorithm
* control
*/
u32 grd_ctrl :3; /* The DIF/DIX Guard control */
/*
* Check blocks whose reference tag contains 0xFFFF flag
*/
u32 difx_ref_esc :1;
/*
* Check blocks whose application tag contains 0xFFFF
* flag
*/
u32 difx_app_esc :1;
u32 io_1st_pdu :1;
u32 dif_ins_rep_type:2; /* ins&rep type */
u32 dif_verify_type :2; /* verify type */
u32 sct_size :1; /* Sector size, 1: 4K; 0: 512 */
u32 pdu_difx_cnt :8;
#endif
} info;
} dif_dw3;
union {
u32 value;
struct {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 difx_len :11; /* DIF/DIFX total length */
u32 difx_en :1; /* DIF/DIFX enable flag */
u32 rsv0 :4;
u32 dif_cnt :16;
#else
u32 dif_cnt :16;
u32 rsv0 :4;
u32 difx_en :1; /* DIF/DIFX enable flag */
u32 difx_len :11; /* DIF/DIFX total length */
#endif
} info;
} dif_other;
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 rep_app_tag :16;
u32 cmp_app_tag :16;
#else
u32 cmp_app_tag :16;
u32 rep_app_tag :16;
#endif
/*
* The ref tag value for verify compare, do not support replace or
* insert ref tag
*/
u32 cmp_ref_tag;
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 cmp_app_tag_msk :16;
u32 rsv1 :16;
#else
u32 rsv1 :16;
u32 cmp_app_tag_msk :16;
#endif
};
/* parent context SW section definition: SW(80B) */
struct hifcoe_sw_section_s {
/* RO fields */
u32 scq_num_rcv_cmd; /* scq number used for cmd receive */
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 xid; /* driver init */
#else
struct {
u32 xid :13;
u32 vport :7;
u32 csctrl :8;
u32 rsvd0 :4;
} sw_ctxt_vport_xid;
#endif
u32 cid; /* ucode init */
u16 conn_id;
u16 immi_rq_page_size;
u16 immi_taskid_min;
u16 immi_taskid_max;
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u32 vlan_id : 16; /* Vlan ID */
/* phycial port to receive and transmit packet. */
u32 port_id : 4;
/*
* new srq offset. Ucode use new srq to receive els/gs with big payload.
*/
u32 rsvd1 : 5;
u32 srr_support : 2; /* sequence retransmition support flag */
u32 srv_type : 5;
#else
union {
u32 pctxt_val0;
struct {
u32 srv_type : 5; /* driver init */
/* sequence retransmition support flag */
u32 srr_support : 2;
u32 rsvd1 : 5;
u32 port_id : 4; /* driver init */
u32 vlan_id : 16; /* driver init */
} dw;
} sw_ctxt_misc;
#endif
u16 oqid_rd;
u16 oqid_wr;
u32 per_xmit_data_size;
/* RW fields */
u32 cmd_scq_gpa_h;
u32 cmd_scq_gpa_l;
/* E_D_TOV timer value: value should be set on ms by driver */
u32 e_d_tov_timer_val;
/*
* mfs unalined bytes of per 64KB dispatch; equal to
* "MAX_PKT_SIZE_PER_DISPATCH%info->parent->tx_mfs"
*/
u16 mfs_unaligned_bytes;
u16 tx_mfs; /* remote port max receive fc payload length */
/* max data len allowed in xfer_rdy dis scenario*/
u32 xfer_rdy_dis_max_len_remote;
u32 xfer_rdy_dis_max_len_local;
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
/* Double or single SGL, 1: double; 0: single */
u32 sgl_num :1;
u32 write_xfer_rdy :1; /* WRITE Xfer_Rdy disable or enable */
u32 rec_support :1; /* REC support flag */
u32 conf_support :1; /* Response confirm support flag */
u32 vlan_enable :1; /* Vlan enable flag */
u32 e_d_tov :1; /* E_D_TOV Resolution, 0: ms, 1: us*/
/* seq_cnt, 1: increament support, 0: increament not support */
u32 seq_cnt :1;
/* 0:Target, 1:Initiator, 2:Target&Initiator */
u32 work_mode :2;
/* used for parent context cache Consistency judgment,1: done*/
u32 flush_done :1;
u32 oq_cos_cmd :3; /* esch oq cos for cmd/xferrdy/rsp */
u32 oq_cos_data :3; /* esch oq cos for data */
u32 cos :3; /* doorbell cos value */
u32 status :8; /* status of flow*/
u32 rsvd4 :2;
u32 priority :3; /* vlan priority */
#else
union {
struct {
u32 priority : 3; /* vlan priority */
u32 rsvd4 : 2;
u32 status : 8; /* status of flow*/
u32 cos : 3; /* doorbell cos value */
u32 oq_cos_data : 3; /* esch oq cos for data */
/* esch oq cos for cmd/xferrdy/rsp */
u32 oq_cos_cmd : 3;
/*
* used for parent context cache Consistency judgment,
* 1: done
*/
u32 flush_done : 1;
/* 0:Target, 1:Initiator, 2:Target&Initiator */
u32 work_mode : 2;
u32 seq_cnt : 1; /* seq_cnt */
u32 e_d_tov : 1; /* E_D_TOV resolution */
u32 vlan_enable : 1; /* Vlan enable flag */
/* Response confirm support flag */
u32 conf_support : 1;
u32 rec_support : 1; /* REC support flag */
/* WRITE Xfer_Rdy disable or enable */
u32 write_xfer_rdy : 1;
/* Double or single SGL, 1: double; 0: single */
u32 sgl_num : 1;
} dw;
u32 pctxt_val1;
} sw_ctxt_config;
#endif
/* immidiate data dif control info(20B) */
struct immi_dif_info_s immi_dif_info;
};
struct hifcoe_hw_rsvd_queue_s {
/* bitmap[0]:255-192 */
/* bitmap[1]:191-128 */
/* bitmap[2]:127-64 */
/* bitmap[3]:63-0 */
u64 seq_id_bitmap[4];
struct {
u64 last_req_seq_id : 8;
u64 xid : 20;
u64 rsvd0 : 36;
} wd0;
};
struct hifcoe_sq_qinfo_s {
u64 rsvd_0 : 10;
/* 0: get pmsn from queue header; 1: get pmsn from ucode */
u64 pmsn_type : 1;
u64 rsvd_1 : 4;
u64 cur_wqe_o : 1; /* should be opposite from loop_o */
u64 rsvd_2 : 48;
u64 cur_sqe_gpa;
u64 pmsn_gpa; /* sq's queue header gpa */
u64 sqe_dmaattr_idx : 6;
u64 sq_so_ro : 2;
u64 rsvd_3 : 2;
u64 ring : 1; /* 0: link; 1: ring */
u64 loop_o : 1; /* init to be the first round o-bit */
u64 rsvd_4 : 4;
u64 zerocopy_dmaattr_idx : 6;
u64 zerocopy_so_ro : 2;
u64 parity : 8;
u64 rsvd_5 : 26;
u64 pcie_template : 6;
};
struct hifcoe_cq_qinfo_s {
u64 pcie_template_hi : 3;
u64 parity_2 : 1;
u64 cur_cqe_gpa : 60;
u64 pi : 15;
u64 pi_o : 1;
u64 ci : 15;
u64 ci_o : 1;
/* if init_mode = 2, is msi/msi-x; other the low-5-bit means c_eqn */
u64 c_eqn_msi_x : 10;
u64 parity_1 : 1;
/* 0: get ci from queue header; 1: get ci from ucode */
u64 ci_type : 1;
u64 cq_depth : 3; /* valid when ring = 1 */
u64 armq : 1; /* 0: IDLE state; 1: NEXT state */
u64 cur_cqe_cnt : 8;
u64 cqe_max_cnt : 8;
u64 cqe_dmaattr_idx : 6;
u64 cq_so_ro : 2;
u64 init_mode : 2; /* 1: armQ; 2: msi/msi-x; others: rsvd */
u64 next_o : 1; /* next pate valid o-bit */
u64 loop_o : 1; /* init to be the first round o-bit */
u64 next_cq_wqe_page_gpa : 52;
u64 pcie_template_lo : 3;
u64 parity_0 : 1;
u64 ci_gpa : 60; /* cq's queue header gpa */
};
struct hifcoe_scq_qinfo_s {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
union {
struct {
u64 parity : 6;
u64 rq_th2_preld_cache_num : 5;
u64 rq_th1_preld_cache_num : 5;
u64 rq_th0_preld_cache_num : 5;
u64 rq_min_preld_cache_num : 4;
u64 sq_th2_preld_cache_num : 5;
u64 sq_th1_preld_cache_num : 5;
u64 sq_th0_preld_cache_num : 5;
u64 sq_min_preld_cache_num : 4;
u64 scq_n : 20; /* scq number */
} info;
u64 pctxt_val1;
} hw_scqc_config;
#else
union {
struct {
u64 scq_n : 20; /* scq number */
u64 sq_min_preld_cache_num : 4;
u64 sq_th0_preld_cache_num : 5;
u64 sq_th1_preld_cache_num : 5;
u64 sq_th2_preld_cache_num : 5;
u64 rq_min_preld_cache_num : 4;
u64 rq_th0_preld_cache_num : 5;
u64 rq_th1_preld_cache_num : 5;
u64 rq_th2_preld_cache_num : 5;
u64 parity : 6;
} info;
u64 pctxt_val1;
} hw_scqc_config;
#endif
};
struct hifcoe_srq_qinfo_s {
#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
u64 srqc_gpa : 60;
u64 parity : 4;
#else
u64 parity : 4;
u64 srqc_gpa : 60;
#endif
};
/* here is the layout of service type 12/13 */
struct hifcoe_parent_context_s {
u8 key[HIFCOE_PARENT_CONTEXT_KEY_ALIGN_SIZE];
struct hifcoe_scq_qinfo_s resp_scq_qinfo;
struct hifcoe_srq_qinfo_s imm_srq_info;
struct hifcoe_sq_qinfo_s sq_qinfo;
u8 timer_section[HIFCOE_PARENT_CONTEXT_TIMER_SIZE];
struct hifcoe_hw_rsvd_queue_s hw_rsvdq;
struct hifcoe_srq_qinfo_s els_srq_info;
struct hifcoe_sw_section_s sw_section;
};
#endif
drivers/scsi/huawei/hifc/hifcoe_wqe.h 0 → 100644
浏览文件 @ e1ab4d02
此差异已折叠。
drivers/scsi/huawei/hifc/unf_io.c 0 → 100644
浏览文件 @ e1ab4d02
此差异已折叠。
drivers/scsi/huawei/hifc/unf_io.h 0 → 100644
浏览文件 @ e1ab4d02
/* SPDX-License-Identifier: GPL-2.0 */
/* Huawei Hifc PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
*/
#ifndef __UNF_IO_H__
#define __UNF_IO_H__
#define UNF_MAX_TARGET_NUMBER 2048
#define UNF_DEFAULT_MAX_LUN 0xFFFF
#define UNF_MAX_DMA_SEGS 0x400
#define UNF_MAX_SCSI_CMND_LEN 16
#define UNF_MAX_SECTORS 0xffff
#define UNF_MAX_BUS_CHANNEL 0
#define UNF_DMA_BOUNDARY 0xffffffffffffffff
#define UNF_MAX_CMND_PER_LUN 64 /* LUN max command */
#define NO_SENSE 0x00
#define RECOVERED_ERROR 0x01
#define NOT_READY 0x02
#define MEDIUM_ERROR 0x03
#define HARDWARE_ERROR 0x04
#define ILLEGAL_REQUEST 0x05
#define UNIT_ATTENTION 0x06
#define DATA_PROTECT 0x07
#define BLANK_CHECK 0x08
#define COPY_ABORTED 0x0a
#define ABORTED_COMMAND 0x0b
#define VOLUME_OVERFLOW 0x0d
#define MISCOMPARE 0x0e
#define UNF_GET_SCSI_HOST_ID_BY_CMND(pcmd) ((pcmd)->scsi_host_id)
#define UNF_GET_SCSI_ID_BY_CMND(pcmd) ((pcmd)->scsi_id)
#define UNF_GET_HOST_PORT_BY_CMND(pcmd) ((pcmd)->drv_private)
#define UNF_GET_FCP_CMND(pcmd) ((pcmd)->pcmnd[0])
#define UNF_GET_DATA_LEN(pcmd) ((pcmd)->transfer_len)
#define UNF_GET_DATA_DIRECTION(pcmd) ((pcmd)->data_direction)
#define UNF_GET_HOST_CMND(pcmd) ((pcmd)->upper_cmnd)
#define UNF_GET_CMND_DONE_FUNC(pcmd) ((pcmd)->pfn_done)
#define UNF_GET_SGL_ENTRY_BUF_FUNC(pcmd) ((pcmd)->pfn_unf_ini_get_sgl_entry)
#define UNF_GET_SENSE_BUF_ADDR(pcmd) ((pcmd)->sense_buf)
#define UNF_GET_ERR_CODE_TABLE(pcmd) ((pcmd)->err_code_table)
#define UNF_GET_ERR_CODE_TABLE_COUNT(pcmd) ((pcmd)->err_code_table_cout)
#define UNF_SET_HOST_CMND(pcmd, host_cmd) ((pcmd)->upper_cmnd = (host_cmd))
#define UNF_SET_CMND_DONE_FUNC(pcmd, pfn) ((pcmd)->pfn_done = (pfn))
#define UNF_SET_RESID(pcmd, id_len) ((pcmd)->resid = (id_len))
#define UNF_SET_CMND_RESULT(pcmd, uiresult) ((pcmd)->result = ((int)uiresult))
#define UNF_DONE_SCSI_CMND(pcmd) ((pcmd)->pfn_done(pcmd))
#define UNF_GET_CMND_SGL(pcmd) ((pcmd)->sgl)
#define UNF_INI_GET_DIF_SGL(pcmd) ((pcmd)->dif_control.dif_sgl)
unsigned int unf_ini_scsi_completed(void *v_lport,
struct unf_frame_pkg_s *v_pkg);
unsigned int unf_ini_get_sgl_entry(void *v_pkg, char **v_buf,
unsigned int *v_buf_len);
unsigned int unf_ini_get_dif_sgl_entry(void *v_pkg, char **v_buf,
unsigned int *v_buf_len);
void unf_complete_cmnd(struct unf_scsi_cmd_s *v_scsi_cmnd, unsigned int result);
void unf_done_ini_xchg(struct unf_xchg_s *v_xchg);
unsigned int unf_tmf_timeout_recovery_special(void *v_rport, void *v_xchg);
void unf_abts_timeout_recovery_default(void *v_rport, void *v_xchg);
int unf_cm_queue_command(struct unf_scsi_cmd_s *v_scsi_cmnd);
int unf_cm_eh_abort_handler(struct unf_scsi_cmd_s *v_scsi_cmnd);
int unf_cm_eh_device_reset_handler(struct unf_scsi_cmd_s *v_scsi_cmnd);
int unf_cm_target_reset_handler(struct unf_scsi_cmd_s *v_scsi_cmnd);
int unf_cm_bus_reset_handler(struct unf_scsi_cmd_s *v_scsi_cmnd);
struct unf_rport_s *unf_find_rport_by_scsi_id(
struct unf_lport_s *v_lport,
struct unf_ini_error_code_s *v_err_code_table,
unsigned int v_err_code_table_cout,
unsigned int v_scsi_id,
unsigned int *v_scsi_result);
struct unf_lport_s *unf_find_lport_by_scsi_cmd(
struct unf_scsi_cmd_s *v_scsi_cmnd);
void unf_tmf_abnormal_recovery(struct unf_lport_s *v_lport,
struct unf_rport_s *v_rport,
struct unf_xchg_s *v_xchg);
unsigned int unf_get_uplevel_cmnd_errcode(
struct unf_ini_error_code_s *v_err_table,
unsigned int v_err_table_count,
unsigned int v_drv_err_code);
#endif
drivers/scsi/huawei/hifc/unf_io_abnormal.c 0 → 100644
浏览文件 @ e1ab4d02
此差异已折叠。
drivers/scsi/huawei/hifc/unf_io_abnormal.h 0 → 100644
浏览文件 @ e1ab4d02
/* SPDX-License-Identifier: GPL-2.0 */
/* Huawei Hifc PCI Express Linux driver
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*
*/
#ifndef __UNF_IO__ABNORMAL_H__
#define __UNF_IO__ABNORMAL_H__
#define UNF_GET_LL_ERR(v_pkg) ((v_pkg->status) >> 16)
void unf_process_scsi_mgmt_result(struct unf_frame_pkg_s *v_pkg,
struct unf_xchg_s *v_xchg);
unsigned int unf_hardware_start_io(struct unf_lport_s *v_lport,
struct unf_frame_pkg_s *v_pkg);
#endif
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