drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twice

For vega20, there are two UVD rings which share one powerplay instance.
Under some case(two rings used parallel), the uvd dpm is disabled twice
which causes the SMC hang.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NRex Zhu <rezhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

@@ -2464,6 +2464,9 @@ static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 {
 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 
+	if (data->vce_power_gated == bgate)
+		return ;
+
 	data->vce_power_gated = bgate;
 	vega20_enable_disable_vce_dpm(hwmgr, !bgate);
 }
@@ -2472,6 +2475,9 @@ static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 {
 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 
+	if (data->uvd_power_gated == bgate)
+		return ;
+
 	data->uvd_power_gated = bgate;
 	vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
 }