xhci-pci: Allow host runtime PM as default for Intel Alder Lake xHCI
stable inclusion from stable-5.10.38 commit ca043cc02a88b893c8f43da03ef94fd3e8a711d0 bugzilla: 51875 CVE: NA -------------------------------- commit b8135111 upstream. In the same way as Intel Tiger Lake TCSS (Type-C Subsystem) the Alder Lake TCSS xHCI needs to be runtime suspended whenever possible to allow the TCSS hardware block to enter D3cold and thus save energy. Cc: stable@vger.kernel.org Signed-off-by: NAbhijeet Rao <abhijeet.rao@intel.com> Signed-off-by: NNikunj A. Dadhania <nikunj.dadhania@intel.com> Signed-off-by: NAzhar Shaikh <azhar.shaikh@intel.com> Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com> Link: https://lore.kernel.org/r/20210512080816.866037-2-mathias.nyman@linux.intel.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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