powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440
The following changes add processing to initialize the Xilinx 16550 UART in the boot wrapper for Virtex targets without firmware. Normally the boot wrapper assumes that the serial port has already been initialized by firmware. The wrapper was also modified to add the 440 build. Signed-off-by: NJohn Linn <john.linn@xilinx.com> Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Showing
arch/powerpc/boot/virtex.c
0 → 100644
想要评论请 注册 或 登录