提交 d436a609 编写于 作者: L Lee Jones 提交者: Maxime Coquelin

ARM: DT: STi: STiH416: Add DT node for MiPHY365x

The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
上级 0f6c28b7
......@@ -19,5 +19,15 @@
bus-width = <8>;
non-removable;
};
miphy365x_phy: miphy365x@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};
phy_port1: port@fe38a000 {
st,pcie-tx-pol-inv;
};
};
};
};
......@@ -37,5 +37,15 @@
bus-width = <8>;
non-removable;
};
miphy365x_phy: miphy365x@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};
phy_port1: port@fe38a000 {
st,pcie-tx-pol-inv;
};
};
};
};
......@@ -9,6 +9,8 @@
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
#include <dt-bindings/phy/phy-miphy365x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
......@@ -278,5 +280,25 @@
clock-names = "mmc";
clocks = <&clk_s_a1_ls 8>;
};
miphy365x_phy: miphy365x@fe382000 {
compatible = "st,miphy365x-phy";
st,syscfg = <&syscfg_rear>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
phy_port0: port@fe382000 {
#phy-cells = <1>;
reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
reg-names = "sata", "pcie", "syscfg";
};
phy_port1: port@fe38a000 {
#phy-cells = <1>;
reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
reg-names = "sata", "pcie", "syscfg";
};
};
};
};
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