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提交 d2796743 编写于 作者: M Mark Einon 提交者： Greg Kroah-Hartman
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staging: et131x: Put all .c files into one big file 

Created one big .c file for the driver, moving the contents of all
driver .c files into it.
Signed-off-by: NMark Einon <mark.einon@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 cd8eca6f
展开全部 隐藏空白更改
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Showing with 5102 addition and 5862 deletion
drivers/staging/et131x/Makefile
浏览文件 @ d2796743
......@@ -3,14 +3,3 @@
#
obj-$(CONFIG_ET131X) += et131x.o
et131x-y := et1310_eeprom.o \
et1310_mac.o \
et1310_phy.o \
et1310_pm.o \
et1310_rx.o \
et1310_tx.o \
et131x_initpci.o \
et131x_ethtool.o \
et131x_isr.o \
et131x_netdev.o
drivers/staging/et131x/et1310_eeprom.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
*
*------------------------------------------------------------------------------
*
* et1310_eeprom.c - Code used to access the device's EEPROM
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_defs.h"
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <asm/system.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et131x_adapter.h"
#include "et131x.h"
/*
* EEPROM Defines
*/
/* LBCIF Register Groups (addressed via 32-bit offsets) */
#define LBCIF_DWORD0_GROUP 0xAC
#define LBCIF_DWORD1_GROUP 0xB0
/* LBCIF Registers (addressed via 8-bit offsets) */
#define LBCIF_ADDRESS_REGISTER 0xAC
#define LBCIF_DATA_REGISTER 0xB0
#define LBCIF_CONTROL_REGISTER 0xB1
#define LBCIF_STATUS_REGISTER 0xB2
/* LBCIF Control Register Bits */
#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
#define LBCIF_CONTROL_PAGE_WRITE 0x02
#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
#define LBCIF_CONTROL_I2C_WRITE 0x40
#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
/* LBCIF Status Register Bits */
#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
#define LBCIF_STATUS_I2C_IDLE 0x02
#define LBCIF_STATUS_ACK_ERROR 0x04
#define LBCIF_STATUS_GENERAL_ERROR 0x08
#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
#define LBCIF_STATUS_EEPROM_PRESENT 0x80
/* Miscellaneous Constraints */
#define MAX_NUM_REGISTER_POLLS 1000
#define MAX_NUM_WRITE_RETRIES 2
static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
{
u32 reg;
int i;
/*
* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
* bits 7,1:0 both equal to 1, at least once after reset.
* Subsequent operations need only to check that bits 1:0 are equal
* to 1 prior to starting a single byte read/write
*/
for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
/* Read registers grouped in DWORD1 */
if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
return -EIO;
/* I2C idle and Phy Queue Avail both true */
if ((reg & 0x3000) == 0x3000) {
if (status)
*status = reg;
return reg & 0xFF;
}
}
return -ETIMEDOUT;
}
/**
* eeprom_write - Write a byte to the ET1310's EEPROM
* @adapter: pointer to our private adapter structure
* @addr: the address to write
* @data: the value to write
*
* Returns 1 for a successful write.
*/
static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
{
struct pci_dev *pdev = adapter->pdev;
int index = 0;
int retries;
int err = 0;
int i2c_wack = 0;
int writeok = 0;
u32 status;
u32 val = 0;
/*
* For an EEPROM, an I2C single byte write is defined as a START
* condition followed by the device address, EEPROM address, one byte
* of data and a STOP condition. The STOP condition will trigger the
* EEPROM's internally timed write cycle to the nonvolatile memory.
* All inputs are disabled during this write cycle and the EEPROM will
* not respond to any access until the internal write is complete.
*/
err = eeprom_wait_ready(pdev, NULL);
if (err)
return err;
/*
* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
* and bits 1:0 both =0. Bit 5 should be set according to the
* type of EEPROM being accessed (1=two byte addressing, 0=one
* byte addressing).
*/
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
return -EIO;
i2c_wack = 1;
/* Prepare EEPROM address for Step 3 */
for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
/* Write the address to the LBCIF Address Register */
if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
break;
/*
* Write the data to the LBCIF Data Register (the I2C write
* will begin).
*/
if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
break;
/*
* Monitor bit 1:0 of the LBCIF Status Register. When bits
* 1:0 are both equal to 1, the I2C write has completed and the
* internal write cycle of the EEPROM is about to start.
* (bits 1:0 = 01 is a legal state while waiting from both
* equal to 1, but bits 1:0 = 10 is invalid and implies that
* something is broken).
*/
err = eeprom_wait_ready(pdev, &status);
if (err < 0)
return 0;
/*
* Check bit 3 of the LBCIF Status Register. If equal to 1,
* an error has occurred.Don't break here if we are revision
* 1, this is so we do a blind write for load bug.
*/
if ((status & LBCIF_STATUS_GENERAL_ERROR)
&& adapter->pdev->revision == 0)
break;
/*
* Check bit 2 of the LBCIF Status Register. If equal to 1 an
* ACK error has occurred on the address phase of the write.
* This could be due to an actual hardware failure or the
* EEPROM may still be in its internal write cycle from a
* previous write. This write operation was ignored and must be
*repeated later.
*/
if (status & LBCIF_STATUS_ACK_ERROR) {
/*
* This could be due to an actual hardware failure
* or the EEPROM may still be in its internal write
* cycle from a previous write. This write operation
* was ignored and must be repeated later.
*/
udelay(10);
continue;
}
writeok = 1;
break;
}
/*
* Set bit 6 of the LBCIF Control Register = 0.
*/
udelay(10);
while (i2c_wack) {
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
LBCIF_CONTROL_LBCIF_ENABLE))
writeok = 0;
/* Do read until internal ACK_ERROR goes away meaning write
* completed
*/
do {
pci_write_config_dword(pdev,
LBCIF_ADDRESS_REGISTER,
addr);
do {
pci_read_config_dword(pdev,
LBCIF_DATA_REGISTER, &val);
} while ((val & 0x00010000) == 0);
} while (val & 0x00040000);
if ((val & 0xFF00) != 0xC000 || index == 10000)
break;
index++;
}
return writeok ? 0 : -EIO;
}
/**
* eeprom_read - Read a byte from the ET1310's EEPROM
* @adapter: pointer to our private adapter structure
* @addr: the address from which to read
* @pdata: a pointer to a byte in which to store the value of the read
* @eeprom_id: the ID of the EEPROM
* @addrmode: how the EEPROM is to be accessed
*
* Returns 1 for a successful read
*/
static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
{
struct pci_dev *pdev = adapter->pdev;
int err;
u32 status;
/*
* A single byte read is similar to the single byte write, with the
* exception of the data flow:
*/
err = eeprom_wait_ready(pdev, NULL);
if (err)
return err;
/*
* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
* and bits 1:0 both =0. Bit 5 should be set according to the type
* of EEPROM being accessed (1=two byte addressing, 0=one byte
* addressing).
*/
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
LBCIF_CONTROL_LBCIF_ENABLE))
return -EIO;
/*
* Write the address to the LBCIF Address Register (I2C read will
* begin).
*/
if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
return -EIO;
/*
* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
* is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
* has occurred).
*/
err = eeprom_wait_ready(pdev, &status);
if (err < 0)
return err;
/*
* Regardless of error status, read data byte from LBCIF Data
* Register.
*/
*pdata = err;
/*
* Check bit 2 of the LBCIF Status Register. If = 1,
* then an error has occurred.
*/
return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
}
int et131x_init_eeprom(struct et131x_adapter *adapter)
{
struct pci_dev *pdev = adapter->pdev;
u8 eestatus;
/* We first need to check the EEPROM Status code located at offset
* 0xB2 of config space
*/
pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
&eestatus);
/* THIS IS A WORKAROUND:
* I need to call this function twice to get my card in a
* LG M1 Express Dual running. I tried also a msleep before this
* function, because I thougth there could be some time condidions
* but it didn't work. Call the whole function twice also work.
*/
if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
dev_err(&pdev->dev,
"Could not read PCI config space for EEPROM Status\n");
return -EIO;
}
/* Determine if the error(s) we care about are present. If they are
* present we need to fail.
*/
if (eestatus & 0x4C) {
int write_failed = 0;
if (pdev->revision == 0x01) {
int i;
static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
/* Re-write the first 4 bytes if we have an eeprom
* present and the revision id is 1, this fixes the
* corruption seen with 1310 B Silicon
*/
for (i = 0; i < 3; i++)
if (eeprom_write(adapter, i, eedata[i]) < 0)
write_failed = 1;
}
if (pdev->revision != 0x01 || write_failed) {
dev_err(&pdev->dev,
"Fatal EEPROM Status Error - 0x%04x\n", eestatus);
/* This error could mean that there was an error
* reading the eeprom or that the eeprom doesn't exist.
* We will treat each case the same and not try to
* gather additional information that normally would
* come from the eeprom, like MAC Address
*/
adapter->has_eeprom = 0;
return -EIO;
}
}
adapter->has_eeprom = 1;
/* Read the EEPROM for information regarding LED behavior. Refer to
* ET1310_phy.c, et131x_xcvr_init(), for its use.
*/
eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
if (adapter->eeprom_data[0] != 0xcd)
/* Disable all optional features */
adapter->eeprom_data[1] = 0x00;
return 0;
}
drivers/staging/et131x/et1310_mac.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
此差异已折叠。
drivers/staging/et131x/et1310_phy.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1310 and ET131x series MACs
*
* Copyright * 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
*
*------------------------------------------------------------------------------
*
* et1310_phy.c - Routines for configuring and accessing the PHY
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright * 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_defs.h"
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include <linux/random.h>
#include <linux/phy.h>
#include "et1310_phy.h"
#include "et131x_adapter.h"
#include "et1310_address_map.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
#include "et131x.h"
int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
{
struct net_device *netdev = bus->priv;
struct et131x_adapter *adapter = netdev_priv(netdev);
u16 value;
int ret;
ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
if (ret < 0)
return ret;
else
return value;
}
int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value)
{
struct net_device *netdev = bus->priv;
struct et131x_adapter *adapter = netdev_priv(netdev);
return et131x_mii_write(adapter, reg, value);
}
int et131x_mdio_reset(struct mii_bus *bus)
{
struct net_device *netdev = bus->priv;
struct et131x_adapter *adapter = netdev_priv(netdev);
et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
return 0;
}
int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
{
struct phy_device *phydev = adapter->phydev;
if (!phydev)
return -EIO;
return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
}
/**
* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
* @adapter: pointer to our private adapter structure
* @addr: the address of the transceiver
* @reg: the register to read
* @value: pointer to a 16-bit value in which the value will be stored
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
u8 reg, u16 *value)
{
struct mac_regs __iomem *mac = &adapter->regs->mac;
int status = 0;
u32 delay = 0;
u32 mii_addr;
u32 mii_cmd;
u32 mii_indicator;
/* Save a local copy of the registers we are dealing with so we can
* set them back
*/
mii_addr = readl(&mac->mii_mgmt_addr);
mii_cmd = readl(&mac->mii_mgmt_cmd);
/* Stop the current operation */
writel(0, &mac->mii_mgmt_cmd);
/* Set up the register we need to read from on the correct PHY */
writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
writel(0x1, &mac->mii_mgmt_cmd);
do {
udelay(50);
delay++;
mii_indicator = readl(&mac->mii_mgmt_indicator);
} while ((mii_indicator & MGMT_WAIT) && delay < 50);
/* If we hit the max delay, we could not read the register */
if (delay == 50) {
dev_warn(&adapter->pdev->dev,
"reg 0x%08x could not be read\n", reg);
dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
mii_indicator);
status = -EIO;
}
/* If we hit here we were able to read the register and we need to
* return the value to the caller */
*value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
/* Stop the read operation */
writel(0, &mac->mii_mgmt_cmd);
/* set the registers we touched back to the state at which we entered
* this function
*/
writel(mii_addr, &mac->mii_mgmt_addr);
writel(mii_cmd, &mac->mii_mgmt_cmd);
return status;
}
/**
* et131x_mii_write - Write to a PHY register through the MII interface of the MAC
* @adapter: pointer to our private adapter structure
* @reg: the register to read
* @value: 16-bit value to write
*
* FIXME: one caller in netdev still
*
* Return 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
{
struct mac_regs __iomem *mac = &adapter->regs->mac;
struct phy_device *phydev = adapter->phydev;
int status = 0;
u8 addr;
u32 delay = 0;
u32 mii_addr;
u32 mii_cmd;
u32 mii_indicator;
if (!phydev)
return -EIO;
addr = phydev->addr;
/* Save a local copy of the registers we are dealing with so we can
* set them back
*/
mii_addr = readl(&mac->mii_mgmt_addr);
mii_cmd = readl(&mac->mii_mgmt_cmd);
/* Stop the current operation */
writel(0, &mac->mii_mgmt_cmd);
/* Set up the register we need to write to on the correct PHY */
writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
/* Add the value to write to the registers to the mac */
writel(value, &mac->mii_mgmt_ctrl);
do {
udelay(50);
delay++;
mii_indicator = readl(&mac->mii_mgmt_indicator);
} while ((mii_indicator & MGMT_BUSY) && delay < 100);
/* If we hit the max delay, we could not write the register */
if (delay == 100) {
u16 tmp;
dev_warn(&adapter->pdev->dev,
"reg 0x%08x could not be written", reg);
dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
mii_indicator);
dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
readl(&mac->mii_mgmt_cmd));
et131x_mii_read(adapter, reg, &tmp);
status = -EIO;
}
/* Stop the write operation */
writel(0, &mac->mii_mgmt_cmd);
/*
* set the registers we touched back to the state at which we entered
* this function
*/
writel(mii_addr, &mac->mii_mgmt_addr);
writel(mii_cmd, &mac->mii_mgmt_cmd);
return status;
}
/**
* et1310_phy_power_down - PHY power control
* @adapter: device to control
* @down: true for off/false for back on
*
* one hundred, ten, one thousand megs
* How would you like to have your LAN accessed
* Can't you see that this code processed
* Phy power, phy power..
*/
void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
{
u16 data;
et131x_mii_read(adapter, MII_BMCR, &data);
data &= ~BMCR_PDOWN;
if (down)
data |= BMCR_PDOWN;
et131x_mii_write(adapter, MII_BMCR, data);
}
/* Still used from _mac for BIT_READ */
void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
u16 regnum, u16 bitnum, u8 *value)
{
u16 reg;
u16 mask = 0x0001 << bitnum;
/* Read the requested register */
et131x_mii_read(adapter, regnum, &reg);
switch (action) {
case TRUEPHY_BIT_READ:
*value = (reg & mask) >> bitnum;
break;
case TRUEPHY_BIT_SET:
et131x_mii_write(adapter, regnum, reg | mask);
break;
case TRUEPHY_BIT_CLEAR:
et131x_mii_write(adapter, regnum, reg & ~mask);
break;
default:
break;
}
}
/**
* et131x_xcvr_init - Init the phy if we are setting it into force mode
* @adapter: pointer to our private adapter structure
*
*/
void et131x_xcvr_init(struct et131x_adapter *adapter)
{
u16 imr;
u16 isr;
u16 lcr2;
et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
/* Set the link status interrupt only. Bad behavior when link status
* and auto neg are set, we run into a nested interrupt problem
*/
imr |= (ET_PHY_INT_MASK_AUTONEGSTAT &
ET_PHY_INT_MASK_LINKSTAT &
ET_PHY_INT_MASK_ENABLE);
et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
/* Set the LED behavior such that LED 1 indicates speed (off =
* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
* link and activity (on for link, blink off for activity).
*
* NOTE: Some customizations have been added here for specific
* vendors; The LED behavior is now determined by vendor data in the
* EEPROM. However, the above description is the default.
*/
if ((adapter->eeprom_data[1] & 0x4) == 0) {
et131x_mii_read(adapter, PHY_LED_2, &lcr2);
lcr2 &= (ET_LED2_LED_100TX & ET_LED2_LED_1000T);
lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
if ((adapter->eeprom_data[1] & 0x8) == 0)
lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
else
lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
et131x_mii_write(adapter, PHY_LED_2, lcr2);
}
}
drivers/staging/et131x/et1310_pm.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
*
*------------------------------------------------------------------------------
*
* et1310_pm.c - All power management related code (not completely implemented)
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_rx.h"
#include "et131x_adapter.h"
#include "et131x.h"
/**
* et1310_in_phy_coma - check if the device is in phy coma
* @adapter: pointer to our adapter structure
*
* Returns 0 if the device is not in phy coma, 1 if it is in phy coma
*/
int et1310_in_phy_coma(struct et131x_adapter *adapter)
{
u32 pmcsr;
pmcsr = readl(&adapter->regs->global.pm_csr);
return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
}
/**
* et1310_enable_phy_coma - called when network cable is unplugged
* @adapter: pointer to our adapter structure
*
* driver receive an phy status change interrupt while in D0 and check that
* phy_status is down.
*
* -- gate off JAGCore;
* -- set gigE PHY in Coma mode
* -- wake on phy_interrupt; Perform software reset JAGCore,
* re-initialize jagcore and gigE PHY
*
* Add D0-ASPM-PhyLinkDown Support:
* -- while in D0, when there is a phy_interrupt indicating phy link
* down status, call the MPSetPhyComa routine to enter this active
* state power saving mode
* -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
* indicating linkup status, call the MPDisablePhyComa routine to
* restore JAGCore and gigE PHY
*/
void et1310_enable_phy_coma(struct et131x_adapter *adapter)
{
unsigned long flags;
u32 pmcsr;
pmcsr = readl(&adapter->regs->global.pm_csr);
/* Save the GbE PHY speed and duplex modes. Need to restore this
* when cable is plugged back in
*/
/*
* TODO - when PM is re-enabled, check if we need to
* perform a similar task as this -
* adapter->pdown_speed = adapter->ai_force_speed;
* adapter->pdown_duplex = adapter->ai_force_duplex;
*/
/* Stop sending packets. */
spin_lock_irqsave(&adapter->send_hw_lock, flags);
adapter->flags |= fMP_ADAPTER_LOWER_POWER;
spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
/* Wait for outstanding Receive packets */
et131x_disable_txrx(adapter->netdev);
/* Gate off JAGCore 3 clock domains */
pmcsr &= ~ET_PMCSR_INIT;
writel(pmcsr, &adapter->regs->global.pm_csr);
/* Program gigE PHY in to Coma mode */
pmcsr |= ET_PM_PHY_SW_COMA;
writel(pmcsr, &adapter->regs->global.pm_csr);
}
/**
* et1310_disable_phy_coma - Disable the Phy Coma Mode
* @adapter: pointer to our adapter structure
*/
void et1310_disable_phy_coma(struct et131x_adapter *adapter)
{
u32 pmcsr;
pmcsr = readl(&adapter->regs->global.pm_csr);
/* Disable phy_sw_coma register and re-enable JAGCore clocks */
pmcsr |= ET_PMCSR_INIT;
pmcsr &= ~ET_PM_PHY_SW_COMA;
writel(pmcsr, &adapter->regs->global.pm_csr);
/* Restore the GbE PHY speed and duplex modes;
* Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
*/
/* TODO - when PM is re-enabled, check if we need to
* perform a similar task as this -
* adapter->ai_force_speed = adapter->pdown_speed;
* adapter->ai_force_duplex = adapter->pdown_duplex;
*/
/* Re-initialize the send structures */
et131x_init_send(adapter);
/* Reset the RFD list and re-start RU */
et131x_reset_recv(adapter);
/* Bring the device back to the state it was during init prior to
* autonegotiation being complete. This way, when we get the auto-neg
* complete interrupt, we can complete init by calling ConfigMacREGS2.
*/
et131x_soft_reset(adapter);
/* setup et1310 as per the documentation ?? */
et131x_adapter_setup(adapter);
/* Allow Tx to restart */
adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
et131x_enable_txrx(adapter->netdev);
}
drivers/staging/et131x/et1310_rx.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
此差异已折叠。
drivers/staging/et131x/et1310_tx.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
此差异已折叠。
drivers/staging/et131x/et131x.c 0 → 100644
浏览文件 @ d2796743
此差异已折叠。
drivers/staging/et131x/et131x.h
浏览文件 @ d2796743
/*
* Merged from files
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
......@@ -51,6 +49,66 @@
#define DRIVER_NAME "et131x"
#define DRIVER_VERSION "v2.0"
/* EEPROM defines */
/* LBCIF Register Groups (addressed via 32-bit offsets) */
#define LBCIF_DWORD0_GROUP 0xAC
#define LBCIF_DWORD1_GROUP 0xB0
/* LBCIF Registers (addressed via 8-bit offsets) */
#define LBCIF_ADDRESS_REGISTER 0xAC
#define LBCIF_DATA_REGISTER 0xB0
#define LBCIF_CONTROL_REGISTER 0xB1
#define LBCIF_STATUS_REGISTER 0xB2
/* LBCIF Control Register Bits */
#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
#define LBCIF_CONTROL_PAGE_WRITE 0x02
#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
#define LBCIF_CONTROL_I2C_WRITE 0x40
#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
/* LBCIF Status Register Bits */
#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
#define LBCIF_STATUS_I2C_IDLE 0x02
#define LBCIF_STATUS_ACK_ERROR 0x04
#define LBCIF_STATUS_GENERAL_ERROR 0x08
#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
#define LBCIF_STATUS_EEPROM_PRESENT 0x80
/* Miscellaneous Constraints */
#define MAX_NUM_REGISTER_POLLS 1000
#define MAX_NUM_WRITE_RETRIES 2
/* MAC defines */
#define COUNTER_WRAP_16_BIT 0x10000
#define COUNTER_WRAP_12_BIT 0x1000
/* PCI defines */
#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
/* ISR defines */
/*
* For interrupts, normal running is:
* rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
* watchdog_interrupt & txdma_xfer_done
*
* In both cases, when flow control is enabled for either Tx or bi-direction,
* we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
* buffer rings are running low.
*/
#define INT_MASK_DISABLE 0xffffffff
/* NOTE: Masking out MAC_STAT Interrupt for now...
* #define INT_MASK_ENABLE 0xfff6bf17
* #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
*/
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
/* et131x_eeprom.c */
int et131x_init_eeprom(struct et131x_adapter *adapter);
......
drivers/staging/et131x/et131x_ethtool.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
/*
* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "et131x_defs.h"
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/ethtool.h>
#include <linux/phy.h>
#include <linux/pci.h>
#include "et131x_adapter.h"
#include "et1310_phy.h"
#include "et131x.h"
static int et131x_get_settings(struct net_device *netdev,
struct ethtool_cmd *cmd)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
return phy_ethtool_gset(adapter->phydev, cmd);
}
static int et131x_set_settings(struct net_device *netdev,
struct ethtool_cmd *cmd)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
return phy_ethtool_sset(adapter->phydev, cmd);
}
static int et131x_get_regs_len(struct net_device *netdev)
{
#define ET131X_REGS_LEN 256
return ET131X_REGS_LEN * sizeof(u32);
}
static void et131x_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *regs_data)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
struct address_map __iomem *aregs = adapter->regs;
u32 *regs_buff = regs_data;
u32 num = 0;
memset(regs_data, 0, et131x_get_regs_len(netdev));
regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
adapter->pdev->device;
/* PHY regs */
et131x_mii_read(adapter, MII_BMCR, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_BMSR, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_PHYSID1, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_PHYSID2, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_LPA, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_EXPANSION, (u16 *)&regs_buff[num++]);
/* Autoneg next page transmit reg */
et131x_mii_read(adapter, 0x07, (u16 *)&regs_buff[num++]);
/* Link partner next page reg */
et131x_mii_read(adapter, 0x08, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_CTRL1000, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_STAT1000, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_ESTATUS, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_CONFIG, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LED_1, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LED_2, (u16 *)&regs_buff[num++]);
/* Global regs */
regs_buff[num++] = readl(&aregs->global.txq_start_addr);
regs_buff[num++] = readl(&aregs->global.txq_end_addr);
regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
regs_buff[num++] = readl(&aregs->global.pm_csr);
regs_buff[num++] = adapter->stats.interrupt_status;
regs_buff[num++] = readl(&aregs->global.int_mask);
regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
regs_buff[num++] = readl(&aregs->global.int_status_alias);
regs_buff[num++] = readl(&aregs->global.sw_reset);
regs_buff[num++] = readl(&aregs->global.slv_timer);
regs_buff[num++] = readl(&aregs->global.msi_config);
regs_buff[num++] = readl(&aregs->global.loopback);
regs_buff[num++] = readl(&aregs->global.watchdog_timer);
/* TXDMA regs */
regs_buff[num++] = readl(&aregs->txdma.csr);
regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
regs_buff[num++] = readl(&aregs->txdma.service_request);
regs_buff[num++] = readl(&aregs->txdma.service_complete);
regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
/* RXDMA regs */
regs_buff[num++] = readl(&aregs->rxdma.csr);
regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
}
#define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
static void et131x_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *info)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
}
static struct ethtool_ops et131x_ethtool_ops = {
.get_settings = et131x_get_settings,
.set_settings = et131x_set_settings,
.get_drvinfo = et131x_get_drvinfo,
.get_regs_len = et131x_get_regs_len,
.get_regs = et131x_get_regs,
.get_link = ethtool_op_get_link,
};
void et131x_set_ethtool_ops(struct net_device *netdev)
{
SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
}
drivers/staging/et131x/et131x_initpci.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
此差异已折叠。
drivers/staging/et131x/et131x_isr.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
此差异已折叠。
drivers/staging/et131x/et131x_netdev.c 已删除 100644 → 0
浏览文件 @ cd8eca6f
此差异已折叠。
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