dt-bindings: riscv: document cbom-block-size

The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.

So add the necessary property for the system to know the core's
block-size.
Reviewed-by: NAnup Patel <anup@brainfault.org>
Reviewed-by: NGuo Ren <guoren@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220706231536.2041855-3-heiko@sntech.deSigned-off-by: NPalmer Dabbelt <palmer@rivosinc.com>

Documentation/devicetree/bindings/riscv/cpus.yaml

@@ -63,6 +63,11 @@ properties:
       - riscv,sv48
       - riscv,none
 
+  riscv,cbom-block-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The blocksize in bytes for the Zicbom cache operations.
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture