ARM: mxs: add saif clock
Set pll0 as parent. Signed-off-by: NDong Aisheng <b29396@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>
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Set pll0 as parent. Signed-off-by: NDong Aisheng <b29396@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>