drm/amd/pp: Change activity_target for performance optimization on Polaris

And not support perDPM level optimization on Polaris, so
delete sclk activity_target array.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h

@@ -50,6 +50,6 @@
 #define SMU7_CGULVCONTROL_DFLT                      0x00007450
 #define SMU7_TARGETACTIVITY_DFLT                     50
 #define SMU7_MCLK_TARGETACTIVITY_DFLT                10
-
+#define SMU7_SCLK_TARGETACTIVITY_DFLT                30
 #endif
 

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

@@ -1485,6 +1485,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 	data->dll_default_on = false;
 	data->mclk_dpm0_activity_target = 0xa;
 	data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT;
+	data->sclk_activity_target = SMU7_SCLK_TARGETACTIVITY_DFLT;
 	data->vddc_vddgfx_delta = 300;
 	data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
 	data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h

@@ -290,6 +290,7 @@ struct smu7_hwmgr {
 	bool                                      use_pcie_performance_levels;
 	bool                                      use_pcie_power_saving_levels;
 	uint32_t                                  mclk_activity_target;
+	uint16_t                                  sclk_activity_target;
 	uint32_t                                  mclk_dpm0_activity_target;
 	uint32_t                                  low_sclk_interrupt_threshold;
 	uint32_t                                  last_mclk_dpm_enable_mask;

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

@@ -366,7 +366,6 @@ static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
 {
 	struct polaris10_smumgr *smu_data;
-	int i;
 
 	smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
 	if (smu_data == NULL)
@@ -377,9 +376,6 @@ static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
 	if (smu7_init(hwmgr))
 		return -EINVAL;
 
-	for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
-		smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-
 	return 0;
 }
 
@@ -1037,7 +1033,7 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 
 		result = polaris10_populate_single_graphic_level(hwmgr,
 				dpm_table->sclk_table.dpm_levels[i].value,
-				(uint16_t)smu_data->activity_target[i],
+				hw_data->sclk_activity_target,
 				&(smu_data->smc_state_table.GraphicsLevel[i]));
 		if (result)
 			return result;

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h

@@ -59,7 +59,6 @@ struct polaris10_smumgr {
 	struct SMU74_Discrete_PmFuses  power_tune_table;
 	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
 	const struct polaris10_pt_defaults       *power_tune_defaults;
-	uint32_t               activity_target[SMU74_MAX_LEVELS_GRAPHICS];
 	uint32_t               bif_sclk_table[SMU74_MAX_LEVELS_LINK];
 };