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提交 cdbb816b 编写于 作者: T Tao Zhou 提交者： Alex Deucher
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drm/amdgpu: remove check for CE in RAS error address query 

Only RAS UE error address is queried currently, no need to check CE status.
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 faf4d8e0
隐藏空白更改
内联 并排
Showing with 59 addition and 90 deletion
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
浏览文件 @ cdbb816b
...@@ -327,10 +327,9 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, ...@@ -327,10 +327,9 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
return; return;
} }
/* calculate error address if ue/ce error is detected */ /* calculate error address if ue error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
/* the lowest lsb bits should be ignored */ /* the lowest lsb bits should be ignored */
...@@ -343,10 +342,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, ...@@ -343,10 +342,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
ADDR_OF_256B_BLOCK(channel_index) | ADDR_OF_256B_BLOCK(channel_index) |
OFFSET_IN_256B_BLOCK(err_addr); OFFSET_IN_256B_BLOCK(err_addr);
/* we only save ue error information currently, ce is skipped */ amdgpu_umc_fill_error_record(err_data, err_addr,
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
== 1)
amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page, channel_index, umc_inst); retired_page, channel_index, umc_inst);
} }
......
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
浏览文件 @ cdbb816b
...@@ -209,10 +209,9 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, ...@@ -209,10 +209,9 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
if (!err_data->err_addr) if (!err_data->err_addr)
return; return;
/* calculate error address if ue/ce error is detected */ /* calculate error address if ue error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
...@@ -228,22 +227,18 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, ...@@ -228,22 +227,18 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
/* clear [C4 C3 C2] in soc physical address */ /* clear [C4 C3 C2] in soc physical address */
soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT); soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
/* we only save ue error information currently, ce is skipped */ /* loop for all possibilities of [C4 C3 C2] */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
== 1) { retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
/* loop for all possibilities of [C4 C3 C2] */ dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) { amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT); retired_page, channel_index, umc_inst);
dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
amdgpu_umc_fill_error_record(err_data, err_addr, /* shift R14 bit */
retired_page, channel_index, umc_inst); retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
/* shift R14 bit */ amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT); retired_page, channel_index, umc_inst);
dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page, channel_index, umc_inst);
}
} }
} }
} }
...@@ -481,10 +476,9 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, ...@@ -481,10 +476,9 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
channel_index = channel_index =
adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
/* calculate error address if ue/ce error is detected */ /* calculate error address if ue error is detected */
if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) ||
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) ||
mca_addr != UMC_INVALID_ADDR) { mca_addr != UMC_INVALID_ADDR) {
if (mca_addr == UMC_INVALID_ADDR) { if (mca_addr == UMC_INVALID_ADDR) {
err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
...@@ -505,23 +499,18 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, ...@@ -505,23 +499,18 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
/* clear [C4 C3 C2] in soc physical address */ /* clear [C4 C3 C2] in soc physical address */
soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT); soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
/* we only save ue error information currently, ce is skipped */ /* loop for all possibilities of [C4 C3 C2] */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
== 1 || retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
mca_addr != UMC_INVALID_ADDR) { dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
/* loop for all possibilities of [C4 C3 C2] */ amdgpu_umc_fill_error_record(err_data, err_addr,
for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) { retired_page, channel_index, umc_inst);
retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page); /* shift R14 bit */
amdgpu_umc_fill_error_record(err_data, err_addr, retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
retired_page, channel_index, umc_inst); dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
amdgpu_umc_fill_error_record(err_data, err_addr,
/* shift R14 bit */ retired_page, channel_index, umc_inst);
retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page, channel_index, umc_inst);
}
} }
} }
......
drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
浏览文件 @ cdbb816b
...@@ -208,7 +208,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, ...@@ -208,7 +208,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
{ {
uint64_t mc_umc_status_addr; uint64_t mc_umc_status_addr;
uint64_t mc_umc_status, err_addr; uint64_t mc_umc_status, err_addr;
uint32_t channel_index; uint64_t mc_umc_addrt0, na_err_addr_base;
uint64_t na_err_addr, retired_page_addr;
uint32_t channel_index, addr_lsb, col = 0;
int ret = 0;
mc_umc_status_addr = mc_umc_status_addr =
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
...@@ -229,13 +232,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, ...@@ -229,13 +232,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
umc_inst * adev->umc.channel_inst_num + umc_inst * adev->umc.channel_inst_num +
ch_inst]; ch_inst];
/* calculate error address if ue/ce error is detected */ /* calculate error address if ue error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
uint32_t addr_lsb;
uint64_t mc_umc_addrt0;
mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
...@@ -243,32 +243,24 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, ...@@ -243,32 +243,24 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
/* the lowest lsb bits should be ignored */ /* the lowest lsb bits should be ignored */
addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb); addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
err_addr &= ~((0x1ULL << addr_lsb) - 1); err_addr &= ~((0x1ULL << addr_lsb) - 1);
na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
/* we only save ue error information currently, ce is skipped */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) { /* loop for all possibilities of [C6 C5] in normal address. */
uint64_t na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT); for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
uint64_t na_err_addr, retired_page_addr; na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
uint32_t col = 0;
int ret = 0; /* Mapping normal error address to retired soc physical address. */
ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
/* loop for all possibilities of [C6 C5] in normal address. */ na_err_addr, &retired_page_addr);
for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) { if (ret) {
na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT); dev_err(adev->dev, "Failed to map pa from umc na.\n");
break;
/* Mapping normal error address to retired soc physical address. */
ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
na_err_addr, &retired_page_addr);
if (ret) {
dev_err(adev->dev, "Failed to map pa from umc na.\n");
break;
}
dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
retired_page_addr);
amdgpu_umc_fill_error_record(err_data, na_err_addr,
retired_page_addr, channel_index, umc_inst);
} }
dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
retired_page_addr);
amdgpu_umc_fill_error_record(err_data, na_err_addr,
retired_page_addr, channel_index, umc_inst);
} }
} }
......
drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
浏览文件 @ cdbb816b
...@@ -130,10 +130,9 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev, ...@@ -130,10 +130,9 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
if (!err_data->err_addr) if (!err_data->err_addr)
return; return;
/* calculate error address if ue/ce error is detected */ /* calculate error address if ue error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
...@@ -143,10 +142,7 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev, ...@@ -143,10 +142,7 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
ADDR_OF_256B_BLOCK(channel_index) | ADDR_OF_256B_BLOCK(channel_index) |
OFFSET_IN_256B_BLOCK(err_addr); OFFSET_IN_256B_BLOCK(err_addr);
/* we only save ue error information currently, ce is skipped */ amdgpu_umc_fill_error_record(err_data, err_addr,
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
== 1)
amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page, channel_index, umc_inst); retired_page, channel_index, umc_inst);
} }
} }
...@@ -343,10 +339,9 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, ...@@ -343,10 +339,9 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
return; return;
} }
/* calculate error address if ue/ce error is detected */ /* calculate error address if ue error is detected */
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
/* the lowest lsb bits should be ignored */ /* the lowest lsb bits should be ignored */
...@@ -359,10 +354,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, ...@@ -359,10 +354,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
ADDR_OF_256B_BLOCK(channel_index) | ADDR_OF_256B_BLOCK(channel_index) |
OFFSET_IN_256B_BLOCK(err_addr); OFFSET_IN_256B_BLOCK(err_addr);
/* we only save ue error information currently, ce is skipped */ amdgpu_umc_fill_error_record(err_data, err_addr,
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
== 1)
amdgpu_umc_fill_error_record(err_data, err_addr,
retired_page, channel_index, umc_inst); retired_page, channel_index, umc_inst);
} }
......
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