提交 ccb8b12c 编写于 作者: S Stéphane Marchesin 提交者: Thierry Reding

drm/tegra: sor - Remove pixel clock rounding

The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.
Signed-off-by: NStéphane Marchesin <marcheu@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>
上级 1b0c7b48
......@@ -876,9 +876,6 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output,
struct tegra_sor *sor = to_sor(output);
int err;
/* round to next MHz */
pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000;
err = clk_set_parent(clk, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to set parent clock: %d\n", err);
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册