提交 cad73da2 编写于 作者: G Gregory Herrero 提交者: Felipe Balbi

usb: dwc2: host: clear pending interrupts prior hibernation

If an interrupt rises during hibernation process, dwc2 will assert
interrupt line to interrupt controller. If interrupt is level
sensitive, interrupt handler will be called in a loop because dwc2
will not be able to clear it while controller is hibernated.
Thus, clear all controller interrupts before hibernation entry.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
上级 5bbf6ce0
......@@ -398,6 +398,12 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
}
}
/*
* Clear any pending interrupts since dwc2 will not be able to
* clear them after entering hibernation.
*/
dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
/* Put the controller in low power state */
pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
......
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