提交 ca3fd11a 编写于 作者: R Randy Dunlap 提交者: Zheng Zengkai

ptp: dp83640: don't define PAGE0

stable inclusion
from stable-5.10.68
commit f6f80766558b72d59bd7a25519abc55c71c126c7
bugzilla: 182671 https://gitee.com/openeuler/kernel/issues/I4EWUH

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f6f80766558b72d59bd7a25519abc55c71c126c7

--------------------------------

commit 7366c23f upstream.

Building dp83640.c on arch/parisc/ produces a build warning for
PAGE0 being redefined. Since the macro is not used in the dp83640
driver, just make it a comment for documentation purposes.

In file included from ../drivers/net/phy/dp83640.c:23:
../drivers/net/phy/dp83640_reg.h:8: warning: "PAGE0" redefined
    8 | #define PAGE0                     0x0000
                 from ../drivers/net/phy/dp83640.c:11:
../arch/parisc/include/asm/page.h:187: note: this is the location of the previous definition
  187 | #define PAGE0   ((struct zeropage *)__PAGE_OFFSET)

Fixes: cb646e2b ("ptp: Added a clock driver for the National Semiconductor PHYTER.")
Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Cc: Richard Cochran <richard.cochran@omicron.at>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20210913220605.19682-1-rdunlap@infradead.orgSigned-off-by: NJakub Kicinski <kuba@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Acked-by: NWeilong Chen <chenweilong@huawei.com>
Signed-off-by: NChen Jun <chenjun102@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
上级 c73505b6
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
#ifndef HAVE_DP83640_REGISTERS #ifndef HAVE_DP83640_REGISTERS
#define HAVE_DP83640_REGISTERS #define HAVE_DP83640_REGISTERS
#define PAGE0 0x0000 /* #define PAGE0 0x0000 */
#define PHYCR2 0x001c /* PHY Control Register 2 */ #define PHYCR2 0x001c /* PHY Control Register 2 */
#define PAGE4 0x0004 #define PAGE4 0x0004
......
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