clk: mediatek: add the option for determining PLL source clock
Since the previous setup always sets the PLL using crystal 26MHz, this doesn't always happen in every MediaTek platform. So the patch added flexibility for assigning extra member for determining the PLL source clock. Signed-off-by: NChen Zhong <chen.zhong@mediatek.com> Signed-off-by: NSean Wang <sean.wang@mediatek.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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