提交 c8c959f6 编写于 作者: J Jiansong Chen 提交者: Alex Deucher

drm/amdgpu: initialize IP offset for navy_flounder

since navy_flounder has the same ip offset with sienna_cichlid,
follow sienna_cichlid setting for the moment.
Signed-off-by: NJiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: NTao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 543aa259
......@@ -424,6 +424,7 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
navi12_reg_base_init(adev);
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
sienna_cichlid_reg_base_init(adev);
break;
default:
......
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