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提交 bc3771fa 编写于 作者: F fengsheng 提交者： Yang Yingliang
浏览文件
操作

drivers : remove drivers/soc/hisilicon/sysctl 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4IYWW?from=project-issue
CVE: NA

------------------------------------------------------------

This driver is not in use. Remove it.
Signed-off-by: Nfengsheng <fengsheng5@huawei.com>
Reviewed-by: Nlidongming <lidongming5@huawei.com>
Reviewed-by: Nouyang delong <ouyangdelong@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 463a23d0
展开全部 隐藏空白更改
内联 并排
Showing with 0 addition and 4267 deletion
MAINTAINERS
浏览文件 @ bc3771fa
......@@ -16332,11 +16332,6 @@ S: Buried alive in reporters
F: *
F: */
HISILICON SYSCTRL DRIVER
M: Feng Sheng <fengsheng5@huawei.com>
S: Maintained
F: drivers/soc/hisilicon/sysctl/
HISILICON IO_MGMT SUBSYSTEM RDE DRIVER
M: hucheng Hu(Cheng) <hucheng.hu@huawei.com>
S: Maintained
......
arch/arm64/configs/hulk_defconfig
浏览文件 @ bc3771fa
......@@ -280,7 +280,6 @@ CONFIG_ARCH_XGENE=y
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y
CONFIG_SOC_HISILICON_SYSCTL=m
#
# Enable Livepatch
......
arch/arm64/configs/openeuler_defconfig
浏览文件 @ bc3771fa
......@@ -5011,7 +5011,6 @@ CONFIG_ARM_SMMU_V3=y
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
CONFIG_SOC_HISILICON_SYSCTL=m
# CONFIG_PM_DEVFREQ is not set
CONFIG_EXTCON=y
......
arch/arm64/configs/syzkaller_defconfig
浏览文件 @ bc3771fa
......@@ -280,7 +280,6 @@ CONFIG_ARCH_XGENE=y
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y
CONFIG_SOC_HISILICON_SYSCTL=m
#
# Enable Livepatch
#
......
arch/x86/configs/openeuler_defconfig
浏览文件 @ bc3771fa
......@@ -6168,7 +6168,6 @@ CONFIG_IRQ_REMAP=y
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
CONFIG_SOC_HISILICON_SYSCTL=m
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
......
arch/x86/configs/storage_ci_defconfig
浏览文件 @ bc3771fa
......@@ -2389,7 +2389,6 @@ CONFIG_PCC=y
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
CONFIG_SOC_HISILICON_SYSCTL=m
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
......
drivers/soc/Kconfig
浏览文件 @ bc3771fa
......@@ -18,6 +18,5 @@ source "drivers/soc/ux500/Kconfig"
source "drivers/soc/versatile/Kconfig"
source "drivers/soc/xilinx/Kconfig"
source "drivers/soc/zte/Kconfig"
source "drivers/soc/hisilicon/Kconfig"
endmenu
drivers/soc/Makefile
浏览文件 @ bc3771fa
......@@ -25,4 +25,3 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_PLAT_VERSATILE) += versatile/
obj-y += xilinx/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-y += hisilicon/
drivers/soc/hisilicon/Kconfig 已删除 100644 → 0
浏览文件 @ 463a23d0
source "drivers/soc/hisilicon/sysctl/Kconfig"
drivers/soc/hisilicon/sysctl/Kconfig 已删除 100644 → 0
浏览文件 @ 463a23d0
config SOC_HISILICON_SYSCTL
tristate
depends on ACPI_APEI_GHES
default m
\ No newline at end of file
drivers/soc/hisilicon/sysctl/Makefile 已删除 100644 → 0
浏览文件 @ 463a23d0
his_sysctl-objs := sysctl_drv.o sysctl_local_ras.o sysctl_dfx.o sysctl_pmbus.o
obj-$(CONFIG_SOC_HISILICON_SYSCTL) += his_sysctl.o
drivers/soc/hisilicon/sysctl/dmc_c_union_define.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __DMC_C_UNION_DEFINE_H__
#define __DMC_C_UNION_DEFINE_H__
/* Define the union dmc_ddrc_u_cfg_ecc */
typedef union {
/* Define the struct bits */
struct {
unsigned int ecc_en : 1 ; /* [0] */
unsigned int reserved_0 : 3 ; /* [3..1] */
unsigned int eccwb_en : 1 ; /* [4] */
unsigned int reserved_1 : 3 ; /* [7..5] */
unsigned int ecc_byp : 1 ; /* [8] */
unsigned int ecc_msk : 1 ; /* [9] */
unsigned int reserved_2 : 2 ; /* [11..10] */
unsigned int ras_en : 1 ; /* [12] */
unsigned int ras_bps : 1 ; /* [13] */
unsigned int poison_en : 1 ; /* [14] */
unsigned int poison_chk_type : 1 ; /* [15] */
unsigned int reserved_3 : 16 ; /* [31..16] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} dmc_ddrc_u_cfg_ecc;
#endif /* __DMC_C_UNION_DEFINE_H__ */
drivers/soc/hisilicon/sysctl/dmc_reg_offset.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __DMC_REG_OFFSET_H__
#define __DMC_REG_OFFSET_H__
/* DMC Base address of Module's Register */
#define DMC_DMC_BASE (0x0)
/******************************************************************************/
/* xxx DMC Registers' Definitions */
/******************************************************************************/
#define DMC_DMC_DDRC_CTRL_SREF_REG (DMC_DMC_BASE + 0x0)
#define DMC_DMC_DDRC_CTRL_INIT_REG (DMC_DMC_BASE + 0x4)
#define DMC_DMC_DDRC_CTRL_DDRRST_REG (DMC_DMC_BASE + 0x8)
#define DMC_DMC_DDRC_CTRL_SFC_REG (DMC_DMC_BASE + 0xC)
#define DMC_DMC_DDRC_CTRL_PERF_REG (DMC_DMC_BASE + 0x10)
#define DMC_DMC_DDRC_CTRL_MTEST_REG (DMC_DMC_BASE + 0x14)
#define DMC_DMC_DDRC_CFG_LP_REG (DMC_DMC_BASE + 0x1C)
#define DMC_DMC_DDRC_CFG_SREF_REG (DMC_DMC_BASE + 0x20)
#define DMC_DMC_DDRC_CFG_PD_REG (DMC_DMC_BASE + 0x28)
#define DMC_DMC_DDRC_CFG_AREF_REG (DMC_DMC_BASE + 0x2C)
#define DMC_DMC_DDRC_CFG_ECC_REG (DMC_DMC_BASE + 0x30)
#define DMC_DMC_DDRC_CFG_ERRINJ_REG (DMC_DMC_BASE + 0x34)
#define DMC_DMC_DDRC_CFG_FIFO_ERRINJ_REG (DMC_DMC_BASE + 0x38)
#define DMC_DMC_DDRC_CFG_OPENPAGE_REG (DMC_DMC_BASE + 0x3C)
#define DMC_DMC_DDRC_CFG_WORKMODE_REG (DMC_DMC_BASE + 0x40)
#define DMC_DMC_DDRC_CFG_WORKMODE2_REG (DMC_DMC_BASE + 0x44)
#define DMC_DMC_DDRC_CFG_WORKMODE3_REG (DMC_DMC_BASE + 0x48)
#define DMC_DMC_DDRC_CFG_DDRMODE_REG (DMC_DMC_BASE + 0x50)
#define DMC_DMC_DDRC_CFG_DIMM_REG (DMC_DMC_BASE + 0x54)
#define DMC_DMC_DDRC_CFG_SCRAMB_REG (DMC_DMC_BASE + 0x58)
#define DMC_DMC_DDRC_CFG_RNKVOL_REG (DMC_DMC_BASE + 0x60)
#define DMC_DMC_DDRC_CFG_ODT_REG (DMC_DMC_BASE + 0xA0)
#define DMC_DMC_DDRC_CFG_CA_ODT_REG (DMC_DMC_BASE + 0xE0)
#define DMC_DMC_DDRC_CFG_TIMING0_REG (DMC_DMC_BASE + 0x100)
#define DMC_DMC_DDRC_CFG_TIMING1_REG (DMC_DMC_BASE + 0x104)
#define DMC_DMC_DDRC_CFG_TIMING2_REG (DMC_DMC_BASE + 0x108)
#define DMC_DMC_DDRC_CFG_TIMING3_REG (DMC_DMC_BASE + 0x10C)
#define DMC_DMC_DDRC_CFG_TIMING4_REG (DMC_DMC_BASE + 0x110)
#define DMC_DMC_DDRC_CFG_TIMING5_REG (DMC_DMC_BASE + 0x114)
#define DMC_DMC_DDRC_CFG_TIMING6_REG (DMC_DMC_BASE + 0x118)
#define DMC_DMC_DDRC_CFG_TIMING7_REG (DMC_DMC_BASE + 0x11C)
#define DMC_DMC_DDRC_CFG_TIMING8_REG (DMC_DMC_BASE + 0x120)
#define DMC_DMC_DDRC_CFG_NXT_TIMING0_REG (DMC_DMC_BASE + 0x124)
#define DMC_DMC_DDRC_CFG_NXT_TIMING1_REG (DMC_DMC_BASE + 0x128)
#define DMC_DMC_DDRC_CFG_NXT_TIMING2_REG (DMC_DMC_BASE + 0x12C)
#define DMC_DMC_DDRC_CFG_NXT_TIMING3_REG (DMC_DMC_BASE + 0x130)
#define DMC_DMC_DDRC_CFG_NXT_TIMING4_REG (DMC_DMC_BASE + 0x134)
#define DMC_DMC_DDRC_CFG_NXT_TIMING5_REG (DMC_DMC_BASE + 0x138)
#define DMC_DMC_DDRC_CFG_NXT_TIMING6_REG (DMC_DMC_BASE + 0x13C)
#define DMC_DMC_DDRC_CFG_NXT_TIMING7_REG (DMC_DMC_BASE + 0x140)
#define DMC_DMC_DDRC_CFG_NXT_TIMING8_REG (DMC_DMC_BASE + 0x144)
#define DMC_DMC_DDRC_CFG_BLDATA_REG (DMC_DMC_BASE + 0x148)
#define DMC_DMC_DDRC_CFG_DMCLVL_REG (DMC_DMC_BASE + 0x14C)
#define DMC_DMC_DDRC_CFG_TIMEOUT_REG (DMC_DMC_BASE + 0x150)
#define DMC_DMC_DDRC_CFG_QOS_REG (DMC_DMC_BASE + 0x154)
#define DMC_DMC_DDRC_CFG_EXMBIST_CMD_REG (DMC_DMC_BASE + 0x158)
#define DMC_DMC_DDRC_CFG_EXMBIST_DAT_REG (DMC_DMC_BASE + 0x15C)
#define DMC_DMC_DDRC_CFG_MBIST_REG (DMC_DMC_BASE + 0x160)
#define DMC_DMC_DDRC_CFG_EXMBIST_CLK_MODE_REG (DMC_DMC_BASE + 0x164)
#define DMC_DMC_DDRC_CFG_OSC_PRD_REG (DMC_DMC_BASE + 0x178)
#define DMC_DMC_DDRC_CFG_OSC_CFG_REG (DMC_DMC_BASE + 0x17C)
#define DMC_DMC_DDRC_CFG_TRAIN_REG (DMC_DMC_BASE + 0x180)
#define DMC_DMC_DDRC_CFG_DFI_LAT0_REG (DMC_DMC_BASE + 0x184)
#define DMC_DMC_DDRC_CFG_DFI_LAT1_REG (DMC_DMC_BASE + 0x188)
#define DMC_DMC_DDRC_CFG_REC0_REG (DMC_DMC_BASE + 0x190)
#define DMC_DMC_DDRC_CFG_REC1_REG (DMC_DMC_BASE + 0x194)
#define DMC_DMC_DDRC_CFG_CRC_REG (DMC_DMC_BASE + 0x198)
#define DMC_DMC_DDRC_CFG_CRC_ERRINJ0_REG (DMC_DMC_BASE + 0x1A0)
#define DMC_DMC_DDRC_CFG_CRC_ERRINJ1_REG (DMC_DMC_BASE + 0x1A4)
#define DMC_DMC_DDRC_CFG_PAR_ERRINJ0_REG (DMC_DMC_BASE + 0x1A8)
#define DMC_DMC_DDRC_CFG_PAR_ERRINJ1_REG (DMC_DMC_BASE + 0x1AC)
#define DMC_DMC_DDRC_CFG_DDRPHY_REG (DMC_DMC_BASE + 0x200)
#define DMC_DMC_DDRC_CFG_AGING_REG (DMC_DMC_BASE + 0x204)
#define DMC_DMC_DDRC_CFG_SFC_TIM_REG (DMC_DMC_BASE + 0x20C)
#define DMC_DMC_DDRC_CFG_SFC_REG (DMC_DMC_BASE + 0x210)
#define DMC_DMC_DDRC_CFG_SFC_ADDR0_REG (DMC_DMC_BASE + 0x214)
#define DMC_DMC_DDRC_CFG_SFC_ADDR1_REG (DMC_DMC_BASE + 0x218)
#define DMC_DMC_DDRC_CFG_SFC_WDATA_REG (DMC_DMC_BASE + 0x21C)
#define DMC_DMC_DDRC_CFG_SFC_WCTRL_REG (DMC_DMC_BASE + 0x220)
#define DMC_DMC_DDRC_CFG_SFC_MASK0_REG (DMC_DMC_BASE + 0x224)
#define DMC_DMC_DDRC_CFG_SFC_MASK1_REG (DMC_DMC_BASE + 0x228)
#define DMC_DMC_DDRC_CFG_TMON_REG (DMC_DMC_BASE + 0x240)
#define DMC_DMC_DDRC_CFG_TMON_RANK_REG (DMC_DMC_BASE + 0x244)
#define DMC_DMC_DDRC_CFG_TMON_AREF_REG (DMC_DMC_BASE + 0x248)
#define DMC_DMC_DDRC_CFG_EXRESP_REG (DMC_DMC_BASE + 0x24C)
#define DMC_DMC_DDRC_CFG_MRR_MAP_REG (DMC_DMC_BASE + 0x250)
#define DMC_DMC_DDRC_CFG_STADAT_REG (DMC_DMC_BASE + 0x254)
#define DMC_DMC_DDRC_CFG_DATMIN_REG (DMC_DMC_BASE + 0x258)
#define DMC_DMC_DDRC_CFG_DATMAX_REG (DMC_DMC_BASE + 0x25C)
#define DMC_DMC_DDRC_CFG_STACMD_REG (DMC_DMC_BASE + 0x260)
#define DMC_DMC_DDRC_CFG_CMDMIN_REG (DMC_DMC_BASE + 0x264)
#define DMC_DMC_DDRC_CFG_CMDMAX_REG (DMC_DMC_BASE + 0x268)
#define DMC_DMC_DDRC_CFG_PERF_REG (DMC_DMC_BASE + 0x26C)
#define DMC_DMC_DDRC_CFG_STAID_REG (DMC_DMC_BASE + 0x270)
#define DMC_DMC_DDRC_CFG_STAIDMSK_REG (DMC_DMC_BASE + 0x274)
#define DMC_DMC_DDRC_CFG_DUM_EN_REG (DMC_DMC_BASE + 0x278)
#define DMC_DMC_DDRC_CFG_DUM_CFG_REG (DMC_DMC_BASE + 0x27C)
#define DMC_DMC_DDRC_INTMSK_REG (DMC_DMC_BASE + 0x280)
#define DMC_DMC_DDRC_RINT_REG (DMC_DMC_BASE + 0x284)
#define DMC_DMC_DDRC_INTSTS_REG (DMC_DMC_BASE + 0x288)
#define DMC_DMC_DDRC_CURR_STATUS_REG (DMC_DMC_BASE + 0x290)
#define DMC_DMC_DDRC_CURR_FUNC_REG (DMC_DMC_BASE + 0x294)
#define DMC_DMC_DDRC_CURR_FUNC2_REG (DMC_DMC_BASE + 0x298)
#define DMC_DMC_DDRC_CURR_FUNC3_REG (DMC_DMC_BASE + 0x29C)
#define DMC_DMC_DDRC_CURR_EXECST_REG (DMC_DMC_BASE + 0x2A0)
#define DMC_DMC_DDRC_CURR_WGFIFOST_REG (DMC_DMC_BASE + 0x2A4)
#define DMC_DMC_DDRC_CFG_ECC_CTRL_REG (DMC_DMC_BASE + 0x2A8)
#define DMC_DMC_DDRC_HIS_SERR_ID_REG (DMC_DMC_BASE + 0x2AC)
#define DMC_DMC_DDRC_HIS_SERR_ADR0_REG (DMC_DMC_BASE + 0x2D0)
#define DMC_DMC_DDRC_HIS_SERR_ADR1_REG (DMC_DMC_BASE + 0x2D4)
#define DMC_DMC_DDRC_HIS_SERR_RDATA0_REG (DMC_DMC_BASE + 0x2D8)
#define DMC_DMC_DDRC_HIS_SERR_RDATA1_REG (DMC_DMC_BASE + 0x2DC)
#define DMC_DMC_DDRC_HIS_SERR_RDATA2_REG (DMC_DMC_BASE + 0x2E0)
#define DMC_DMC_DDRC_HIS_SERR_RDATA3_REG (DMC_DMC_BASE + 0x2E4)
#define DMC_DMC_DDRC_HIS_SERR_RDATA4_REG (DMC_DMC_BASE + 0x2E8)
#define DMC_DMC_DDRC_HIS_SERR_RDATA5_REG (DMC_DMC_BASE + 0x2EC)
#define DMC_DMC_DDRC_HIS_SERR_RDATA6_REG (DMC_DMC_BASE + 0x2F0)
#define DMC_DMC_DDRC_HIS_SERR_RDATA7_REG (DMC_DMC_BASE + 0x2F4)
#define DMC_DMC_DDRC_HIS_SERR_RDATA8_REG (DMC_DMC_BASE + 0x2F8)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA0_REG (DMC_DMC_BASE + 0x2FC)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA1_REG (DMC_DMC_BASE + 0x300)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA2_REG (DMC_DMC_BASE + 0x304)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA3_REG (DMC_DMC_BASE + 0x308)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA4_REG (DMC_DMC_BASE + 0x30C)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA5_REG (DMC_DMC_BASE + 0x310)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA6_REG (DMC_DMC_BASE + 0x314)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA7_REG (DMC_DMC_BASE + 0x318)
#define DMC_DMC_DDRC_HIS_SERR_EXPDATA8_REG (DMC_DMC_BASE + 0x31C)
#define DMC_DMC_DDRC_HIS_MERR_ADR0_REG (DMC_DMC_BASE + 0x320)
#define DMC_DMC_DDRC_HIS_MERR_ADR1_REG (DMC_DMC_BASE + 0x324)
#define DMC_DMC_DDRC_HIS_MERR_ID_REG (DMC_DMC_BASE + 0x328)
#define DMC_DMC_DDRC_HIS_MERR_RDATA0_REG (DMC_DMC_BASE + 0x330)
#define DMC_DMC_DDRC_HIS_MERR_RDATA1_REG (DMC_DMC_BASE + 0x334)
#define DMC_DMC_DDRC_HIS_MERR_RDATA2_REG (DMC_DMC_BASE + 0x338)
#define DMC_DMC_DDRC_HIS_MERR_RDATA3_REG (DMC_DMC_BASE + 0x33C)
#define DMC_DMC_DDRC_HIS_MERR_RDATA4_REG (DMC_DMC_BASE + 0x340)
#define DMC_DMC_DDRC_HIS_MERR_RDATA5_REG (DMC_DMC_BASE + 0x344)
#define DMC_DMC_DDRC_HIS_MERR_RDATA6_REG (DMC_DMC_BASE + 0x348)
#define DMC_DMC_DDRC_HIS_MERR_RDATA7_REG (DMC_DMC_BASE + 0x34C)
#define DMC_DMC_DDRC_HIS_MERR_RDATA8_REG (DMC_DMC_BASE + 0x350)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA0_REG (DMC_DMC_BASE + 0x354)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA1_REG (DMC_DMC_BASE + 0x358)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA2_REG (DMC_DMC_BASE + 0x35C)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA3_REG (DMC_DMC_BASE + 0x360)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA4_REG (DMC_DMC_BASE + 0x364)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA5_REG (DMC_DMC_BASE + 0x368)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA6_REG (DMC_DMC_BASE + 0x36C)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA7_REG (DMC_DMC_BASE + 0x370)
#define DMC_DMC_DDRC_HIS_MERR_EXPDATA8_REG (DMC_DMC_BASE + 0x374)
#define DMC_DMC_DDRC_HIS_SERRCNT_REG (DMC_DMC_BASE + 0x378)
#define DMC_DMC_DDRC_HIS_MERRCNT_REG (DMC_DMC_BASE + 0x37C)
#define DMC_DMC_DDRC_HIS_FLUX_WR_REG (DMC_DMC_BASE + 0x380)
#define DMC_DMC_DDRC_HIS_FLUX_RD_REG (DMC_DMC_BASE + 0x384)
#define DMC_DMC_DDRC_HIS_FLUX_WCMD_REG (DMC_DMC_BASE + 0x388)
#define DMC_DMC_DDRC_HIS_FLUX_RCMD_REG (DMC_DMC_BASE + 0x38C)
#define DMC_DMC_DDRC_HIS_FLUXID_WR_REG (DMC_DMC_BASE + 0x390)
#define DMC_DMC_DDRC_HIS_FLUXID_RD_REG (DMC_DMC_BASE + 0x394)
#define DMC_DMC_DDRC_HIS_FLUXID_WCMD_REG (DMC_DMC_BASE + 0x398)
#define DMC_DMC_DDRC_HIS_FLUXID_RCMD_REG (DMC_DMC_BASE + 0x39C)
#define DMC_DMC_DDRC_HIS_WLATCNT0_REG (DMC_DMC_BASE + 0x3A0)
#define DMC_DMC_DDRC_HIS_WLATCNT1_REG (DMC_DMC_BASE + 0x3A4)
#define DMC_DMC_DDRC_HIS_RLATCNT0_REG (DMC_DMC_BASE + 0x3A8)
#define DMC_DMC_DDRC_HIS_RLATCNT1_REG (DMC_DMC_BASE + 0x3AC)
#define DMC_DMC_DDRC_HIS_INHERE_RLAT_CNT_REG (DMC_DMC_BASE + 0x3B0)
#define DMC_DMC_DDRC_STAT_RPT_REG (DMC_DMC_BASE + 0x3B4)
#define DMC_DMC_DDRC_HIS_CMD_SUM_REG (DMC_DMC_BASE + 0x3B8)
#define DMC_DMC_DDRC_HIS_DAT_SUM_REG (DMC_DMC_BASE + 0x3BC)
#define DMC_DMC_DDRC_HIS_PRE_CMD_REG (DMC_DMC_BASE + 0x3C0)
#define DMC_DMC_DDRC_HIS_ACT_CMD_REG (DMC_DMC_BASE + 0x3C4)
#define DMC_DMC_DDRC_HIS_BNK_CHG_REG (DMC_DMC_BASE + 0x3C8)
#define DMC_DMC_DDRC_HIS_RNK_CHG_REG (DMC_DMC_BASE + 0x3CC)
#define DMC_DMC_DDRC_HIS_RW_CHG_REG (DMC_DMC_BASE + 0x3D0)
#define DMC_DMC_DDRC_HIS_TMON_ERR_REG (DMC_DMC_BASE + 0x3E0)
#define DMC_DMC_DDRC_HIS_RERR_ADDRL_REG (DMC_DMC_BASE + 0x3F0)
#define DMC_DMC_DDRC_HIS_RERR_ADDRH_REG (DMC_DMC_BASE + 0x3F4)
#define DMC_DMC_DDRC_HIS_RERR_ID_REG (DMC_DMC_BASE + 0x3F8)
#define DMC_DMC_DDRC_HIS_RERR_CNT_REG (DMC_DMC_BASE + 0x3FC)
#define DMC_DMC_DDRC_HIS_REC_ERR0_REG (DMC_DMC_BASE + 0x400)
#define DMC_DMC_DDRC_HIS_REC_ERR1_REG (DMC_DMC_BASE + 0x404)
#define DMC_DMC_DDRC_HIS_EXMBIST_STATUS_REG (DMC_DMC_BASE + 0x40C)
#define DMC_DMC_DDRC_HIS_SFC_RDATA_REG (DMC_DMC_BASE + 0x4A8)
#define DMC_DMC_DDRC_SFC_RCTRL_REG (DMC_DMC_BASE + 0x4AC)
#define DMC_DMC_DDRC_HIS_SFC_RDATA0_DBI_REG (DMC_DMC_BASE + 0x4C8)
#define DMC_DMC_DDRC_HIS_SFC_RDATA1_DBI_REG (DMC_DMC_BASE + 0x4CC)
#define DMC_DMC_DDRC_HIS_SFC_RDATA_ECC_DBI_REG (DMC_DMC_BASE + 0x4D0)
#define DMC_DMC_DDRC_FUNC_STAT0_REG (DMC_DMC_BASE + 0x4D4)
#define DMC_DMC_DDRC_FUNC_STAT1_REG (DMC_DMC_BASE + 0x4D8)
#define DMC_DMC_DDRC_FUNC_STAT2_REG (DMC_DMC_BASE + 0x4DC)
#define DMC_DMC_DDRC_FUNC_STAT3_REG (DMC_DMC_BASE + 0x4E0)
#define DMC_DMC_DDRC_FUNC_STAT4_REG (DMC_DMC_BASE + 0x4E4)
#define DMC_DMC_DDRC_FUNC_STAT5_REG (DMC_DMC_BASE + 0x4E8)
#define DMC_DMC_DDRC_FUNC_STAT6_REG (DMC_DMC_BASE + 0x4EC)
#define DMC_DMC_DDRC_FUNC_STAT7_REG (DMC_DMC_BASE + 0x4F0)
#define DMC_DMC_DDRC_FUNC_STAT8_REG (DMC_DMC_BASE + 0x4F4)
#define DMC_DMC_DDRC_FUNC_STAT9_REG (DMC_DMC_BASE + 0x4F8)
#define DMC_DMC_DDRC_FUNC_STAT10_REG (DMC_DMC_BASE + 0x4FC)
#define DMC_DMC_DDRC_FUNC_STAT11_REG (DMC_DMC_BASE + 0x500)
#define DMC_DMC_DDRC_DMC_STAT12_REG (DMC_DMC_BASE + 0x504)
#define DMC_DMC_DDRC_TEST_RAM_TMOD_REG (DMC_DMC_BASE + 0x508)
#define DMC_DMC_DDRC_TEST_RTL_CFG0_REG (DMC_DMC_BASE + 0x510)
#define DMC_DMC_DDRC_TEST_RTL_CFG1_REG (DMC_DMC_BASE + 0x514)
#define DMC_DMC_DDRC_TEST_RTL_CFG2_REG (DMC_DMC_BASE + 0x518)
#define DMC_DMC_DDRC_OSC_COUNT_REG (DMC_DMC_BASE + 0x520)
#define DMC_DMC_DDRC_EDXN_DQMAP_REG (DMC_DMC_BASE + 0x580)
#define DMC_DMC_DDRC_ODXN_DQMAP_REG (DMC_DMC_BASE + 0x584)
#define DMC_DMC_DDRC_CFG_SFC_EXTCMD_CTRL_REG (DMC_DMC_BASE + 0x600)
#define DMC_DMC_DDRC_CFG_SFC_LOOP_CTRL_REG (DMC_DMC_BASE + 0x604)
#define DMC_DMC_DDRC_CFG_SFC_BER_RD_RPT_REG (DMC_DMC_BASE + 0x608)
#define DMC_DMC_DDRC_CFG_SFC_HEAD_TAIL_CUT_REG (DMC_DMC_BASE + 0x60C)
#define DMC_DMC_DDRC_CFG_SFC_PAT_PRD_REG (DMC_DMC_BASE + 0x610)
#define DMC_DMC_DDRC_CFG_SFC_WL_CTRL_REG (DMC_DMC_BASE + 0x614)
#define DMC_DMC_DDRC_CFG_SFC_ADDR2_REG (DMC_DMC_BASE + 0x618)
#define DMC_DMC_DDRC_CFG_SFC_ADDR3_REG (DMC_DMC_BASE + 0x61C)
#define DMC_DMC_DDRC_CFG_SFC_PAT_SEL_REG (DMC_DMC_BASE + 0x620)
#define DMC_DMC_DDRC_CFG_SFC_PAT_SEL_PTR_REG (DMC_DMC_BASE + 0x624)
#define DMC_DMC_DDRC_CFG_SFC_CMP_MASK_REG (DMC_DMC_BASE + 0x628)
#define DMC_DMC_DDRC_CFG_SFC_CMP_MASK_PTR_REG (DMC_DMC_BASE + 0x62C)
#define DMC_DMC_DDRC_CFG_SFC_TIM2_REG (DMC_DMC_BASE + 0x630)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED_REG (DMC_DMC_BASE + 0x634)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED1_REG (DMC_DMC_BASE + 0x638)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED2_REG (DMC_DMC_BASE + 0x63C)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED3_REG (DMC_DMC_BASE + 0x640)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED4_REG (DMC_DMC_BASE + 0x644)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED5_REG (DMC_DMC_BASE + 0x648)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED6_REG (DMC_DMC_BASE + 0x64C)
#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED7_REG (DMC_DMC_BASE + 0x650)
#define DMC_DMC_DDRC_HIS_SFC_DQS_POS_ERR_0_REG (DMC_DMC_BASE + 0x654)
#define DMC_DMC_DDRC_HIS_SFC_DQS_POS_ERR_1_REG (DMC_DMC_BASE + 0x658)
#define DMC_DMC_DDRC_HIS_SFC_DQS_POS_ERR_2_REG (DMC_DMC_BASE + 0x65C)
#define DMC_DMC_DDRC_HIS_SFC_DQS_NEG_ERR_0_REG (DMC_DMC_BASE + 0x660)
#define DMC_DMC_DDRC_HIS_SFC_DQS_NEG_ERR_1_REG (DMC_DMC_BASE + 0x664)
#define DMC_DMC_DDRC_HIS_SFC_DQS_NEG_ERR_2_REG (DMC_DMC_BASE + 0x668)
#define DMC_DMC_DDRC_HIS_SFC_PER_NIB_ERR_REG (DMC_DMC_BASE + 0x66C)
#define DMC_DMC_DDRC_HIS_SFC_PER_BYTE_ERR_REG (DMC_DMC_BASE + 0x670)
#define DMC_DMC_DDRC_HIS_SFC_ANY_ERR_REG (DMC_DMC_BASE + 0x674)
#define DMC_DMC_DDRC_HIS_SFC_QUE_CUR_PTR_REG (DMC_DMC_BASE + 0x678)
#define DMC_DMC_DDRC_HIS_SFC_ERR_NUM_REG (DMC_DMC_BASE + 0x67C)
#define DMC_DMC_DDRC_CFG_AC_ISI_PAT_REG (DMC_DMC_BASE + 0x680)
#define DMC_DMC_DDRC_CFG_AC_ISI_PTR_REG (DMC_DMC_BASE + 0x684)
#define DMC_DMC_DDRC_HIS_BG_CHG_REG (DMC_DMC_BASE + 0x688)
#define DMC_DMC_DDRC_CURR_EXEC_STATE_REG (DMC_DMC_BASE + 0x68C)
#define DMC_DMC_DDRC_PHYUPD_REQ_CNT_REG (DMC_DMC_BASE + 0x690)
#define DMC_DMC_DDRC_PHYUPD_EXIT_WAIT_REG (DMC_DMC_BASE + 0x694)
#define DMC_DMC_DDRC_CFG_TIMING9_REG (DMC_DMC_BASE + 0x698)
#define DMC_DMC_DDRC_CFG_NXT_TIMING9_REG (DMC_DMC_BASE + 0x69C)
#define DMC_DMC_DDRC_CFG_CE_CNT_TH_REG (DMC_DMC_BASE + 0x6A0)
#define DMC_DMC_DDRC_CFG_FUNNEL_CTRL_REG (DMC_DMC_BASE + 0x6A4)
#define DMC_DMC_DDRC_CFG_FUNNEL_BASE_REG (DMC_DMC_BASE + 0x6A8)
#define DMC_DMC_DDRC_CFG_FUNNEL_TH_REG (DMC_DMC_BASE + 0x6AC)
#define DMC_DMC_DDRC_HIS_SRAM_CE_CNT_REG (DMC_DMC_BASE + 0x6B0)
#define DMC_DMC_DDRC_HIS_DP_CE_CNT_REG (DMC_DMC_BASE + 0x6B4)
#define DMC_DMC_DDRC_CFG_AC_PIPE_REG (DMC_DMC_BASE + 0x6B8)
#define DMC_DMC_DDRC_HIS_AREF_PSTPND_CNT_REG (DMC_DMC_BASE + 0x6BC)
#define DMC_DMC_DDRC_PERF_EVENT_EN_REG (DMC_DMC_BASE + 0x6C0)
#define DMC_DMC_DDRC_PERF_INTR_REG (DMC_DMC_BASE + 0x6C4)
#define DMC_DMC_DDRC_PERF_INTM_REG (DMC_DMC_BASE + 0x6C8)
#define DMC_DMC_DDRC_PERF_INTS_REG (DMC_DMC_BASE + 0x6CC)
#define DMC_DMC_DDRC_PERF_INTC_REG (DMC_DMC_BASE + 0x6D0)
#define DMC_DMC_DDRC_CFG_RES0_REG (DMC_DMC_BASE + 0x700)
#define DMC_DMC_DDRC_CFG_RES1_REG (DMC_DMC_BASE + 0x704)
#define DMC_DMC_DDRC_CFG_RES2_REG (DMC_DMC_BASE + 0x708)
#define DMC_DMC_DDRC_CFG_RES3_REG (DMC_DMC_BASE + 0x70C)
#define DMC_DMC_DDRC_CFG_RES4_REG (DMC_DMC_BASE + 0x710)
#define DMC_DMC_DDRC_CFG_RES5_REG (DMC_DMC_BASE + 0x714)
#define DMC_DMC_DDRC_CFG_RES6_REG (DMC_DMC_BASE + 0x718)
#define DMC_DMC_DDRC_CFG_RES7_REG (DMC_DMC_BASE + 0x71C)
#define DMC_DMC_DDRC_CFG_MAGIC_WORD_REG (DMC_DMC_BASE + 0x7F0)
#define DMC_DMC_DDRC_CFG_VERSION_REG (DMC_DMC_BASE + 0xC10)
#endif
drivers/soc/hisilicon/sysctl/hllc_pcs_c_union_define.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __HLLC_PCS_C_UNION_DEFINE_H__
#define __HLLC_PCS_C_UNION_DEFINE_H__
/* Define the union pcs_u_tx_training_sts */
typedef union {
/* Define the struct bits */
struct {
unsigned int tx_curr_st : 7 ; /* [6..0] */
unsigned int ts1_ack_send_over : 1 ; /* [7] */
unsigned int ts1_ack_received : 1 ; /* [8] */
unsigned int ts1_received : 1 ; /* [9] */
unsigned int ts0_ack_send_over : 1 ; /* [10] */
unsigned int ts0_ack_received : 1 ; /* [11] */
unsigned int ts0_received : 1 ; /* [12] */
unsigned int tx_training_succeed : 1 ; /* [13] */
unsigned int tx_training_done : 1 ; /* [14] */
unsigned int tx_training_over : 1 ; /* [15] */
unsigned int snd_training_done : 1 ; /* [16] */
unsigned int tx_asyn_fifo_full : 1 ; /* [17] */
unsigned int tx_asyn_fifo_afull : 1 ; /* [18] */
unsigned int tx_asyn_push_word_cnt : 5 ; /* [23..19] */
unsigned int reserved_0 : 8 ; /* [31..24] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} pcs_u_tx_training_sts;
#endif /* __HLLC_PCS_C_UNION_DEFINE_H__ */
drivers/soc/hisilicon/sysctl/hllc_pcs_reg_offset.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __HLLC_PCS_REG_OFFSET_H__
#define __HLLC_PCS_REG_OFFSET_H__
/* HLLC_PCS Base address of Module's Register */
#define HLLC_HLLC_PCS_BASE (0x0)
/******************************************************************************/
/* xxx HLLC_PCS Registers' Definitions */
/******************************************************************************/
#define HLLC_HLLC_PCS_PCS_GLOBAL_CFG_REG (HLLC_HLLC_PCS_BASE + 0x0)
#define HLLC_HLLC_PCS_PCS_MISC_CFG_REG (HLLC_HLLC_PCS_BASE + 0x4)
#define HLLC_HLLC_PCS_PCS_POLARITY_CFG_REG (HLLC_HLLC_PCS_BASE + 0x8)
#define HLLC_HLLC_PCS_PCS_TRAINING_CFG_REG (HLLC_HLLC_PCS_BASE + 0xC)
#define HLLC_HLLC_PCS_PLL_PHASE_ADJUST_PARAM_CFG_REG (HLLC_HLLC_PCS_BASE + 0x10)
#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_MODE_CTRL_REG (HLLC_HLLC_PCS_BASE + 0x14)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_EN_CFG_REG (HLLC_HLLC_PCS_BASE + 0x18)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_RD_PTR_MODE_CFG_REG (HLLC_HLLC_PCS_BASE + 0x1C)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_RD_PTR_CFG_REG (HLLC_HLLC_PCS_BASE + 0x20)
#define HLLC_HLLC_PCS_PCS_PARALLEL_LOOPBACK_CFG_REG (HLLC_HLLC_PCS_BASE + 0x24)
#define HLLC_HLLC_PCS_PCS_TRAINING_TIMEOUT_CFG_REG (HLLC_HLLC_PCS_BASE + 0x28)
#define HLLC_HLLC_PCS_RAS_INT_MASK_REG (HLLC_HLLC_PCS_BASE + 0x3C)
#define HLLC_HLLC_PCS_RAS_INT_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x40)
#define HLLC_HLLC_PCS_HILINK_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x44)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x48)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x4C)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x50)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x54)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x58)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x5C)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x60)
#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x64)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x68)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x6C)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x70)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x74)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x78)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x7C)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x80)
#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x84)
#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x90)
#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_PD_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x94)
#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_CNT_REG (HLLC_HLLC_PCS_BASE + 0x98)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_0_REG (HLLC_HLLC_PCS_BASE + 0xA0)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_1_REG (HLLC_HLLC_PCS_BASE + 0xA4)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_2_REG (HLLC_HLLC_PCS_BASE + 0xA8)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_3_REG (HLLC_HLLC_PCS_BASE + 0xAC)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_4_REG (HLLC_HLLC_PCS_BASE + 0xB0)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_5_REG (HLLC_HLLC_PCS_BASE + 0xB4)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_6_REG (HLLC_HLLC_PCS_BASE + 0xB8)
#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_7_REG (HLLC_HLLC_PCS_BASE + 0xBC)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_0_REG (HLLC_HLLC_PCS_BASE + 0xD0)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_1_REG (HLLC_HLLC_PCS_BASE + 0xD4)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_2_REG (HLLC_HLLC_PCS_BASE + 0xD8)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_3_REG (HLLC_HLLC_PCS_BASE + 0xDC)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_4_REG (HLLC_HLLC_PCS_BASE + 0xE0)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_5_REG (HLLC_HLLC_PCS_BASE + 0xE4)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_6_REG (HLLC_HLLC_PCS_BASE + 0xE8)
#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_7_REG (HLLC_HLLC_PCS_BASE + 0xEC)
#define HLLC_HLLC_PCS_PCS_RX_HEAD_ILLEGAL_STATUS_REG (HLLC_HLLC_PCS_BASE + 0xF0)
#define HLLC_HLLC_PCS_PCS_BIST_START_REG (HLLC_HLLC_PCS_BASE + 0x100)
#define HLLC_HLLC_PCS_PCS_TEST_END_REG (HLLC_HLLC_PCS_BASE + 0x104)
#define HLLC_HLLC_PCS_PCS_BIST_CTRL_CFG_REG (HLLC_HLLC_PCS_BASE + 0x108)
#define HLLC_HLLC_PCS_PCS_BIST_MODE_CFG_REG (HLLC_HLLC_PCS_BASE + 0x10C)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x110)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x114)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x118)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x11C)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x120)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x124)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x128)
#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x12C)
#define HLLC_HLLC_PCS_PCS_BIST_FLIT_STS_REG (HLLC_HLLC_PCS_BASE + 0x130)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x134)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x138)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x13C)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x140)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x144)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x148)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x14C)
#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x150)
#endif
drivers/soc/hisilicon/sysctl/hllc_ras_c_union_define.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __HLLC_RAS_C_UNION_DEFINE_H__
#define __HLLC_RAS_C_UNION_DEFINE_H__
/* Define the union hllc_ras_u_err_misc1l */
typedef union {
/* Define the struct bits */
struct {
unsigned int hydra_tx_ch0_2bit_ecc_err : 1 ; /* [0] */
unsigned int hydra_tx_ch1_2bit_ecc_err : 1 ; /* [1] */
unsigned int hydra_tx_ch2_2bit_ecc_err : 1 ; /* [2] */
unsigned int phy_tx_retry_2bit_ecc_err : 1 ; /* [3] */
unsigned int hydra_rx_ch0_2bit_ecc_err : 1 ; /* [4] */
unsigned int hydra_rx_ch1_2bit_ecc_err : 1 ; /* [5] */
unsigned int hydra_rx_ch2_2bit_ecc_err : 1 ; /* [6] */
unsigned int reserved_0 : 1 ; /* [7] */
unsigned int phy_rx_retry_ptr_err : 1 ; /* [8] */
unsigned int phy_tx_retry_buf_ptr_err : 1 ; /* [9] */
unsigned int phy_tx_retry_ptr_err : 1 ; /* [10] */
unsigned int reserved_1 : 5 ; /* [15..11] */
unsigned int hydra_tx_ch0_ovf : 1 ; /* [16] */
unsigned int hydra_tx_ch1_ovf : 1 ; /* [17] */
unsigned int hydra_tx_ch2_ovf : 1 ; /* [18] */
unsigned int phy_tx_retry_buf_ovf : 1 ; /* [19] */
unsigned int hydra_rx_ch0_ovf : 1 ; /* [20] */
unsigned int hydra_rx_ch1_ovf : 1 ; /* [21] */
unsigned int hydra_rx_ch2_ovf : 1 ; /* [22] */
unsigned int reserved_2 : 1 ; /* [23] */
unsigned int hydra_pcs_err0 : 1 ; /* [24] */
unsigned int hydra_pcs_err1 : 1 ; /* [25] */
unsigned int hydra_pcs_err2 : 1 ; /* [26] */
unsigned int hydra_pcs_err3 : 1 ; /* [27] */
unsigned int hydra_pcs_err4 : 1 ; /* [28] */
unsigned int hydra_pcs_err5 : 1 ; /* [29] */
unsigned int hydra_pcs_err6 : 1 ; /* [30] */
unsigned int hydra_pcs_err7 : 1 ; /* [31] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} hllc_ras_u_err_misc1l;
/* Define the union hllc_ras_u_err_misc1h */
typedef union {
/* Define the struct bits */
struct {
unsigned int hydra_tx_ch0_1bit_ecc_err : 1 ; /* [0] */
unsigned int hydra_tx_ch1_1bit_ecc_err : 1 ; /* [1] */
unsigned int hydra_tx_ch2_1bit_ecc_err : 1 ; /* [2] */
unsigned int phy_tx_retry_1bit_ecc_err : 1 ; /* [3] */
unsigned int hydra_rx_ch0_1bit_ecc_err : 1 ; /* [4] */
unsigned int hydra_rx_ch1_1bit_ecc_err : 1 ; /* [5] */
unsigned int hydra_rx_ch2_1bit_ecc_err : 1 ; /* [6] */
unsigned int reserved_0 : 1 ; /* [7] */
unsigned int phy_rx_flit_crc_err : 1 ; /* [8] */
unsigned int reserved_1 : 23 ; /* [31..9] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} hllc_ras_u_err_misc1h;
#endif /* __C_UNION_DEFINE_HLLC_RAS_H__ */
drivers/soc/hisilicon/sysctl/hllc_ras_reg_offset.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __HLLC_RAS_REG_OFFSET_H__
#define __HLLC_RAS_REG_OFFSET_H__
/* HLLC_RAS Base address of Module's Register */
#define HLLC_HLLC_RAS_BASE (0x0)
/******************************************************************************/
/* xxx HLLC_RAS Registers' Definitions */
/******************************************************************************/
#define HLLC_HLLC_RAS_HLLC_ERR_FRL_REG (HLLC_HLLC_RAS_BASE + 0x2000)
#define HLLC_HLLC_RAS_HLLC_ERR_FRH_REG (HLLC_HLLC_RAS_BASE + 0x2004)
#define HLLC_HLLC_RAS_HLLC_ERR_CTRLL_REG (HLLC_HLLC_RAS_BASE + 0x2008)
#define HLLC_HLLC_RAS_HLLC_ERR_CTRLH_REG (HLLC_HLLC_RAS_BASE + 0x200C)
#define HLLC_HLLC_RAS_HLLC_ERR_STATUSL_REG (HLLC_HLLC_RAS_BASE + 0x2010)
#define HLLC_HLLC_RAS_HLLC_ERR_STATUSH_REG (HLLC_HLLC_RAS_BASE + 0x2014)
#define HLLC_HLLC_RAS_HLLC_ERR_ADDRL_REG (HLLC_HLLC_RAS_BASE + 0x2018)
#define HLLC_HLLC_RAS_HLLC_ERR_ADDRH_REG (HLLC_HLLC_RAS_BASE + 0x201C)
#define HLLC_HLLC_RAS_HLLC_ERR_MISC0L_REG (HLLC_HLLC_RAS_BASE + 0x2020)
#define HLLC_HLLC_RAS_HLLC_ERR_MISC0H_REG (HLLC_HLLC_RAS_BASE + 0x2024)
#define HLLC_HLLC_RAS_HLLC_ERR_MISC1L_REG (HLLC_HLLC_RAS_BASE + 0x2028)
#define HLLC_HLLC_RAS_HLLC_ERR_MISC1H_REG (HLLC_HLLC_RAS_BASE + 0x202C)
#endif
drivers/soc/hisilicon/sysctl/hllc_regs_c_union_define.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __HLLC_REGS_C_UNION_DEFINE_H__
#define __HLLC_REGS_C_UNION_DEFINE_H__
/* Define the union hllc_regs_u_inject_ecc_type */
typedef union {
/* Define the struct bits */
struct {
unsigned int inject_ecc_err_type : 2 ; /* [1..0] */
unsigned int reserved_0 : 30 ; /* [31..2] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} hllc_regs_u_inject_ecc_type;
/* Define the union hllc_regs_u_inject_ecc_en */
typedef union {
/* Define the struct bits */
struct {
unsigned int hydra_rx_inject_ecc_err_en : 3 ; /* [2..0] */
unsigned int reserved_0 : 1 ; /* [3] */
unsigned int phy_tx_retry_inject_ecc_err_en : 1 ; /* [4] */
unsigned int reserved_1 : 3 ; /* [7..5] */
unsigned int hydra_tx_inject_ecc_err_en : 3 ; /* [10..8] */
unsigned int reserved_2 : 1 ; /* [11] */
unsigned int reserved_3 : 20 ; /* [31..12] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} hllc_regs_u_inject_ecc_en;
#endif /* __HLLC_REGS_C_UNION_DEFINE_H__ */
drivers/soc/hisilicon/sysctl/hllc_regs_reg_offset.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __HLLC_REGS_REG_OFFSET_H__
#define __HLLC_REGS_REG_OFFSET_H__
/* HLLC_REGS Base address of Module's Register */
#define HLLC_HLLC_REGS_BASE (0x0)
/******************************************************************************/
/* xxx HLLC_REGS Registers' Definitions */
/******************************************************************************/
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_AFULL_TH_CFG_REG (HLLC_HLLC_REGS_BASE + 0x0)
#define HLLC_HLLC_REGS_HLLC_TOKEN_CFG_REG (HLLC_HLLC_REGS_BASE + 0x100)
#define HLLC_HLLC_REGS_HLLC_RETRAINING_CFG0_REG (HLLC_HLLC_REGS_BASE + 0x300)
#define HLLC_HLLC_REGS_HLLC_RETRAINING_CFG1_REG (HLLC_HLLC_REGS_BASE + 0x304)
#define HLLC_HLLC_REGS_HLLC_RETRAINING_CFG2_REG (HLLC_HLLC_REGS_BASE + 0x308)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_CRD_RET_CFG_REG (HLLC_HLLC_REGS_BASE + 0x400)
#define HLLC_HLLC_REGS_HLLC_SYS_MAGIC_WORD_REG (HLLC_HLLC_REGS_BASE + 0x7F0)
#define HLLC_HLLC_REGS_HLLC_INT0_SRC_REG (HLLC_HLLC_REGS_BASE + 0x800)
#define HLLC_HLLC_REGS_HLLC_INT0_MSK_REG (HLLC_HLLC_REGS_BASE + 0x804)
#define HLLC_HLLC_REGS_HLLC_INT0_ST_REG (HLLC_HLLC_REGS_BASE + 0x808)
#define HLLC_HLLC_REGS_HLLC_INT0_CLR_REG (HLLC_HLLC_REGS_BASE + 0x80C)
#define HLLC_HLLC_REGS_HLLC_INT1_SRC_REG (HLLC_HLLC_REGS_BASE + 0x810)
#define HLLC_HLLC_REGS_HLLC_INT1_MSK_REG (HLLC_HLLC_REGS_BASE + 0x814)
#define HLLC_HLLC_REGS_HLLC_INT1_ST_REG (HLLC_HLLC_REGS_BASE + 0x818)
#define HLLC_HLLC_REGS_HLLC_INT1_CLR_REG (HLLC_HLLC_REGS_BASE + 0x81C)
#define HLLC_HLLC_REGS_HLLC_ECO0_REG (HLLC_HLLC_REGS_BASE + 0xC00)
#define HLLC_HLLC_REGS_HLLC_ECO1_REG (HLLC_HLLC_REGS_BASE + 0xC04)
#define HLLC_HLLC_REGS_HLLC_ECO2_REG (HLLC_HLLC_REGS_BASE + 0xC08)
#define HLLC_HLLC_REGS_HLLC_ECO3_REG (HLLC_HLLC_REGS_BASE + 0xC0C)
#define HLLC_HLLC_REGS_HLLC_SYS_VERSION_REG (HLLC_HLLC_REGS_BASE + 0xC10)
#define HLLC_HLLC_REGS_HLLC_CNT_EN_REG (HLLC_HLLC_REGS_BASE + 0x1040)
#define HLLC_HLLC_REGS_HLLC_CNT_CLR_REG (HLLC_HLLC_REGS_BASE + 0x1044)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1100)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_BP_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1140)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_BP_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1148)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_BP_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1150)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_BP_MAX_DURATION_REG (HLLC_HLLC_REGS_BASE + 0x1160)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_BP_MAX_DURATION_REG (HLLC_HLLC_REGS_BASE + 0x1168)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_BP_MAX_DURATION_REG (HLLC_HLLC_REGS_BASE + 0x1170)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_BUF_ST_REG (HLLC_HLLC_REGS_BASE + 0x1180)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x11C0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x11C8)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x11D0)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_CRD_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1200)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1220)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RMT_ACK_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1240)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_ST_REG (HLLC_HLLC_REGS_BASE + 0x1280)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_BUF_ST_REG (HLLC_HLLC_REGS_BASE + 0x1284)
#define HLLC_HLLC_REGS_HLLC_LOC_PHY_TX_RETRY_WR_PTR_REG (HLLC_HLLC_REGS_BASE + 0x1290)
#define HLLC_HLLC_REGS_HLLC_RMT_PHY_RX_RETRY_REQ_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12A0)
#define HLLC_HLLC_REGS_HLLC_RMT_PHY_RX_RETRY_ACK_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12A8)
#define HLLC_HLLC_REGS_PHY_TX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12C0)
#define HLLC_HLLC_REGS_PHY_TX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12C8)
#define HLLC_HLLC_REGS_PHY_TX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12D0)
#define HLLC_HLLC_REGS_PHY_TX_IDLE_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12D8)
#define HLLC_HLLC_REGS_HLLC_RETRAINING_REQ_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1300)
#define HLLC_HLLC_REGS_HLLC_RETRAINING_ACK_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1308)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_CRD_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1400)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1420)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_LOC_ACK_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1440)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_RETRY_ST_REG (HLLC_HLLC_REGS_BASE + 0x1480)
#define HLLC_HLLC_REGS_HLLC_LOC_PHY_RX_RETRY_RD_PTR_REG (HLLC_HLLC_REGS_BASE + 0x1490)
#define HLLC_HLLC_REGS_HLLC_LOC_PHY_RX_RETRY_REQ_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14A0)
#define HLLC_HLLC_REGS_HLLC_LOC_PHY_RX_RETRY_ACK_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14A8)
#define HLLC_HLLC_REGS_PHY_RX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14C0)
#define HLLC_HLLC_REGS_PHY_RX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14C8)
#define HLLC_HLLC_REGS_PHY_RX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14D0)
#define HLLC_HLLC_REGS_PHY_RX_IDLE_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14D8)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1500)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_BUF_ST_REG (HLLC_HLLC_REGS_BASE + 0x1580)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x15C0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x15C8)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x15D0)
#define HLLC_HLLC_REGS_HLLC_INJECT_ECC_TYPE_REG (HLLC_HLLC_REGS_BASE + 0x1600)
#define HLLC_HLLC_REGS_HLLC_INJECT_ECC_EN_REG (HLLC_HLLC_REGS_BASE + 0x1604)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_2BIT_ECC_ERR_ADDR_REG (HLLC_HLLC_REGS_BASE + 0x1680)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1688)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1690)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1698)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_2BIT_ECC_ERR_ADDR_REG (HLLC_HLLC_REGS_BASE + 0x16A0)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16A8)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_2BIT_ECC_ERR_ADDR_REG (HLLC_HLLC_REGS_BASE + 0x16C0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16C8)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16D0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16D8)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_EN_REG (HLLC_HLLC_REGS_BASE + 0x1700)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_TIMES_REG (HLLC_HLLC_REGS_BASE + 0x1704)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_DONE_REG (HLLC_HLLC_REGS_BASE + 0x1780)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x17A0)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x17C0)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_PERFORMANCE_TEST_EN_REG (HLLC_HLLC_REGS_BASE + 0x1800)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_PERFORMANCE_TEST_PERIOD_REG (HLLC_HLLC_REGS_BASE + 0x1808)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_PERFORMANCE_TEST_DONE_REG (HLLC_HLLC_REGS_BASE + 0x1880)
#define HLLC_HLLC_REGS_PHY_RX_CH0_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18A0)
#define HLLC_HLLC_REGS_PHY_RX_CH1_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18A8)
#define HLLC_HLLC_REGS_PHY_RX_CH2_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18B0)
#define HLLC_HLLC_REGS_PHY_RX_IDLE_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18B8)
#define HLLC_HLLC_REGS_PHY_RX_NULL_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18C0)
#define HLLC_HLLC_REGS_HLLC_DEBUG_ECC_CFG_REG (HLLC_HLLC_REGS_BASE + 0x1900)
#define HLLC_HLLC_REGS_HLLC_DEBUG_CRC_CFG_REG (HLLC_HLLC_REGS_BASE + 0x1904)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1980)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1984)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1988)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1990)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x19A0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x19A4)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x19A8)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19C0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19C4)
#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19C8)
#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19D0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19E0)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19E4)
#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19E8)
#define HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19F0)
#endif
drivers/soc/hisilicon/sysctl/pa_c_union_define.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __PA_C_UNION_DEFINE_H__
#define __PA_C_UNION_DEFINE_H__
/* Define the union pa_u_global_cfg */
typedef union {
/* Define the struct bits */
struct {
unsigned int intlv_mode_cfg : 3 ; /* [2..0] */
unsigned int nimbus_extend_en_cfg : 1 ; /* [3] */
unsigned int rsv1 : 4 ; /* [7..4] */
unsigned int wb_norely_en_cfg : 1 ; /* [8] */
unsigned int rsv2 : 7 ; /* [15..9] */
unsigned int hydra_port_en_cfg : 3 ; /* [18..16] */
unsigned int rsv3 : 1 ; /* [19] */
unsigned int ewa_dis_cfg : 1 ; /* [20] */
unsigned int rsv4 : 3 ; /* [23..21] */
unsigned int dvm_retry_en_cfg : 1 ; /* [24] */
unsigned int rsv5 : 3 ; /* [27..25] */
unsigned int compdata_err_poison_en : 1 ; /* [28] */
unsigned int reg_goto_pcie_en_cfg : 1 ; /* [29] */
unsigned int nc_lpid_seq_en_cfg : 1 ; /* [30] */
unsigned int nc_non_order_en_cfg : 1 ; /* [31] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} pa_u_global_cfg;
#endif /* __PA_C_UNION_DEFINE_H__ */
drivers/soc/hisilicon/sysctl/pa_reg_offset.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __PA_REG_OFFSET_H__
#define __PA_REG_OFFSET_H__
/* PA Base address of Module's Register */
#define PA_PA_BASE (0x0)
/******************************************************************************/
/* xxx PA Registers' Definitions */
/******************************************************************************/
#define PA_PA_ID_MAPPING_CFG_REG (PA_PA_BASE + 0x0)
#define PA_PA_GLOBAL_CFG_REG (PA_PA_BASE + 0x4)
#define PA_PA_LINK_DOWN_CFG_REG (PA_PA_BASE + 0x8)
#define PA_PA_HYDRA_PORT0_MISC_CFG0_REG (PA_PA_BASE + 0xC)
#define PA_PA_HYDRA_PORT1_MISC_CFG0_REG (PA_PA_BASE + 0x10)
#define PA_PA_HYDRA_PORT2_MISC_CFG0_REG (PA_PA_BASE + 0x14)
#define PA_PA_HYDRA_PORT0_MISC_CFG1_REG (PA_PA_BASE + 0x18)
#define PA_PA_HYDRA_PORT1_MISC_CFG1_REG (PA_PA_BASE + 0x1C)
#define PA_PA_HYDRA_PORT2_MISC_CFG1_REG (PA_PA_BASE + 0x20)
#define PA_PA_TX_HALT_CFG_REG (PA_PA_BASE + 0x24)
#define PA_PA_RX_REQHALT_CFG_REG (PA_PA_BASE + 0x28)
#define PA_PA_RX_SNPHALT_CFG_REG (PA_PA_BASE + 0x2C)
#define PA_PA_RX_RSPHALT_CFG_REG (PA_PA_BASE + 0x30)
#define PA_PA_RX_DATHALT_CFG_REG (PA_PA_BASE + 0x34)
#define PA_PA_MEM_ECC_CORRECT_CFG_REG (PA_PA_BASE + 0x38)
#define PA_PA_DAW_BYP_TGTID_CFG_REG (PA_PA_BASE + 0x3C)
#define PA_PA_DDR_UTL_UPDATE_PERIOD_CFG_REG (PA_PA_BASE + 0x40)
#define PA_PA_STREAM_WRITE_SRCID0_CFG_REG (PA_PA_BASE + 0x44)
#define PA_PA_STREAM_WRITE_SRCID1_CFG_REG (PA_PA_BASE + 0x48)
#define PA_PA_COPYBACK_BP_TH_CFG_REG (PA_PA_BASE + 0x4C)
#define PA_PA_EXTEND_DEFAULT_SLV_TGTID_CFG_REG (PA_PA_BASE + 0x50)
#define PA_PA_IO_PERF_OPT_SRCID_CFG_REG (PA_PA_BASE + 0x54)
#define PA_PA_IO_PER_OPT_CTRL_CFG_REG (PA_PA_BASE + 0x58)
#define PA_PA_PREFETCH_TGT_CFG_REG (PA_PA_BASE + 0x5C)
#define PA_PA_ECO_RSV_REG1_REG (PA_PA_BASE + 0x60)
#define PA_PA_EMU_VERSION_REG_REG (PA_PA_BASE + 0x64)
#define PA_PA_FPGA_VERSION_REG_REG (PA_PA_BASE + 0x68)
#define PA_PA_INTMASK_REG (PA_PA_BASE + 0x70)
#define PA_PA_RAWINT_REG (PA_PA_BASE + 0x74)
#define PA_PA_INTSTS_REG (PA_PA_BASE + 0x78)
#define PA_PA_INTCLR_REG (PA_PA_BASE + 0x7C)
#define PA_PA_H0_TX_REQ_CURR_CNT_REG (PA_PA_BASE + 0x400)
#define PA_PA_H0_TX_CA_REQ_CURR_CNT_REG (PA_PA_BASE + 0x404)
#define PA_PA_H0_TX_NC_REQ_CURR_CNT_REG (PA_PA_BASE + 0x408)
#define PA_PA_H0_TX_P2P_CURR_CNT_REG (PA_PA_BASE + 0x40C)
#define PA_PA_H0_TX_FWD_CURR_CNT_REG (PA_PA_BASE + 0x410)
#define PA_PA_H1_TX_REQ_CURR_CNT_REG (PA_PA_BASE + 0x420)
#define PA_PA_H1_TX_CA_REQ_CURR_CNT_REG (PA_PA_BASE + 0x424)
#define PA_PA_H1_TX_NC_REQ_CURR_CNT_REG (PA_PA_BASE + 0x428)
#define PA_PA_H1_TX_P2P_CURR_CNT_REG (PA_PA_BASE + 0x42C)
#define PA_PA_H1_TX_FWD_CURR_CNT_REG (PA_PA_BASE + 0x430)
#define PA_PA_H2_TX_REQ_CURR_CNT_REG (PA_PA_BASE + 0x440)
#define PA_PA_H2_TX_CA_REQ_CURR_CNT_REG (PA_PA_BASE + 0x444)
#define PA_PA_H2_TX_NC_REQ_CURR_CNT_REG (PA_PA_BASE + 0x448)
#define PA_PA_H2_TX_P2P_CURR_CNT_REG (PA_PA_BASE + 0x44C)
#define PA_PA_H2_TX_FWD_CURR_CNT_REG (PA_PA_BASE + 0x450)
#define PA_PA_TX_REQ_CNT_REG (PA_PA_BASE + 0x460)
#define PA_PA_TX_SNP_CNT_REG (PA_PA_BASE + 0x464)
#define PA_PA_TX_RSP_CNT_REG (PA_PA_BASE + 0x468)
#define PA_PA_TX_DAT_CNT_REG (PA_PA_BASE + 0x46C)
#define PA_PA_TX_CA_RETRYACK_CNT_REG (PA_PA_BASE + 0x470)
#define PA_PA_TX_NC_RETRYACK_CNT_REG (PA_PA_BASE + 0x474)
#define PA_PA_TX_P2P_RETRYACK_CNT_REG (PA_PA_BASE + 0x478)
#define PA_PA_TX_CA_PGNT_CNT_REG (PA_PA_BASE + 0x47C)
#define PA_PA_TX_NC_PGNT_CNT_REG (PA_PA_BASE + 0x480)
#define PA_PA_TX_P2P_PGNT_CNT_REG (PA_PA_BASE + 0x484)
#define PA_PA_TX_PCRDRETURN_CNT_REG (PA_PA_BASE + 0x488)
#define PA_PA_TX_MEM_ERR_CNT_REG (PA_PA_BASE + 0x48C)
#define PA_PA_TX_MEM_ERR_HIS_ST_REG (PA_PA_BASE + 0x490)
#define PA_PA_TX_HYDRA_BP_HIS_ST_REG (PA_PA_BASE + 0x494)
#define PA_PA_TX_BUFF_HALT_HIS_ST_REG (PA_PA_BASE + 0x498)
#define PA_PA_TX_BUFF_FIFO_ST_REG (PA_PA_BASE + 0x49C)
#define PA_PA_H0_TX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x4A0)
#define PA_PA_H1_TX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x4A4)
#define PA_PA_H2_TX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x4A8)
#define PA_PA_H0_TX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x4AC)
#define PA_PA_H1_TX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x4B0)
#define PA_PA_H2_TX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x4B4)
#define PA_PA_H0_TX_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x4B8)
#define PA_PA_H1_TX_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x4BC)
#define PA_PA_H2_TX_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x4C0)
#define PA_PA_H0_TX_RSP_ERR_INFO_REG (PA_PA_BASE + 0x4C4)
#define PA_PA_H1_TX_RSP_ERR_INFO_REG (PA_PA_BASE + 0x4C8)
#define PA_PA_H2_TX_RSP_ERR_INFO_REG (PA_PA_BASE + 0x4CC)
#define PA_PA_TX_BUFF_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4D0)
#define PA_PA_H0_TX_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4D4)
#define PA_PA_H1_TX_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4D8)
#define PA_PA_H2_TX_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4DC)
#define PA_PA_H0_TX_REQ_ERR_INFO_REG (PA_PA_BASE + 0x4E0)
#define PA_PA_H1_TX_REQ_ERR_INFO_REG (PA_PA_BASE + 0x4E4)
#define PA_PA_H2_TX_REQ_ERR_INFO_REG (PA_PA_BASE + 0x4E8)
#define PA_PA_H0_RX_REQ_WDATA_BUFF_CNT_REG (PA_PA_BASE + 0x500)
#define PA_PA_H0_RX_REQ_CA_CURR_CNT_REG (PA_PA_BASE + 0x504)
#define PA_PA_H0_RX_REQ_SW_CURR_CNT_REG (PA_PA_BASE + 0x508)
#define PA_PA_H0_RX_REQ_CA_ADDR_CNT_REG (PA_PA_BASE + 0x50C)
#define PA_PA_H0_RX_REQ_NC_CURR_CNT_REG (PA_PA_BASE + 0x510)
#define PA_PA_H0_RX_REQ_NCFWD_CURR_CNT_REG (PA_PA_BASE + 0x514)
#define PA_PA_H0_RX_SNP_CURR_CNT_REG (PA_PA_BASE + 0x518)
#define PA_PA_H0_RX_COMPDBID_CURR_CNT_REG (PA_PA_BASE + 0x51C)
#define PA_PA_H0_RX_SNPRSP_BUFF_CNT_REG (PA_PA_BASE + 0x520)
#define PA_PA_H0_RX_REQ_RETRY_ACK_CNT_REG (PA_PA_BASE + 0x524)
#define PA_PA_H0_RX_REQ_PGNT_CNT_REG (PA_PA_BASE + 0x528)
#define PA_PA_H0_RX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x52C)
#define PA_PA_H0_RX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x530)
#define PA_PA_H0_RX_REQ_DAW_ERR_INFO_REG (PA_PA_BASE + 0x534)
#define PA_PA_H0_RX_REQ_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x538)
#define PA_PA_H0_RX_SNPRSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x53C)
#define PA_PA_H0_RX_SNP_RSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x540)
#define PA_PA_H0_RX_STREAM_WR_BUFF_CNT_REG (PA_PA_BASE + 0x544)
#define PA_PA_H0_RX_BUFF_OF_HIS_ST_REG (PA_PA_BASE + 0x548)
#define PA_PA_H1_RX_REQ_WDATA_BUFF_CNT_REG (PA_PA_BASE + 0x600)
#define PA_PA_H1_RX_REQ_CA_CURR_CNT_REG (PA_PA_BASE + 0x604)
#define PA_PA_H1_RX_REQ_SW_CURR_CNT_REG (PA_PA_BASE + 0x608)
#define PA_PA_H1_RX_REQ_CA_ADDR_CNT_REG (PA_PA_BASE + 0x60C)
#define PA_PA_H1_RX_REQ_NC_CURR_CNT_REG (PA_PA_BASE + 0x610)
#define PA_PA_H1_RX_REQ_NCFWD_CURR_CNT_REG (PA_PA_BASE + 0x614)
#define PA_PA_H1_RX_SNP_CURR_CNT_REG (PA_PA_BASE + 0x618)
#define PA_PA_H1_RX_COMPDBID_CURR_CNT_REG (PA_PA_BASE + 0x61C)
#define PA_PA_H1_RX_SNPRSP_BUFF_CNT_REG (PA_PA_BASE + 0x620)
#define PA_PA_H1_RX_REQ_RETRY_ACK_CNT_REG (PA_PA_BASE + 0x624)
#define PA_PA_H1_RX_REQ_PGNT_CNT_REG (PA_PA_BASE + 0x628)
#define PA_PA_H1_RX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x62C)
#define PA_PA_H1_RX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x630)
#define PA_PA_H1_RX_REQ_DAW_ERR_INFO_REG (PA_PA_BASE + 0x634)
#define PA_PA_H1_RX_REQ_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x638)
#define PA_PA_H1_RX_SNPRSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x63C)
#define PA_PA_H1_RX_SNP_RSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x640)
#define PA_PA_H1_RX_STREAM_WR_BUFF_CNT_REG (PA_PA_BASE + 0x644)
#define PA_PA_H1_RX_BUFF_OF_HIS_ST_REG (PA_PA_BASE + 0x648)
#define PA_PA_H2_RX_REQ_WDATA_BUFF_CNT_REG (PA_PA_BASE + 0x700)
#define PA_PA_H2_RX_REQ_CA_CURR_CNT_REG (PA_PA_BASE + 0x704)
#define PA_PA_H2_RX_REQ_SW_CURR_CNT_REG (PA_PA_BASE + 0x708)
#define PA_PA_H2_RX_REQ_CA_ADDR_CNT_REG (PA_PA_BASE + 0x70C)
#define PA_PA_H2_RX_REQ_NC_CURR_CNT_REG (PA_PA_BASE + 0x710)
#define PA_PA_H2_RX_REQ_NCFWD_CURR_CNT_REG (PA_PA_BASE + 0x714)
#define PA_PA_H2_RX_SNP_CURR_CNT_REG (PA_PA_BASE + 0x718)
#define PA_PA_H2_RX_COMPDBID_CURR_CNT_REG (PA_PA_BASE + 0x71C)
#define PA_PA_H2_RX_SNPRSP_BUFF_CNT_REG (PA_PA_BASE + 0x720)
#define PA_PA_H2_RX_REQ_RETRY_ACK_CNT_REG (PA_PA_BASE + 0x724)
#define PA_PA_H2_RX_REQ_PGNT_CNT_REG (PA_PA_BASE + 0x728)
#define PA_PA_H2_RX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x72C)
#define PA_PA_H2_RX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x730)
#define PA_PA_H2_RX_REQ_DAW_ERR_INFO_REG (PA_PA_BASE + 0x734)
#define PA_PA_H2_RX_REQ_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x738)
#define PA_PA_H2_RX_SNPRSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x73C)
#define PA_PA_H2_RX_SNP_RSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x740)
#define PA_PA_H2_RX_STREAM_WR_BUFF_CNT_REG (PA_PA_BASE + 0x744)
#define PA_PA_H2_RX_BUFF_OF_HIS_ST_REG (PA_PA_BASE + 0x748)
#define PA_PA_RX_REQ_CNT_REG (PA_PA_BASE + 0x800)
#define PA_PA_RX_SNP_CNT_REG (PA_PA_BASE + 0x804)
#define PA_PA_RX_RSP_CNT_REG (PA_PA_BASE + 0x808)
#define PA_PA_RX_DAT_CNT_REG (PA_PA_BASE + 0x80C)
#define PA_PA_RX_RETINFO_SCH_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x810)
#define PA_PA_RX_RETINFO_SCH_FIFO_FULL_ST_REG (PA_PA_BASE + 0x814)
#define PA_PA_RX_REQ_SCH_FIFO_ST_REG (PA_PA_BASE + 0x818)
#define PA_PA_RX_SNP_SCH_FIFO_ST_REG (PA_PA_BASE + 0x81C)
#define PA_PA_RX_RSP_SCH_FIFO_ST_REG (PA_PA_BASE + 0x820)
#define PA_PA_RX_DAT_SCH_FIFO_ST_REG (PA_PA_BASE + 0x824)
#define PA_PA_RX_MEM_ECC_1BIT_ERR_HIS_ST_REG (PA_PA_BASE + 0x828)
#define PA_PA_RX_MEM_ECC_2BIT_ERR_HIS_ST_REG (PA_PA_BASE + 0x82C)
#define PA_PA_RX_MEM_ERR_CNT_REG (PA_PA_BASE + 0x830)
#define PA_PA_RX_SKY_LINK_BP_ST_REG (PA_PA_BASE + 0x834)
#define PA_PA_RX_SKY_LINK_BP_HIS_ST_REG (PA_PA_BASE + 0x838)
#define PA_PA_RX_BUFF_HALT_HIS_ST_REG (PA_PA_BASE + 0x83C)
#define PA_PA_RX_SCH_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x840)
#define PA_PA_RX_RETINFO_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x844)
#define PA_PA_MEM_ERR_INJECT_CFG_REG (PA_PA_BASE + 0x850)
#define PA_PA_DID_HHA_ID_CFG0_REG (PA_PA_BASE + 0x860)
#define PA_PA_DID_HHA_ID_CFG1_REG (PA_PA_BASE + 0x864)
#define PA_PA_DID_HHA_ID_CFG2_REG (PA_PA_BASE + 0x868)
#define PA_PA_DID_HHA_ID_CFG3_REG (PA_PA_BASE + 0x86C)
#define PA_PA_DID_L3T_ID_CFG_REG (PA_PA_BASE + 0x870)
#define PA_PA_DID_DEFAULT_SLV_ID_CFG_REG (PA_PA_BASE + 0x874)
#define PA_PA_CER_IDR_REG (PA_PA_BASE + 0xC10)
#define PA_PA_CER_IDR_MODIFY_EN_REG (PA_PA_BASE + 0xC14)
#define PA_PA_ERR_FRL_REG (PA_PA_BASE + 0x2000)
#define PA_PA_ERR_FRH_REG (PA_PA_BASE + 0x2004)
#define PA_PA_ERR_CTRLL_REG (PA_PA_BASE + 0x2008)
#define PA_PA_ERR_CTRLH_REG (PA_PA_BASE + 0x200C)
#define PA_PA_ERR_STATUSL_REG (PA_PA_BASE + 0x2010)
#define PA_PA_ERR_STATUSH_REG (PA_PA_BASE + 0x2014)
#define PA_PA_ERR_ADDRL_REG (PA_PA_BASE + 0x2018)
#define PA_PA_ERR_ADDRH_REG (PA_PA_BASE + 0x201C)
#define PA_PA_ERR_MISC0L_REG (PA_PA_BASE + 0x2020)
#define PA_PA_ERR_MISC0H_REG (PA_PA_BASE + 0x2024)
#define PA_PA_ERR_MISC1L_REG (PA_PA_BASE + 0x2028)
#define PA_PA_ERR_MISC1H_REG (PA_PA_BASE + 0x202C)
#endif
drivers/soc/hisilicon/sysctl/rasc_c_union_define.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __RASC_C_UNION_DEFINE_H__
#define __RASC_C_UNION_DEFINE_H__
/* Define the union ddrc_rasc_u_cfg_clr */
typedef union {
/* Define the struct bits */
struct {
unsigned int all_errcnt_clr : 1 ; /* [0] */
unsigned int ha_errcnt_clr : 1 ; /* [1] */
unsigned int vls_errcnt_clr : 1 ; /* [2] */
unsigned int rvls_errcnt_clr : 1 ; /* [3] */
unsigned int pa_errcnt_clr : 1 ; /* [4] */
unsigned int sp_errcnt_clr : 1 ; /* [5] */
unsigned int sp_rberrcnt_clr : 1 ; /* [6] */
unsigned int reserved_0 : 1 ; /* [7] */
unsigned int corr_errcnt_clr : 1 ; /* [8] */
unsigned int uncorr_errcnt_clr : 1 ; /* [9] */
unsigned int reserved_1 : 22 ; /* [31..10] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} ddrc_rasc_u_cfg_clr;
/* Define the union ddrc_rasc_u_cfg_info_rnk */
typedef union {
/* Define the struct bits */
struct {
unsigned int idx_rnk : 4 ; /* [3..0] */
unsigned int rnk_sel_mode : 1 ; /* [4] */
unsigned int reserved_0 : 27 ; /* [31..5] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} ddrc_rasc_u_cfg_info_rnk;
/* Define the union ddrc_rasc_u_his_ha_rankcnt_inf */
typedef union {
/* Define the struct bits */
struct {
unsigned int ha_rnk_funnel_corr_cnt : 16 ; /* [15..0] */
unsigned int ha_rnk_corr_cnt : 16 ; /* [31..16] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} ddrc_rasc_u_his_ha_rankcnt_inf;
#endif /* __RASC_C_UNION_DEFINE_H__ */
drivers/soc/hisilicon/sysctl/rasc_reg_offset.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __RASC_REG_OFFSET_H__
#define __RASC_REG_OFFSET_H__
/* RASC Base address of Module's Register */
#define DDRC_RASC_BASE (0x1800)
/******************************************************************************/
/* xxx RASC Registers' Definitions */
/******************************************************************************/
#define DDRC_RASC_RASC_CTRL_MODE_REG (DDRC_RASC_BASE + 0x0)
#define DDRC_RASC_RASC_CTRL_ADDDC_REG (DDRC_RASC_BASE + 0x4)
#define DDRC_RASC_RASC_CTRL_PASCRUB_REG (DDRC_RASC_BASE + 0x8)
#define DDRC_RASC_RASC_CTRL_SPARING_REG (DDRC_RASC_BASE + 0xC)
#define DDRC_RASC_RASC_CTRL_FLUSH_REG (DDRC_RASC_BASE + 0x10)
#define DDRC_RASC_RASC_CTRL_ERRINJ_REG (DDRC_RASC_BASE + 0x14)
#define DDRC_RASC_RASC_CTRL_FUNNEL_REG (DDRC_RASC_BASE + 0x18)
#define DDRC_RASC_RASC_CFG_MODE_REG (DDRC_RASC_BASE + 0x20)
#define DDRC_RASC_RASC_CFG_RANKMAP_REG (DDRC_RASC_BASE + 0x30)
#define DDRC_RASC_RASC_CFG_CLR_REG (DDRC_RASC_BASE + 0x54)
#define DDRC_RASC_RASC_CFG_INFO_RNK_REG (DDRC_RASC_BASE + 0x58)
#define DDRC_RASC_RASC_CFG_INFO_DEVIDX_REG (DDRC_RASC_BASE + 0x5C)
#define DDRC_RASC_RASC_CFG_INFO_BNKIDX_REG (DDRC_RASC_BASE + 0x60)
#define DDRC_RASC_RASC_CFG_PASTART_REG (DDRC_RASC_BASE + 0x70)
#define DDRC_RASC_RASC_CFG_PAEND_REG (DDRC_RASC_BASE + 0x80)
#define DDRC_RASC_RASC_CFG_PS_REG (DDRC_RASC_BASE + 0x90)
#define DDRC_RASC_RASC_CFG_ADDDC_REGION0_REG (DDRC_RASC_BASE + 0xA0)
#define DDRC_RASC_RASC_CFG_ADDDC_REGION1_REG (DDRC_RASC_BASE + 0xA4)
#define DDRC_RASC_RASC_CFG_ADDDC_RVLS_REG (DDRC_RASC_BASE + 0xA8)
#define DDRC_RASC_RASC_CFG_VLS_INTERVAL_REG (DDRC_RASC_BASE + 0xAC)
#define DDRC_RASC_RASC_CFG_VLS_X8_REG (DDRC_RASC_BASE + 0xB0)
#define DDRC_RASC_RASC_CFG_SP_REG (DDRC_RASC_BASE + 0xC0)
#define DDRC_RASC_RASC_CFG_SPR_INTERVAL_REG (DDRC_RASC_BASE + 0xC4)
#define DDRC_RASC_RASC_CFG_SPR_OUTSTANDING_REG (DDRC_RASC_BASE + 0xC8)
#define DDRC_RASC_RASC_CFG_CE_LVL_REG (DDRC_RASC_BASE + 0xD4)
#define DDRC_RASC_RASC_CFG_FUNNEL_BASE_REG (DDRC_RASC_BASE + 0xE0)
#define DDRC_RASC_RASC_CFG_FUNNEL_TH_REG (DDRC_RASC_BASE + 0xE4)
#define DDRC_RASC_RASC_CFG_ERRINJMODE_REG (DDRC_RASC_BASE + 0xF0)
#define DDRC_RASC_RASC_CFG_ERRINJ_ADDR_L_REG (DDRC_RASC_BASE + 0xF4)
#define DDRC_RASC_RASC_CFG_ERRINJ_ADDR_H_REG (DDRC_RASC_BASE + 0xF8)
#define DDRC_RASC_RASC_CFG_ERRINJ_ADDRMSK_L_REG (DDRC_RASC_BASE + 0xFC)
#define DDRC_RASC_RASC_CFG_ERRINJ_ADDRMSK_H_REG (DDRC_RASC_BASE + 0x100)
#define DDRC_RASC_RASC_CFG_ERR_BUF_SEL_REG (DDRC_RASC_BASE + 0x104)
#define DDRC_RASC_RASC_CFG_ERRINJ_DMSK_REG (DDRC_RASC_BASE + 0x110)
#define DDRC_RASC_RASC_CFG_POISON_REG (DDRC_RASC_BASE + 0x140)
#define DDRC_RASC_RASC_CFG_RAM_ERRINJ_REG (DDRC_RASC_BASE + 0x150)
#define DDRC_RASC_RASC_CFG_RAM_TMOD_REG (DDRC_RASC_BASE + 0x154)
#define DDRC_RASC_RASC_CFG_CORR_TH_REG (DDRC_RASC_BASE + 0x160)
#define DDRC_RASC_RASC_CFG_RH_REG (DDRC_RASC_BASE + 0x164)
#define DDRC_RASC_RASC_CFG_RH_ADJA_OP_REG (DDRC_RASC_BASE + 0x168)
#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV1_REG (DDRC_RASC_BASE + 0x16C)
#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV2_REG (DDRC_RASC_BASE + 0x170)
#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV3_REG (DDRC_RASC_BASE + 0x174)
#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV4_REG (DDRC_RASC_BASE + 0x178)
#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV1_REG (DDRC_RASC_BASE + 0x17C)
#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV2_REG (DDRC_RASC_BASE + 0x180)
#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV3_REG (DDRC_RASC_BASE + 0x184)
#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV4_REG (DDRC_RASC_BASE + 0x188)
#define DDRC_RASC_RASC_CFG_RH_SCRAM_UP_REG (DDRC_RASC_BASE + 0x18C)
#define DDRC_RASC_RASC_CFG_RH_SCRAM_DOWN_REG (DDRC_RASC_BASE + 0x190)
#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV1_REG (DDRC_RASC_BASE + 0x194)
#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV2_REG (DDRC_RASC_BASE + 0x198)
#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV3_REG (DDRC_RASC_BASE + 0x19C)
#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV4_REG (DDRC_RASC_BASE + 0x1A0)
#define DDRC_RASC_RASC_CFG_RH_TCAL_REG (DDRC_RASC_BASE + 0x1A4)
#define DDRC_RASC_RASC_CFG_RES0_REG (DDRC_RASC_BASE + 0x1F0)
#define DDRC_RASC_RASC_CFG_RES1_REG (DDRC_RASC_BASE + 0x1F4)
#define DDRC_RASC_RASC_CFG_RES2_REG (DDRC_RASC_BASE + 0x1F8)
#define DDRC_RASC_RASC_CFG_RES3_REG (DDRC_RASC_BASE + 0x1FC)
#define DDRC_RASC_RASC_INTMSK_REG (DDRC_RASC_BASE + 0x200)
#define DDRC_RASC_RASC_RINT_REG (DDRC_RASC_BASE + 0x204)
#define DDRC_RASC_RASC_INTSTS_REG (DDRC_RASC_BASE + 0x208)
#define DDRC_RASC_RASC_CURR_STATUS_REG (DDRC_RASC_BASE + 0x220)
#define DDRC_RASC_RASC_CURR_ERRSTATUS_REG (DDRC_RASC_BASE + 0x224)
#define DDRC_RASC_RASC_CURR_SPRNK_STA_REG (DDRC_RASC_BASE + 0x228)
#define DDRC_RASC_RASC_CURR_SPDEV_STA_REG (DDRC_RASC_BASE + 0x22C)
#define DDRC_RASC_RASC_CURR_SPDEV_DEV1_REG (DDRC_RASC_BASE + 0x230)
#define DDRC_RASC_RASC_CURR_CMD_CNT_REG (DDRC_RASC_BASE + 0x234)
#define DDRC_RASC_RASC_CURR_ADDDC_STA_REG (DDRC_RASC_BASE + 0x238)
#define DDRC_RASC_RASC_HIS_UNCORR_CNT_REG (DDRC_RASC_BASE + 0x240)
#define DDRC_RASC_RASC_HIS_CORR_CNT_REG (DDRC_RASC_BASE + 0x244)
#define DDRC_RASC_RASC_HIS_HAERR_CNT_REG (DDRC_RASC_BASE + 0x250)
#define DDRC_RASC_RASC_HIS_PAERR_CNT_REG (DDRC_RASC_BASE + 0x258)
#define DDRC_RASC_RASC_HIS_SPERR_CNT_REG (DDRC_RASC_BASE + 0x25C)
#define DDRC_RASC_RASC_HIS_SPRBERR_CNT_REG (DDRC_RASC_BASE + 0x260)
#define DDRC_RASC_RASC_HIS_VLSERR_CNT_REG (DDRC_RASC_BASE + 0x264)
#define DDRC_RASC_RASC_HIS_RVLSERR_CNT_REG (DDRC_RASC_BASE + 0x268)
#define DDRC_RASC_RASC_HIS_RANKCNT_INF_REG (DDRC_RASC_BASE + 0x280)
#define DDRC_RASC_RASC_HIS_HA_RANKCNT_INF_REG (DDRC_RASC_BASE + 0x284)
#define DDRC_RASC_RASC_HIS_RANK_ERR_REG (DDRC_RASC_BASE + 0x28C)
#define DDRC_RASC_RASC_HIS_OFFSET_ERR_REG (DDRC_RASC_BASE + 0x290)
#define DDRC_RASC_RASC_HIS_SEG_ERR_REG (DDRC_RASC_BASE + 0x2A0)
#define DDRC_RASC_RASC_HIS_WORST_DEV_REG (DDRC_RASC_BASE + 0x2D4)
#define DDRC_RASC_RASC_HIS_WORST_BNK_REG (DDRC_RASC_BASE + 0x2D8)
#define DDRC_RASC_RASC_HIS_RCDTYP_REG (DDRC_RASC_BASE + 0x300)
#define DDRC_RASC_RASC_HIS_UNCORR_ADDR_L_REG (DDRC_RASC_BASE + 0x310)
#define DDRC_RASC_RASC_HIS_UNCORR_ADDR_H_REG (DDRC_RASC_BASE + 0x314)
#define DDRC_RASC_RASC_HIS_UNCORR_RDATA_REG (DDRC_RASC_BASE + 0x320)
#define DDRC_RASC_RASC_HIS_UNCORR_RDATA_CWH_REG (DDRC_RASC_BASE + 0x350)
#define DDRC_RASC_RASC_HIS_CORR_ADDR_L_REG (DDRC_RASC_BASE + 0x380)
#define DDRC_RASC_RASC_HIS_CORR_ADDR_H_REG (DDRC_RASC_BASE + 0x384)
#define DDRC_RASC_RASC_HIS_CORR_RDATA_REG (DDRC_RASC_BASE + 0x390)
#define DDRC_RASC_RASC_HIS_CORR_RDATA_CWH_REG (DDRC_RASC_BASE + 0x3C0)
#define DDRC_RASC_RASC_HIS_CORR_EXPDATA_REG (DDRC_RASC_BASE + 0x400)
#define DDRC_RASC_RASC_HIS_CORR_EXPDATA_CWH_REG (DDRC_RASC_BASE + 0x430)
#define DDRC_RASC_RASC_HIS_ERRINJ_CNT_REG (DDRC_RASC_BASE + 0x460)
#endif
drivers/soc/hisilicon/sysctl/sysctl_dfx.c 已删除 100644 → 0
浏览文件 @ 463a23d0
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/cper.h>
#include <linux/mutex.h>
#include <linux/uaccess.h>
#include <linux/stat.h>
#include <acpi/ghes.h>
#include <uapi/linux/uuid.h>
#include "sysctl_local_ras.h"
enum {
/* ARM */
RAS_MODULE_CPU_CORE,
/* OEM1 */
RAS_MODULE_PLL,
RAS_MODULE_SLLC,
RAS_MODULE_SIOE,
RAS_MODULE_POE,
RAS_MODULE_DISPATCH,
RAS_MODULE_TDH,
RAS_MODULE_GIC,
RAS_MODULE_RDE,
RAS_MODULE_SAS,
RAS_MODULE_SATA,
RAS_MODULE_USB,
/* OEM2 */
RAS_MODULE_SMMU,
RAS_MODULE_HHA,
RAS_MODULE_PA,
RAS_MODULE_HLLC,
RAS_MODULE_DDRC,
/* PCIE LOCAL */
RAS_MODULE_PCIE_AP,
RAS_MODULE_PCIE_DL,
RAS_MODULE_PCIE_MAC,
RAS_MODULE_PCIE_SDI_LOCAL,
RAS_MODULE_PCIE_TL,
/* HPRE */
RAS_MODULE_ZIP,
RAS_MODULE_SEC,
RAS_MODULE_HPRE,
/* NET */
RAS_MODULE_NET_GE,
RAS_MODULE_NET_25GE,
RAS_MODULE_NET_25GE_RDMA,
RAS_MODULE_NET_50GE_RDMA,
RAS_MODULE_NET_100G_RDMA,
RAS_MODULE_NET_SDI,
RAS_MODULE_NET_100G_VF,
RAS_MODULE_NET_100G_RDMA_VF,
RAS_MODULE_MAX,
};
enum {
SYSCTL_IOCTL_GET_RAS = 0,
};
#define SYSCTL_PROC "hisi_sysctl"
#define SYSCTRL_DFX_DBG_LEVEL 0
#if SYSCTRL_DFX_DBG_LEVEL
#define SYSCTRL_DFX_DBG(fmt...) printk(fmt)
#else
#define SYSCTRL_DFX_DBG(fmt...)
#endif
struct ras_node {
u32 cnt;
};
struct ras_handle {
guid_t gid;
void (*proc)(const void *err);
};
static DEFINE_MUTEX(g_ras_info_lock);
static struct ras_node g_ras_info[RAS_MODULE_MAX] = {0};
static void do_ras_oem_type1(const void *error);
static void do_ras_oem_type2(const void *error);
static void do_ras_arm(const void *error);
static void do_ras_pcie(const void *error);
static void do_ras_pcie_local(const void *error);
static const struct ras_handle g_ras_handle_tab[] = {
{
.gid = CPER_SEC_HISI_OEM_1,
.proc = do_ras_oem_type1,
},
{
.gid = CPER_SEC_HISI_OEM_2,
.proc = do_ras_oem_type2,
},
{
.gid = CPER_SEC_HISI_PCIE_LOCAL,
.proc = do_ras_pcie_local,
},
{
.gid = CPER_SEC_PCIE,
.proc = do_ras_pcie,
},
{
.gid = CPER_SEC_PROC_ARM,
.proc = do_ras_arm,
}
};
static void do_ras_oem_type1(const void *error)
{
u32 ras_moudle_id;
const struct hisi_oem_type1_err_sec *err = error;
if (!err->validation_bits.module_id_vald) {
pr_err("%s : module id is invalid\n", __func__);
return;
}
SYSCTRL_DFX_DBG("%s module_id = %u\n", __func__, err->module_id);
switch (err->module_id) {
case (OEM1_MODULE_PLL):
ras_moudle_id = RAS_MODULE_PLL;
break;
case (OEM1_MODULE_SLLC):
ras_moudle_id = RAS_MODULE_SLLC;
break;
case (OEM1_MODULE_SIOE):
ras_moudle_id = RAS_MODULE_SIOE;
break;
case (OEM1_MODULE_POE):
ras_moudle_id = RAS_MODULE_POE;
break;
case (OEM1_MODULE_DISP):
ras_moudle_id = RAS_MODULE_DISPATCH;
break;
case (OEM1_MODULE_TDH):
ras_moudle_id = RAS_MODULE_TDH;
break;
case (OEM1_MODULE_GIC):
ras_moudle_id = RAS_MODULE_GIC;
break;
case (OEM1_MODULE_RDE):
ras_moudle_id = RAS_MODULE_RDE;
break;
case (OEM1_MODULE_SAS):
ras_moudle_id = RAS_MODULE_SAS;
break;
case (OEM1_MODULE_SATA):
ras_moudle_id = RAS_MODULE_SATA;
break;
case (OEM1_MODULE_USB):
ras_moudle_id = RAS_MODULE_USB;
break;
default:
return;
}
mutex_lock(&g_ras_info_lock);
g_ras_info[ras_moudle_id].cnt++;
mutex_unlock(&g_ras_info_lock);
}
static void do_ras_oem_type2(const void *error)
{
u32 ras_moudle_id;
const struct hisi_oem_type2_err_sec *err = error;
if (!(err->val_bits & HISI_OEM_VALID_MODULE_ID)) {
pr_err("%s: module id is invalid\n", __func__);
return;
}
SYSCTRL_DFX_DBG("%s module_id= %u\n", __func__, err->module_id);
switch (err->module_id) {
case (OEM2_MODULE_SMMU):
ras_moudle_id = RAS_MODULE_SMMU;
break;
case (OEM2_MODULE_HHA):
ras_moudle_id = RAS_MODULE_HHA;
break;
case (OEM2_MODULE_PA):
ras_moudle_id = RAS_MODULE_PA;
break;
case (OEM2_MODULE_HLLC):
ras_moudle_id = RAS_MODULE_HLLC;
break;
case (OEM2_MODULE_DDRC):
ras_moudle_id = RAS_MODULE_DDRC;
break;
default:
return;
}
mutex_lock(&g_ras_info_lock);
g_ras_info[ras_moudle_id].cnt++;
mutex_unlock(&g_ras_info_lock);
}
static bool is_net_subsys_devid(u16 device_id, u32 *module_id)
{
switch (device_id) {
case (HISI_PCIE_DEV_ID_GE):
*module_id = RAS_MODULE_NET_GE;
break;
case (HISI_PCIE_DEV_ID_25GE):
*module_id = RAS_MODULE_NET_25GE;
break;
case (HISI_PCIE_DEV_ID_25GE_RDMA):
*module_id = RAS_MODULE_NET_25GE_RDMA;
break;
case (HISI_PCIE_DEV_ID_50GE_RDMA):
*module_id = RAS_MODULE_NET_50GE_RDMA;
break;
case (HISI_PCIE_DEV_ID_100G_RDMA):
*module_id = RAS_MODULE_NET_100G_RDMA;
break;
case (HISI_PCIE_DEV_ID_SDI):
*module_id = RAS_MODULE_NET_SDI;
break;
case (HISI_PCIE_DEV_ID_100G_VF):
*module_id = RAS_MODULE_NET_100G_VF;
break;
case (HISI_PCIE_DEV_ID_100G_RDMA_VF):
*module_id = RAS_MODULE_NET_100G_RDMA_VF;
break;
default:
return false;
}
return true;
}
static void do_ras_pcie(const void *error)
{
u32 ras_moudle_id;
const struct cper_sec_pcie *err = error;
if (!(err->validation_bits & CPER_PCIE_VALID_DEVICE_ID)) {
pr_err("do ras pcie : device id is invalid\n");
return;
}
if (err->device_id.vendor_id != HISI_PCIE_VENDOR_ID) {
pr_err("do ras pcie : vendor id is not hisi\n");
return;
}
SYSCTRL_DFX_DBG("do ras pcie = 0x%x\n", err->device_id.device_id);
if (err->device_id.device_id == HISI_PCIE_DEV_ID_ZIP) {
ras_moudle_id = RAS_MODULE_ZIP;
} else if (err->device_id.device_id == HISI_PCIE_DEV_ID_SEC) {
ras_moudle_id = RAS_MODULE_SEC;
} else if (err->device_id.device_id == HISI_PCIE_DEV_ID_HPRE) {
ras_moudle_id = RAS_MODULE_HPRE;
} else if (is_net_subsys_devid(err->device_id.device_id, &ras_moudle_id)) {
SYSCTRL_DFX_DBG("RAS: do_net_ras\n");
} else {
pr_err("do ras pcie : device id=0x%x not support\n", err->device_id.device_id);
return;
}
mutex_lock(&g_ras_info_lock);
g_ras_info[ras_moudle_id].cnt++;
mutex_unlock(&g_ras_info_lock);
}
static void do_ras_arm(const void *error)
{
mutex_lock(&g_ras_info_lock);
g_ras_info[RAS_MODULE_CPU_CORE].cnt++;
mutex_unlock(&g_ras_info_lock);
}
static void do_ras_pcie_local(const void *error)
{
u32 ras_moudle_id;
const struct hisi_pcie_local_err_sec *err = error;
if (!(err->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID)) {
pr_err("%s: module id is invalid\n", __func__);
return;
}
SYSCTRL_DFX_DBG("%s module_id=%u\n", __func__, err->sub_module_id);
switch (err->sub_module_id) {
case (PCIE_LOCAL_MODULE_AP):
ras_moudle_id = RAS_MODULE_PCIE_AP;
break;
case (PCIE_LOCAL_MODULE_TL):
ras_moudle_id = RAS_MODULE_PCIE_TL;
break;
case (PCIE_LOCAL_MODULE_MAC):
ras_moudle_id = RAS_MODULE_PCIE_MAC;
break;
case (PCIE_LOCAL_MODULE_DL):
ras_moudle_id = RAS_MODULE_PCIE_DL;
break;
case (PCIE_LOCAL_MODULE_SDI):
ras_moudle_id = RAS_MODULE_PCIE_SDI_LOCAL;
break;
default:
return;
}
mutex_lock(&g_ras_info_lock);
g_ras_info[ras_moudle_id].cnt++;
mutex_unlock(&g_ras_info_lock);
}
void sysctl_dfx_do_ras(struct acpi_hest_generic_data *gdata)
{
u32 count;
guid_t *sec_type = NULL;
SYSCTRL_DFX_DBG("do ras\n");
if (!gdata) {
pr_err("[ERROR]: err gdata\n");
return;
}
sec_type = (guid_t *)gdata->section_type;
for (count = 0; count < ARRAY_SIZE(g_ras_handle_tab); count++) {
if (guid_equal(sec_type, &g_ras_handle_tab[count].gid)) {
g_ras_handle_tab[count].proc(acpi_hest_get_payload(gdata));
break;
}
}
}
static long sysctl_proc_ioctl(struct file *file, unsigned int req, unsigned long arg)
{
if (req == SYSCTL_IOCTL_GET_RAS) {
mutex_lock(&g_ras_info_lock);
if (copy_to_user((void *)arg, &g_ras_info[0], sizeof(g_ras_info)))
pr_err("sysctl proc : copy to user failed\n");
mutex_unlock(&g_ras_info_lock);
}
return 0;
}
static const struct file_operations g_sysctl_proc_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = sysctl_proc_ioctl,
};
int sysctl_proc_init(void)
{
if (!proc_create(SYSCTL_PROC, S_IRUGO, NULL, &g_sysctl_proc_fops)) {
pr_err("sysctl proc create failed\n");
return -ENOMEM;
}
SYSCTRL_DFX_DBG("sysctl proc init\n");
return 0;
}
void sysctl_proc_exit(void)
{
SYSCTRL_DFX_DBG("sysctl proc exit\n");
remove_proc_entry(SYSCTL_PROC, NULL);
}
drivers/soc/hisilicon/sysctl/sysctl_dfx.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _SYSCTL_DFX_H_
#define _SYSCTL_DFX_H_
int sysctl_proc_init(void);
void sysctl_proc_exit(void);
void sysctl_dfx_do_ras(struct acpi_hest_generic_data *gdata);
#endif /* _SYSCTL_DFX_H_ */
drivers/soc/hisilicon/sysctl/sysctl_drv.c 已删除 100644 → 0
浏览文件 @ 463a23d0
此差异已折叠。
drivers/soc/hisilicon/sysctl/sysctl_drv.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _SYSCTL_DRV_H_
#define _SYSCTL_DRV_H_
/* SYSCTRL ERR */
#define SYSCTL_ERR_OK 0 /* Ok */
#define SYSCTL_ERR_PARAM 1 /* Invalid parameter */
#define SYSCTL_ERR_FAILED 2 /* Operation failed */
#define SYSCTL_ERR_PORT 3 /* Invalid port */
#define SYSCTL_ERR_TIMEOUT 4 /* Operation time out */
#define SYSCTL_ERR_NOMATCH 5 /* Version not match */
#define SYSCTL_ERR_EXIST 6 /* Entry exists */
#define SYSCTL_ERR_NOMEM 7 /* Out of memory */
#define SYSCTL_ERR_INIT 8 /* Feature not initialized */
#define SYSCTL_ERR_FAULT 9 /* Invalid address */
#define SYSCTL_ERR_PERM 10 /* Operation not permitted */
#define SYSCTL_ERR_EMPTY 11 /* Table empty */
#define SYSCTL_ERR_FULL 12 /* Table full */
#define SYSCTL_ERR_NOT_FOUND 13 /* Not found */
#define SYSCTL_ERR_BUSY 14 /* Device or resource busy */
#define SYSCTL_ERR_RESOURCE 15 /* No resources for operation */
#define SYSCTL_ERR_CONFIG 16 /* Invalid configuration */
#define SYSCTL_ERR_UNAVAIL 17 /* Feature unavailable */
#define SYSCTL_ERR_CRC 18 /* CRC check failed */
#define SYSCTL_ERR_NXIO 19 /* No such device or address */
#define SYSCTL_ERR_ROLLBACK 20 /* chip rollback fail */
#define SYSCTL_ERR_LEN 32 /* Length too short or too long */
#define SYSCTL_ERR_UNSUPPORT 0xFF /* Feature not supported */
#define CHIP_VER_BASE 0x20107E238
#define PEH_REG_ADDR (0xd7d00008)
#define HLLC0_REG_BASE (0x000200080000)
#define HLLC1_REG_BASE (0x000200090000)
#define HLLC2_REG_BASE (0x0002000a0000)
#define PCS0_REG_BASE (0x0002000c0000)
#define PA_REG_BASE (0x0002001d0000)
#define DDRC0_TB_REG_BASE (0x000094d20000)
#define DDRC0_TA_REG_BASE (0x00009cd20000)
#define HLLC_INTLV_MODE_2PX8 0x0
#define HLLC_INTLV_MODE_2PX16 0x1
#define HLLC_INTLV_MODE_2PX24 0x2
#define HLLC_INTLV_MODE_4PX8 0x3
#define HLLC_INTLV_MODE_3P1 0x5
#define HLLC_INTLV_MODE_3P2 0x6
#define CHIP_VERSION_ES (0x1)
#define HLLC_CHIP_MODULE_ES (0x400000000000)
#define HLLC_CHIP_MODULE_CS (0x200000000000)
#define HLLC_NUM_MAX (0x3)
#define HLLC_CH_NUM_MAX (0x3)
#define TOTEM_NUM_MAX (0x2)
#define TOTEM_TA_NUM (0x0)
#define TOTEM_TB_NUM (0x1)
#define DDRC_CH_NUM_MAX (0x4)
#define DDRC_RANK_NUM_MAX (0x8)
#define HLLC_LANE_NUM_MAX (0x8)
#define CHIP_ID_NUM_MAX (0x4)
#define DDRC_ECC_EN (0x5001)
#define RSV_CHAR_NUM 3
extern unsigned int g_sysctrl_debug;
#define debug_sysctrl_print(fmt...) \
do { \
if (g_sysctrl_debug) \
printk(fmt); \
} while (0)
typedef struct {
unsigned char hllc_enable;
unsigned char rvs0[RSV_CHAR_NUM];
unsigned int hllc_crc_ecc[HLLC_NUM_MAX];
} hllc_crc_ecc_info;
typedef union {
/* Define the struct bits */
struct {
unsigned int hllc_enable : 8 ; /* [7..0] 0:hllc0, 1:hllc1, 2:hllc2 */
unsigned int hllc_link_status : 8 ; /* [15..8] */
unsigned int rsv1 : 16 ; /* [31..16] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} hllc_link_sta_info;
typedef union {
/* Define the struct bits */
struct {
unsigned int hydra_tx_ch0_bit1_ecc_err : 1 ; /* [0] */
unsigned int hydra_tx_ch1_bit1_ecc_err : 1 ; /* [1] */
unsigned int hydra_tx_ch2_bit1_ecc_err : 1 ; /* [2] */
unsigned int phy_tx_retry_bit1_ecc_err : 1 ; /* [3] */
unsigned int hydra_rx_ch0_bit1_ecc_err : 1 ; /* [4] */
unsigned int hydra_rx_ch1_bit1_ecc_err : 1 ; /* [5] */
unsigned int hydra_rx_ch2_bit1_ecc_err : 1 ; /* [6] */
unsigned int hydra_tx_ch0_bit2_ecc_err : 1 ; /* [7] */
unsigned int hydra_tx_ch1_bit2_ecc_err : 1 ; /* [8] */
unsigned int hydra_tx_ch2_bit2_ecc_err : 1 ; /* [9] */
unsigned int phy_tx_retry_bit2_ecc_err : 1 ; /* [10] */
unsigned int hydra_rx_ch0_bit2_ecc_err : 1 ; /* [11] */
unsigned int hydra_rx_ch1_bit2_ecc_err : 1 ; /* [12] */
unsigned int hydra_rx_ch2_bit2_ecc_err : 1 ; /* [13] */
unsigned int rsv1 : 18 ; /* [31..14] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} hllc_mem_ecc_info;
typedef struct {
unsigned char ddrc_mem_secc_en;
unsigned char rsv0[RSV_CHAR_NUM];
unsigned int ddrc_mem_secc;
unsigned int ddrc_mem_mecc;
} ddrc_mem_ecc_info;
u64 get_chip_base(void);
#endif /* _SYSCTL_DRV_H_ */
drivers/soc/hisilicon/sysctl/sysctl_local_ras.c 已删除 100644 → 0
浏览文件 @ 463a23d0
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <acpi/ghes.h>
#include <acpi/apei.h>
#include <ras/ras_event.h>
#include <../drivers/acpi/apei/apei-internal.h>
#include "sysctl_local_ras.h"
#include "sysctl_drv.h"
#include "sysctl_dfx.h"
static LIST_HEAD(hisi_ghes_list);
static DEFINE_MUTEX(hisi_ghes_mutex);
#define HISI_GHES_ESTATUS_MAX_SIZE 65536
#define SUBCTRL_REG_BASE 0x000201070000
#define SUBCTRL_TDH_RESET_OFFSET 0xa58
#define SUBCTRL_TDH_UNRESET_OFFSET 0xa5c
#define TDH_REG_BASE 0x000201190000
#define TDH_MEM_ACCESS_OFFSET 0x140
#define TDH_IRQ_CNT_MAX 0x1000
static u32 g_sysctl_tdh_irq_cnt;
static void __iomem *sysctl_subctrl_tdh_priv[CHIP_ID_NUM_MAX];
static void __iomem *sysctl_tdh_priv[CHIP_ID_NUM_MAX];
static int sysctl_tdh_init(void)
{
u32 chip_id;
u64 addr;
u64 tdh_addr;
u64 chip_module_base;
pr_info("[INFO] %s start.\n", __func__);
chip_module_base = get_chip_base();
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
addr = (u64)chip_id * chip_module_base + SUBCTRL_REG_BASE;
sysctl_subctrl_tdh_priv[chip_id] = ioremap(addr, (u64)0x10000);
if (!sysctl_subctrl_tdh_priv[chip_id])
pr_err("chip=%u, subctrl ioremap failed\n", chip_id);
tdh_addr = (u64)chip_id * chip_module_base + TDH_REG_BASE;
sysctl_tdh_priv[chip_id] = ioremap(tdh_addr, (u64)0x10000);
if (!sysctl_tdh_priv[chip_id])
pr_err("chip=%u, tdh ioremap failed\n", chip_id);
}
return SYSCTL_ERR_OK;
}
static void sysctl_tdh_deinit(void)
{
u8 chip_id;
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
if (sysctl_subctrl_tdh_priv[chip_id])
iounmap((void *)sysctl_subctrl_tdh_priv[chip_id]);
if (sysctl_tdh_priv[chip_id])
iounmap((void *)sysctl_tdh_priv[chip_id]);
}
}
static int sysctl_tdh_reset(u8 chip_id)
{
void __iomem *addr;
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("err chip id %u %s\n", chip_id, __func__);
return SYSCTL_ERR_PARAM;
}
if (!sysctl_subctrl_tdh_priv[chip_id])
return SYSCTL_ERR_PARAM;
addr = sysctl_subctrl_tdh_priv[chip_id] + SUBCTRL_TDH_RESET_OFFSET;
writel(0x3, addr);
return SYSCTL_ERR_OK;
}
static int sysctl_tdh_unreset(u8 chip_id)
{
void __iomem *addr;
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("err chip id %u %s\n", chip_id, __func__);
return SYSCTL_ERR_PARAM;
}
if (!sysctl_subctrl_tdh_priv[chip_id])
return SYSCTL_ERR_PARAM;
addr = sysctl_subctrl_tdh_priv[chip_id] + SUBCTRL_TDH_UNRESET_OFFSET;
writel(0x3, addr);
return SYSCTL_ERR_OK;
}
static int sysctl_tdh_mem_access_open(u8 chip_id)
{
void __iomem *addr;
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("err chip id %u %s\n", chip_id, __func__);
return SYSCTL_ERR_PARAM;
}
if (!sysctl_tdh_priv[chip_id])
return SYSCTL_ERR_PARAM;
addr = sysctl_tdh_priv[chip_id] + TDH_MEM_ACCESS_OFFSET;
writel(0x0, addr);
return SYSCTL_ERR_OK;
}
static inline bool sysctl_is_hest_type_generic_v2(struct ghes *ghes)
{
return ghes->generic->header.type == ACPI_HEST_TYPE_GENERIC_ERROR_V2;
}
static int sysctl_map_gen_v2(const struct ghes *ghes)
{
return apei_map_generic_address(&ghes->generic_v2->read_ack_register);
}
static void sysctl_unmap_gen_v2(const struct ghes *ghes)
{
apei_unmap_generic_address(&ghes->generic_v2->read_ack_register);
}
static int sysctl_correlation_reg_report(const struct hisi_oem_type1_err_sec *ras_cper)
{
switch (ras_cper->module_id) {
case OEM1_MODULE_TDH:
pr_info("[INFO] SYSCTL RAS tdh correlation_reg info:\n");
break;
case OEM1_MODULE_USB:
if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB0) {
pr_info("[INFO] SYSCTL RAS usb0 correlation_reg info:\n");
} else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB1) {
pr_info("[INFO] SYSCTL RAS usb1 correlation_reg info:\n");
} else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB2) {
pr_info("[INFO] SYSCTL RAS usb2 correlation_reg info:\n");
} else {
pr_err("[ERROR] SYSCTL RAS usb sub_module_id[0x%x] is error.\n", ras_cper->sub_mod_id);
return -1;
}
break;
case OEM1_MODULE_SATA:
pr_info("[INFO] SYSCTL RAS sata correlation_reg info:\n");
break;
default:
pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error.\n", ras_cper->module_id);
return -1;
}
pr_info("[INFO] SYSCTL RAS socket_id: %x.\n", ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS nimbus_id: %x.\n", ras_cper->nimbus_id);
pr_info("[INFO] SYSCTL RAS err_misc0: %x.\n", ras_cper->err_misc0);
pr_info("[INFO] SYSCTL RAS err_misc1: %x.\n", ras_cper->err_misc1);
pr_info("[INFO] SYSCTL RAS err_misc2: %x.\n", ras_cper->err_misc2);
pr_info("[INFO] SYSCTL RAS err_misc3: %x.\n", ras_cper->err_misc3);
pr_info("[INFO] SYSCTL RAS err_misc4: %x.\n", ras_cper->err_misc4);
pr_info("[INFO] SYSCTL RAS err_addrl: %x.\n", ras_cper->err_addrl);
pr_info("[INFO] SYSCTL RAS err_addrh: %x.\n", ras_cper->err_addrh);
return 0;
}
static int sysctl_do_recovery(const struct hisi_oem_type1_err_sec *ras_cper)
{
int ret = 0;
switch (ras_cper->module_id) {
case OEM1_MODULE_TDH:
g_sysctl_tdh_irq_cnt++;
sysctl_tdh_reset(ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS tdh of chip[%d] reset.\n", ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS sysctl_tdh_irq_cnt[%d].\n", g_sysctl_tdh_irq_cnt);
udelay(20); /* Delay 20 subtleties */
if (g_sysctl_tdh_irq_cnt <= TDH_IRQ_CNT_MAX) {
sysctl_tdh_unreset(ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS tdh of chip[%d] unreset.\n", ras_cper->socket_id);
sysctl_tdh_mem_access_open(ras_cper->socket_id);
pr_info("[INFO] SYSCTL RAS tdh of chip[%d] mem access open.\n",
ras_cper->socket_id);
} else {
pr_err("[ERROR] SYSCTL RAS tdh of chip[%d] unreset %d times, won't unreset.\n",
ras_cper->socket_id, TDH_IRQ_CNT_MAX);
}
break;
case OEM1_MODULE_USB:
if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB0) {
pr_info("[INFO] SYSCTL RAS usb0 error.\n");
} else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB1) {
pr_info("[INFO] SYSCTL RAS usb1 error.\n");
} else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB2) {
pr_info("[INFO] SYSCTL RAS usb2 error.\n");
} else {
pr_err("[ERROR] SYSCTL RAS usb sub_module_id[0x%x] is error.\n", ras_cper->sub_mod_id);
return ret;
}
break;
case OEM1_MODULE_SATA:
pr_info("[INFO] SYSCTL RAS sata error.\n");
break;
default:
pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error, has not match process in sysctl.\n",
ras_cper->module_id);
return ret;
}
(void)sysctl_correlation_reg_report(ras_cper);
return ret;
}
static int sysctl_hest_hisi_parse_ghes_count(struct acpi_hest_header *hest_hdr, void *data)
{
int *count = data;
if (hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR ||
hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR_V2)
(*count)++;
return 0;
}
static struct ghes *sysctl_ghes_new(struct acpi_hest_generic *sysctl_generic)
{
struct ghes *sysctl_ghes;
size_t err_block_length;
int ret = 0;
sysctl_ghes = kzalloc(sizeof(*sysctl_ghes), GFP_KERNEL);
if (!sysctl_ghes)
return ERR_PTR((long)-ENOMEM);
sysctl_ghes->generic = sysctl_generic;
if (sysctl_is_hest_type_generic_v2(sysctl_ghes)) {
ret = sysctl_map_gen_v2(sysctl_ghes);
if (ret)
goto err_free;
}
ret = apei_map_generic_address(&sysctl_generic->error_status_address);
if (ret)
goto err_unmap_read_ack_addr;
err_block_length = sysctl_generic->error_block_length;
if (err_block_length > HISI_GHES_ESTATUS_MAX_SIZE) {
pr_err("SYSCTL RAS Error status block length is too long: %u for "
"generic hardware error source: %d.\n",
(u32)err_block_length, sysctl_generic->header.source_id);
err_block_length = HISI_GHES_ESTATUS_MAX_SIZE;
}
sysctl_ghes->estatus = NULL;
return sysctl_ghes;
err_unmap_read_ack_addr:
if (sysctl_is_hest_type_generic_v2(sysctl_ghes))
sysctl_unmap_gen_v2(sysctl_ghes);
err_free:
kfree(sysctl_ghes);
return ERR_PTR((long)ret);
}
static int sysctl_hest_hisi_parse_ghes(struct acpi_hest_header *hest_hdr, void *data)
{
struct acpi_hest_generic *sysctl_generic;
struct ghes *sysctl_ghes = NULL;
(void)data;
sysctl_generic = container_of(hest_hdr, struct acpi_hest_generic, header);
if (!sysctl_generic->enabled)
return 0;
debug_sysctrl_print("[DBG] SYSCTL RAS ghes source id: %x.\n",
hest_hdr->source_id);
debug_sysctrl_print("[DBG] SYSCTL RAS ghes error_block_length: %x.\n",
sysctl_generic->error_block_length);
debug_sysctrl_print("[DBG] SYSCTL RAS ghes notify type: %x.\n",
sysctl_generic->notify.type);
sysctl_ghes = sysctl_ghes_new(sysctl_generic);
if (!sysctl_ghes) {
pr_err("[ERROR] SYSCTL RAS sysctl_ghes is null.\n");
return -ENOMEM;
}
list_add(&sysctl_ghes->list, &hisi_ghes_list);
return 0;
}
static int sysctl_ghes_read_estatus_pre(struct ghes **sysctl_ghes, int silent)
{
struct acpi_hest_generic *g = (*sysctl_ghes)->generic;
u32 err_block_length;
phys_addr_t buf_paddr;
int ret;
ret = apei_read(&buf_paddr, &g->error_status_address);
if (ret) {
if (!silent && printk_ratelimit())
pr_err("[ERROR] SYSCTL RAS apei_read fail, source_id: %d.\n", g->header.source_id);
pr_err("[ERROR] SYSCTL RAS apei_read fail, ret: %d.\n", ret);
return -EIO;
}
if (!buf_paddr) {
pr_err("[ERROR] SYSCTL RAS buf_paddr is null.\n");
return -ENOENT;
}
err_block_length = g->error_block_length;
if (err_block_length > HISI_GHES_ESTATUS_MAX_SIZE) {
pr_info("[INFO] SYSCTL RAS error_block_length: %u, source_id: %d.\n", err_block_length, g->header.source_id);
err_block_length = HISI_GHES_ESTATUS_MAX_SIZE;
}
(*sysctl_ghes)->estatus = ioremap_wc(buf_paddr, err_block_length);
if (!((*sysctl_ghes)->estatus)) {
pr_err("estatus ioremap failed\n");
return -ENOENT;
}
if (!((*sysctl_ghes)->estatus->block_status)) {
iounmap((*sysctl_ghes)->estatus);
return -ENOENT;
}
(*sysctl_ghes)->buffer_paddr = buf_paddr;
(*sysctl_ghes)->flags |= GHES_TO_CLEAR;
return 0;
}
static int sysctl_ghes_read_estatus(struct ghes *sysctl_ghes, int silent)
{
u32 len;
int ret;
ret = sysctl_ghes_read_estatus_pre(&sysctl_ghes, silent);
if (ret)
return ret;
ret = -EIO;
len = cper_estatus_len(sysctl_ghes->estatus);
if (len < sizeof(*sysctl_ghes->estatus)) {
pr_err("[ERROR] SYSCTL RAS len[%d] less than sizeof(*ghes->estatus)[%ld].\n",
len, sizeof(*sysctl_ghes->estatus));
goto error_read_block;
}
if (len > sysctl_ghes->generic->error_block_length) {
pr_err("[ERROR] SYSCTL RAS len[%d] more than error_block_length[%d].\n",
len, sysctl_ghes->generic->error_block_length);
goto error_read_block;
}
if (cper_estatus_check_header(sysctl_ghes->estatus)) {
pr_err("[ERROR] SYSCTL RAS cper_estatus_check_header fail.\n");
goto error_read_block;
}
if (cper_estatus_check(sysctl_ghes->estatus)) {
pr_err("[ERROR] SYSCTL RAS cper_estatus_check fail.\n");
goto error_read_block;
}
ret = 0;
return ret;
error_read_block:
pr_err("[ERROR] SYSCTL RAS info of ghes error status block is error.\n");
iounmap(sysctl_ghes->estatus);
pr_err("[ERROR] SYSCTL RAS read error status block fail.\n");
return ret;
}
void sysctl_ghes_clear_estatus(struct ghes *sysctl_ghes)
{
sysctl_ghes->estatus->block_status = 0;
if (!(sysctl_ghes->flags & GHES_TO_CLEAR))
return;
sysctl_ghes->flags &= ~GHES_TO_CLEAR;
}
static void sysctl_ghes_do_proc(struct ghes *sysctl_ghes,
struct acpi_hest_generic_status *sysct_estatus)
{
struct acpi_hest_generic_data *gdata = NULL;
guid_t *sec_type = NULL;
struct hisi_oem_type1_err_sec *ras_cper = NULL;
struct cper_sec_proc_arm *arm_ras_cper = NULL;
(void)sysctl_ghes;
apei_estatus_for_each_section(sysct_estatus, gdata) {
sec_type = (guid_t *)gdata->section_type;
sysctl_dfx_do_ras(gdata);
if (guid_equal(sec_type, &CPER_SEC_HISI_OEM_1)) {
ras_cper = acpi_hest_get_payload(gdata);
(void)sysctl_do_recovery(ras_cper);
} else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) {
arm_ras_cper = acpi_hest_get_payload(gdata);
if (arm_ras_cper->err_info_num != 1) {
pr_err("[ERROR] SYSCTL RAS err_info_num[0x%x] is error.\n",
arm_ras_cper->err_info_num);
return;
}
}
cper_estatus_print("[INFO] SYSCTL RAS HISILICON Error : ",
sysctl_ghes->estatus);
}
}
static int sysctl_ghes_proc(struct ghes *sysctl_ghes)
{
int ret;
ret = sysctl_ghes_read_estatus(sysctl_ghes, 0);
if (ret)
return ret;
sysctl_ghes_do_proc(sysctl_ghes, sysctl_ghes->estatus);
iounmap(sysctl_ghes->estatus);
return ret;
}
static int sysctl_hisi_error_handler(struct work_struct *work)
{
int ret = 0;
struct ghes *sysctl_ghes = NULL;
(void)work;
list_for_each_entry(sysctl_ghes, &hisi_ghes_list, list) {
if (!sysctl_ghes_proc(sysctl_ghes))
ret = NOTIFY_OK;
}
return ret;
}
/* acpi hisi hest init */
static void sysctl_acpi_hisi_hest_init(void)
{
int ret;
unsigned int ghes_count = 0;
debug_sysctrl_print("[DBG] SYSCTL RAS %s start.\n", __func__);
if (hest_disable) {
pr_err("[ERROR] SYSCTL RAS Table parsing disabled.\n");
return;
}
ret = apei_hest_parse(sysctl_hest_hisi_parse_ghes_count, &ghes_count);
if (ret) {
pr_err("[ERROR] SYSCTL RAS hest_hisi_parse_ghes_count fail.\n");
return;
}
debug_sysctrl_print("[DBG] SYSCTL RAS Get ghes count: %d.\n", ghes_count);
ret = apei_hest_parse(sysctl_hest_hisi_parse_ghes, &ghes_count);
if (ret) {
pr_err("[ERROR] SYSCTL RAS hest_hisi_parse_ghes fail.\n");
return;
}
}
int sysctl_notify_hed(struct notifier_block *that, unsigned long event, void *data)
{
int ret;
(void)event;
(void)data;
(void)that;
ret = sysctl_hisi_error_handler(NULL);
return ret;
}
static struct notifier_block g_sysctl_ghes_hisi_notifier_hed = {
.notifier_call = sysctl_notify_hed,
.priority = INT_MAX,
};
int hip_sysctl_local_ras_init(void)
{
int ret;
sysctl_proc_init();
ret = sysctl_tdh_init();
if (ret != SYSCTL_ERR_OK) {
pr_err("[ERROR] SYSCTL RAS sysctl_tdh_init fail.\n");
return ret;
}
sysctl_acpi_hisi_hest_init();
ret = register_acpi_hed_notifier(&g_sysctl_ghes_hisi_notifier_hed);
if (ret != SYSCTL_ERR_OK) {
pr_err("[ERROR] SYSCTL RAS register_acpi_hed_notifier fail.\n");
return ret;
}
ret = sysctl_tdh_mem_access_open(0);
if (ret != SYSCTL_ERR_OK) {
pr_err("[ERROR] SYSCTL RAS sysctl_tdh_mem_access_open fail.\n");
return ret;
}
return ret;
}
static void his_ghes_list_free(void)
{
struct ghes *node = NULL;
struct ghes *tmp_node = NULL;
list_for_each_entry(node, &hisi_ghes_list, list) {
if (!node)
continue;
apei_unmap_generic_address(&node->generic->error_status_address);
if (sysctl_is_hest_type_generic_v2(node))
sysctl_unmap_gen_v2(node);
/* Release the node of the previous loop. */
if (tmp_node != NULL) {
kfree(tmp_node);
tmp_node = NULL;
}
/* Record the node of the current loop. */
tmp_node = node;
/* hisi_ghes_list isn't a member of node. */
if (node->list.next == &hisi_ghes_list) {
node = NULL;
break;
}
}
if (tmp_node != NULL) {
kfree(tmp_node);
tmp_node = NULL;
}
}
void hip_sysctl_local_ras_exit(void)
{
unregister_acpi_hed_notifier(&g_sysctl_ghes_hisi_notifier_hed);
sysctl_proc_exit();
sysctl_tdh_deinit();
his_ghes_list_free();
pr_info("[INFO] hip sysctl local ras exit.\n");
}
drivers/soc/hisilicon/sysctl/sysctl_local_ras.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _SYSCTL_LOCAL_RAS_H_
#define _SYSCTL_LOCAL_RAS_H_
enum {
OEM1_SUB_MODULE_USB0 = 0,
OEM1_SUB_MODULE_USB1,
OEM1_SUB_MODULE_USB2,
};
enum {
OEM1_MODULE_PLL = 1,
OEM1_MODULE_SLLC = 2,
OEM1_MODULE_SIOE = 4,
OEM1_MODULE_POE = 5,
OEM1_MODULE_DISP = 8,
OEM1_MODULE_TDH = 9,
OEM1_MODULE_GIC = 13,
OEM1_MODULE_RDE = 14,
OEM1_MODULE_SAS = 15,
OEM1_MODULE_SATA = 16,
OEM1_MODULE_USB = 17,
};
enum {
OEM2_MODULE_SMMU = 0,
OEM2_MODULE_HHA = 1,
OEM2_MODULE_PA = 2,
OEM2_MODULE_HLLC = 3,
OEM2_MODULE_DDRC = 4,
};
enum {
PCIE_LOCAL_MODULE_AP = 0,
PCIE_LOCAL_MODULE_TL = 1,
PCIE_LOCAL_MODULE_MAC = 2,
PCIE_LOCAL_MODULE_DL = 3,
PCIE_LOCAL_MODULE_SDI = 4,
};
#define HISI_OEM_VALID_SOC_ID BIT(0)
#define HISI_OEM_VALID_SOCKET_ID BIT(1)
#define HISI_OEM_VALID_NIMBUS_ID BIT(2)
#define HISI_OEM_VALID_MODULE_ID BIT(3)
#define HISI_OEM_VALID_SUB_MODULE_ID BIT(4)
#define HISI_OEM_VALID_ERR_SEVERITY BIT(5)
#define HISI_OEM_TYPE2_VALID_ERR_FR BIT(6)
#define HISI_OEM_TYPE2_VALID_ERR_CTRL BIT(7)
#define HISI_OEM_TYPE2_VALID_ERR_STATUS BIT(8)
#define HISI_OEM_TYPE2_VALID_ERR_ADDR BIT(9)
#define HISI_OEM_TYPE2_VALID_ERR_MISC_0 BIT(10)
#define HISI_OEM_TYPE2_VALID_ERR_MISC_1 BIT(11)
#define HISI_PCIE_LOCAL_VALID_VERSION BIT(0)
#define HISI_PCIE_LOCAL_VALID_SOC_ID BIT(1)
#define HISI_PCIE_LOCAL_VALID_SOCKET_ID BIT(2)
#define HISI_PCIE_LOCAL_VALID_NIMBUS_ID BIT(3)
#define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4)
#define HISI_PCIE_LOCAL_VALID_CORE_ID BIT(5)
#define HISI_PCIE_LOCAL_VALID_PORT_ID BIT(6)
#define HISI_PCIE_LOCAL_VALID_ERR_TYPE BIT(7)
#define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY BIT(8)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_0 BIT(9)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_1 BIT(10)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_2 BIT(11)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_3 BIT(12)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_4 BIT(13)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_5 BIT(14)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_6 BIT(15)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_7 BIT(16)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_8 BIT(17)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_9 BIT(18)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_10 BIT(19)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_11 BIT(20)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_12 BIT(21)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_13 BIT(22)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_14 BIT(23)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_15 BIT(24)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_16 BIT(25)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_17 BIT(26)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_18 BIT(27)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_19 BIT(28)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_20 BIT(29)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_21 BIT(30)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_22 BIT(31)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_23 BIT(32)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_24 BIT(33)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_25 BIT(34)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_26 BIT(35)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_27 BIT(36)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_28 BIT(37)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_29 BIT(38)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_30 BIT(39)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_31 BIT(40)
#define HISI_PCIE_LOCAL_VALID_ERR_MISC_32 BIT(41)
#define HISI_PCIE_VENDOR_ID 0x19e5
/* NET Device ID */
#define HISI_PCIE_DEV_ID_GE 0xa220
#define HISI_PCIE_DEV_ID_25GE 0xa221
#define HISI_PCIE_DEV_ID_25GE_RDMA 0xa222
#define HISI_PCIE_DEV_ID_50GE_RDMA 0xa224
#define HISI_PCIE_DEV_ID_100G_RDMA 0xa226
#define HISI_PCIE_DEV_ID_SDI 0xa22a
#define HISI_PCIE_DEV_ID_100G_VF 0xa22e
#define HISI_PCIE_DEV_ID_100G_RDMA_VF 0xa22f
/* HPRE Device ID */
#define HISI_PCIE_DEV_ID_ZIP 0xa250
#define HISI_PCIE_DEV_ID_SEC 0xa255
#define HISI_PCIE_DEV_ID_HPRE 0xa258
#define CPER_SEC_HISI_OEM_1 \
GUID_INIT(0x1F8161E1, 0x55D6, 0x41E6, 0xBD, 0x10, 0x7A,\
0xFD, 0x1D, 0xC5, 0xF7, 0xC5)
#define CPER_SEC_HISI_OEM_2 \
GUID_INIT(0x45534EA6, 0xCE23, 0x4115, 0x85, 0x35, 0xE0, 0x7A, \
0xB3, 0xAE, 0xF9, 0x1D)
#define CPER_SEC_HISI_PCIE_LOCAL \
GUID_INIT(0xb2889fc9, 0xe7d7, 0x4f9d, 0xa8, 0x67, 0xaf, 0x42, \
0xe9, 0x8b, 0xe7, 0x72)
struct oem1_validation_bits {
u32 soc_id_vald : 1;
u32 socket_id_vald : 1;
u32 nimbus_id_vald : 1;
u32 module_id_vald : 1;
u32 submod_id_vald : 1;
u32 err_sever_vald : 1;
u32 err_misc0_vald : 1;
u32 err_misc1_vald : 1;
u32 err_misc2_vald : 1;
u32 err_misc3_vald : 1;
u32 err_misc4_vald : 1;
u32 err_addr_vald : 1;
u32 reserv : 20;
};
struct hisi_oem_type1_err_sec {
struct oem1_validation_bits validation_bits;
u8 version;
u8 soc_id;
u8 socket_id;
u8 nimbus_id;
u8 module_id;
u8 sub_mod_id;
u8 err_severity;
u8 resv1;
u32 err_misc0;
u32 err_misc1;
u32 err_misc2;
u32 err_misc3;
u32 err_misc4;
u32 err_addrl;
u32 err_addrh;
};
struct hisi_oem_type2_err_sec {
u32 val_bits;
u8 version;
u8 soc_id;
u8 socket_id;
u8 nimbus_id;
u8 module_id;
u8 sub_module_id;
u8 err_severity;
u8 reserv;
u32 err_fr_0;
u32 err_fr_1;
u32 err_ctrl_0;
u32 err_ctrl_1;
u32 err_status_0;
u32 err_status_1;
u32 err_addr_0;
u32 err_addr_1;
u32 err_misc0_0;
u32 err_misc0_1;
u32 err_misc1_0;
u32 err_misc1_1;
};
struct hisi_pcie_local_err_sec {
u64 val_bits;
u8 version;
u8 soc_id;
u8 socket_id;
u8 nimbus_id;
u8 sub_module_id;
u8 core_id;
u8 port_id;
u8 err_severity;
u16 err_type;
u8 reserv[2]; /* reserv 2 bytes */
u32 err_misc_0;
u32 err_misc_1;
u32 err_misc_2;
u32 err_misc_3;
u32 err_misc_4;
u32 err_misc_5;
u32 err_misc_6;
u32 err_misc_7;
u32 err_misc_8;
u32 err_misc_9;
u32 err_misc_10;
u32 err_misc_11;
u32 err_misc_12;
u32 err_misc_13;
u32 err_misc_14;
u32 err_misc_15;
u32 err_misc_16;
u32 err_misc_17;
u32 err_misc_18;
u32 err_misc_19;
u32 err_misc_20;
u32 err_misc_21;
u32 err_misc_22;
u32 err_misc_23;
u32 err_misc_24;
u32 err_misc_25;
u32 err_misc_26;
u32 err_misc_27;
u32 err_misc_28;
u32 err_misc_29;
u32 err_misc_30;
u32 err_misc_31;
u32 err_misc_32;
};
int hip_sysctl_local_ras_init(void);
void hip_sysctl_local_ras_exit(void);
#endif
drivers/soc/hisilicon/sysctl/sysctl_pmbus.c 已删除 100644 → 0
浏览文件 @ 463a23d0
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/io.h>
#include <linux/delay.h>
#include "sysctl_drv.h"
#include "sysctl_pmbus.h"
#define SLAVE_ADDR_MAX (1 << 7)
#define CPU_VOL_MIN 500
static void __iomem *g_sysctl_pmbus_base[CHIP_ID_NUM_MAX];
static void his_sysctrl_reg_rd(const void __iomem *addr, u32 reg, unsigned int *val)
{
*val = readl(addr + reg);
}
static void his_sysctrl_reg_wr(void __iomem *addr, u32 reg, unsigned int val)
{
writel(val, addr + reg);
}
static int sysctl_pmbus_init(void)
{
u32 chip_id;
u64 addr;
u64 chip_module_base;
pr_info("[INFO] %s.\n", __func__);
chip_module_base = get_chip_base();
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
addr = (u64)chip_id * chip_module_base + PMBUS_REG_BASE;
g_sysctl_pmbus_base[chip_id] = ioremap(addr, (u64)0x10000);
if (!g_sysctl_pmbus_base[chip_id])
pr_err("chip=%u, pmbus ioremap failed\n", chip_id);
}
return SYSCTL_ERR_OK;
}
static void sysctl_pmbus_deinit(void)
{
u8 chip_id;
for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) {
if (g_sysctl_pmbus_base[chip_id])
iounmap((void *)g_sysctl_pmbus_base[chip_id]);
}
}
int sysctl_reg_read8(u64 addr, u32 data_len)
{
u32 loop;
u8 data;
void __iomem *reg_addr = NULL;
void __iomem *reg_base = NULL;
if ((data_len >= 0x10000) || (data_len == 0)) {
pr_err("%s: data_len[%u] is ERR, be range (0x0--0x10000).\n",
__func__, data_len);
return SYSCTL_ERR_PARAM;
}
reg_base = ioremap(addr, (u64)0x10000);
if (!reg_base) {
pr_err("%s ioremap failed\n", __func__);
return SYSCTL_ERR_FAILED;
}
for (loop = 0; loop < data_len; loop++) {
reg_addr = reg_base + loop;
data = readb(reg_addr);
pr_info("0x%llx: 0x%2.2x\n", addr + loop, data);
}
if (reg_base)
iounmap((void *)reg_base);
return SYSCTL_ERR_OK;
}
int sysctl_reg_write8(u64 addr, u8 data)
{
void __iomem *reg_base = NULL;
reg_base = ioremap(addr, (u64)0x100);
if (!reg_base) {
pr_err("%s ioremap failed\n", __func__);
return SYSCTL_ERR_FAILED;
}
writeb(data, reg_base);
if (reg_base)
iounmap((void *)reg_base);
return SYSCTL_ERR_OK;
}
int sysctl_reg_read32(u64 addr, u32 data_len)
{
u32 loop;
u32 data;
void __iomem *reg_addr = NULL;
void __iomem *reg_base = NULL;
if ((data_len >= 0x10000) ||
(data_len == 0) ||
((addr % 0x4) != 0)) {
pr_err("%s: data_len[%u] is ERR, be range[0x0--0x10000].\n", __func__, data_len);
return SYSCTL_ERR_PARAM;
}
reg_base = ioremap(addr, (u64)0x10000);
if (!reg_base) {
pr_err("%s ioremap failed\n", __func__);
return SYSCTL_ERR_FAILED;
}
for (loop = 0; loop < data_len; loop++) {
reg_addr = reg_base + loop * 0x4;
data = readl(reg_addr);
pr_info("0x%llx: 0x%8.8x\n", addr + (u64)loop * 0x4, data);
}
if (reg_base)
iounmap((void *)reg_base);
return SYSCTL_ERR_OK;
}
int sysctl_reg_write32(u64 addr, u32 data)
{
void __iomem *reg_base = NULL;
if ((addr % 0x4) != 0) {
pr_err("%s: reg_addr is err.\n", __func__);
return SYSCTL_ERR_PARAM;
}
reg_base = ioremap(addr, (u64)0x100);
if (!reg_base) {
pr_err("%s ioremap failed\n", __func__);
return SYSCTL_ERR_FAILED;
}
writel(data, reg_base);
if (reg_base)
iounmap((void *)reg_base);
return SYSCTL_ERR_OK;
}
int InitPmbus(u8 chip_id)
{
void __iomem *base = NULL;
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("[sysctl pmbus]read chip_id range[0x0-0x3]is err!\n");
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
debug_sysctrl_print("Initialize Pmbus\n");
his_sysctrl_reg_wr(base, PMBUS_WR_OPEN_OFFSET, 0x1ACCE551);
his_sysctrl_reg_wr(base, AVS_WR_OPEN_OFFSET, 0x1ACCE551);
his_sysctrl_reg_wr(base, I2C_LOCK_OFFSET, 0x36313832);
his_sysctrl_reg_wr(base, I2C_ENABLE_OFFSET, 0);
his_sysctrl_reg_wr(base, I2C_CON_OFFSET, 0x63);
/* ulSclHigh > 1us */
his_sysctrl_reg_wr(base, I2C_SS_SCL_HCNT_OFFSET, I2C_SS_SCLHCNT);
/* ulSclLow > 1.5us */
his_sysctrl_reg_wr(base, I2C_SS_SCL_LCNT_OFFSET, I2C_SS_SCLLCNT);
/* set sda_hold_fs 1us > 250ns */
his_sysctrl_reg_wr(base, I2C_SDA_HOLD_OFFSET, I2C_SS_SDA_HOLD_FS);
his_sysctrl_reg_wr(base, I2C_ENABLE_OFFSET, 0x1);
debug_sysctrl_print("Initialize Pmbus end\n");
return 0;
}
int DeInitPmbus(u8 chip_id)
{
void __iomem *base = NULL;
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("[sysctl pmbus]read chip_id range[0x0-0x3]is err!\n");
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
his_sysctrl_reg_wr(base, PMBUS_WR_OPEN_OFFSET, 0);
his_sysctrl_reg_wr(base, AVS_WR_OPEN_OFFSET, 0);
return 0;
}
int sysctl_pmbus_cfg(u8 chip_id, u8 addr, u8 page, u32 slave_addr)
{
void __iomem *base = NULL;
if ((chip_id >= CHIP_ID_NUM_MAX) || (slave_addr >= SLAVE_ADDR_MAX)) {
pr_err("[sysctl pmbus] cfg param err,chipid=0x%x,slave_addr=0x%x\n",
chip_id, slave_addr);
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, addr);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | page);
return 0;
}
int sysctl_pmbus_write_common(u8 chip_id, u32 slave_addr, u32 data_len, u8 *buf)
{
u32 i = 0;
u32 temp = 0;
u32 loop = 0x1000;
u32 temp_data;
void __iomem *base = NULL;
if ((chip_id >= CHIP_ID_NUM_MAX) ||
(slave_addr >= SLAVE_ADDR_MAX) ||
(!data_len) || (data_len > PMBUS_WRITE_LEN_MAX) ||
(!buf)) {
pr_err("[sysctl pmbus] write param err,chipid=0x%x,data_len=0x%x,slave_addr=0x%x!\n",
chip_id, data_len, slave_addr);
return SYSCTL_ERR_PARAM;
}
/* clear all interrupt */
base = g_sysctl_pmbus_base[chip_id];
his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3ffff);
/* send: slave_addr[7bit] + write[1bit] */
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr);
/* write data */
for (i = 0; i < data_len - 1; i++)
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, buf[i]);
/* last data should send stop */
temp_data = buf[i];
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | temp_data);
/* poll until send done */
for (;;) {
udelay(100); /* Delay 100 subtleties */
his_sysctrl_reg_rd(base, I2C_INTR_RAW_OFFSET, &temp);
/* send data failed */
if (temp & I2C_TX_ABRT) {
his_sysctrl_reg_rd(base, I2C_TX_ABRT_SRC_REG, &temp);
pr_err("[sysctl pmbus]write data fail, chip_id:0x%x,slave_addr:0x%x\r\n",
chip_id, slave_addr);
his_sysctrl_reg_rd(base, I2C_CLR_TX_ABRT_REG, &temp);
return SYSCTL_ERR_FAILED;
}
his_sysctrl_reg_rd(base, I2C_STATUS_REG, &temp);
/* send done */
if (temp & I2C_TX_FIFO_EMPTY) {
his_sysctrl_reg_rd(base, I2C_TX_FIFO_DATA_NUM_REG, &temp);
if (temp == 0)
break;
}
loop--;
if (loop == 0) {
pr_err("[sysctl pmbus]write data retry fail, chip_id:0x%x,slave_addr:0x%x\r\n",
chip_id, slave_addr);
return SYSCTL_ERR_FAILED;
}
}
return SYSCTL_ERR_OK;
}
int sysctl_pmbus_write(u8 chip_id, u8 addr, u32 slave_addr, u32 data_len, u32 buf)
{
#define TMP_LEN_MAX 5
u8 i;
u8 tmp[TMP_LEN_MAX] = {0};
if (data_len > DATA_NUM_MAX) {
pr_err("[sysctl pmbus] write param err,data_len=0x%x!\n", data_len);
return SYSCTL_ERR_PARAM;
}
tmp[0] = addr;
for (i = 0; i < data_len; i++)
tmp[i + 1] = (buf >> (i * 0x8)) & 0xff;
return sysctl_pmbus_write_common(chip_id, slave_addr, data_len + sizeof(addr), &tmp[0]);
}
static int sysctl_pmbus_read_pre(void __iomem *base, u32 cmd_len, u8 *cmd, u32 slave_addr, u32 data_len)
{
u32 i = 0;
u32 fifo_num = 0;
u32 temp_byte = 0;
if (base == NULL) {
pr_err("[sysctl pmbus] pmbus_read_pre, base is null.\n");
return SYSCTL_ERR_PARAM;
}
/* clear all interrupt */
his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3ffff);
/* clear rx fifo */
his_sysctrl_reg_rd(base, I2C_RXFLR_OFFSET, &fifo_num);
for (i = 0; i < fifo_num; i++)
his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte);
/* send cmd */
if (cmd_len) {
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr);
for (i = 0; i < cmd_len; i++)
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, cmd[i]);
}
/* read data */
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x3 << 0x8) | slave_addr);
i = data_len;
while ((i - 1) > 0) {
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x100);
i--;
}
/* last data should send stop */
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x500);
return 0;
}
static int sysctl_pmbus_wait_data(void __iomem *base, u32 data_len)
{
u32 i = 0;
u32 loop = 0x100;
u32 fifo_num = 0;
u32 temp_byte = 0;
if (base == NULL) {
pr_err("[sysctl pmbus] pmbus_wait_data, base is null.\n");
return SYSCTL_ERR_PARAM;
}
while (loop) {
udelay(100); /* Delay 100 subtleties */
his_sysctrl_reg_rd(base, I2C_RXFLR_OFFSET, &fifo_num);
debug_sysctrl_print("[sysctl_pmbus_read_byte]read pmbus, read rx fifo num:%d\r\n", fifo_num);
if (data_len == fifo_num) {
debug_sysctrl_print("[sysctl_pmbus_read_byte]read pmbus, Loop:%d\r\n", 0xffff - loop);
break;
}
loop -= 1;
}
if (loop == 0) {
pr_err("[sysctl pmbus]read pmbus error, I2C_RXFLR = %d\n", fifo_num);
for (i = 0; i < fifo_num; i++)
his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte);
his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3FFFF);
return SYSCTL_ERR_TIMEOUT;
}
return SYSCTL_ERR_OK;
}
int sysctl_pmbus_read_common(u8 chip_id, struct pmbus_read_op *op)
{
u32 ret;
u32 i = 0;
u32 temp_byte = 0;
void __iomem *base = NULL;
if ((chip_id >= CHIP_ID_NUM_MAX) || (!op)) {
pr_err("[sysctl pmbus]read param err,chipid=0x%x!\n", chip_id);
return SYSCTL_ERR_PARAM;
}
if ((op->slave_addr >= SLAVE_ADDR_MAX) ||
(!op->data_len) || ((op->cmd_len + op->data_len) > PMBUS_READ_LEN_MAX) ||
(!op->data) || ((op->cmd_len) && (!op->cmd))) {
pr_err("[sysctl pmbus]read param err,data_len=0x%x,cmd_len=0x%x,slave_addr=0x%x\n",
op->data_len, op->cmd_len, op->slave_addr);
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
ret = sysctl_pmbus_read_pre(base, op->cmd_len, op->cmd, op->slave_addr, op->data_len);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = sysctl_pmbus_wait_data(base, op->data_len);
if (ret != SYSCTL_ERR_OK)
return ret;
for (i = 0; i < op->data_len; i++) {
his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte);
op->data[i] = temp_byte & 0xff;
}
return SYSCTL_ERR_OK;
}
int sysctl_pmbus_read(u8 chip_id, u8 addr, u32 slave_addr, u32 data_len, u32 *buf)
{
u32 ret;
u32 i = 0;
u32 temp_byte = 0;
u32 temp = 0;
void __iomem *base = NULL;
if ((chip_id >= CHIP_ID_NUM_MAX) ||
(data_len > DATA_NUM_MAX) ||
(data_len == 0x0) ||
(slave_addr >= SLAVE_ADDR_MAX)) {
pr_err("[sysctl pmbus]read param err,chipid=0x%x,data_len=0x%x,slave_addr=0x%x!\n",
chip_id, data_len, slave_addr);
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
ret = sysctl_pmbus_read_pre(base, sizeof(addr), &addr, slave_addr, data_len);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = sysctl_pmbus_wait_data(base, data_len);
if (ret != SYSCTL_ERR_OK)
return ret;
for (i = 0; i < data_len; i++) {
his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte);
temp |= temp_byte << (i * 0x8);
}
pr_info("[sysctl pmbus]read pmbus temp = 0x%x\n", temp);
if (!buf) {
pr_err("[sysctl pmbus]read pmbus error, buf is NULL\n");
return SYSCTL_ERR_PARAM;
}
*buf = temp;
return 0;
}
int sysctl_cpu_voltage_password_cfg(u8 chip_id, u32 slave_addr)
{
void __iomem *base = NULL;
if ((chip_id >= CHIP_ID_NUM_MAX) || (slave_addr >= SLAVE_ADDR_MAX)) {
pr_err("[sysctl pmbus] voltage_password_cfg param err,chipid=0x%x,slave_addr=0x%x!\n",
chip_id, slave_addr);
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x27);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x7c);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | 0xb3);
return 0;
}
static int hi_vrd_info_check_params(u8 chip_id, u8 page, u32 data_len, u32 slave_addr)
{
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("[sysctl pmbus] read chip_id range[0x0-0x3]is err!\n");
return SYSCTL_ERR_PARAM;
}
if (page >= PAGE_NUM_MAX) {
pr_err("[sysctl pmbus] read page range[0x0-0x6f]is err!\n");
return SYSCTL_ERR_PARAM;
}
if ((data_len > DATA_NUM_MAX) || (data_len == 0)) {
pr_err("[sysctl pmbus] read data len range[0x1-0x4]is err!\n");
return SYSCTL_ERR_PARAM;
}
if (slave_addr >= SLAVE_ADDR_MAX) {
pr_err("[sysctl pmbus] vrd_info slave_addr=0x%x err!\n", slave_addr);
return SYSCTL_ERR_PARAM;
}
return SYSCTL_ERR_OK;
}
int hi_vrd_info_get(u8 chip_id, u8 addr, u8 page, u32 slave_addr, u32 data_len, u32 *buf)
{
u32 retry_time = 0x10;
u32 ret;
ret = hi_vrd_info_check_params(chip_id, page, data_len, slave_addr);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = InitPmbus(chip_id);
if (ret != SYSCTL_ERR_OK)
return ret;
/* read val */
ret = sysctl_pmbus_cfg(chip_id, 0x0, page, slave_addr);
if (ret != SYSCTL_ERR_OK)
return ret;
while (retry_time) {
ret = sysctl_pmbus_read(chip_id, addr, slave_addr, data_len, buf);
if (ret != SYSCTL_ERR_TIMEOUT)
break;
retry_time--;
udelay(100); /* Delay 100 subtleties */
}
if (!retry_time) {
pr_err("[sysctl pmbus] read voltage mode time out!\n");
ret = DeInitPmbus(chip_id);
if (ret != SYSCTL_ERR_OK)
return ret;
return SYSCTL_ERR_TIMEOUT;
}
if (!buf) {
pr_err("[sysctl pmbus]read vrd info error, buf is NULL\n");
return SYSCTL_ERR_PARAM;
}
pr_info("read val:0x%x !\n", *buf);
ret = DeInitPmbus(chip_id);
if (ret != SYSCTL_ERR_OK)
return ret;
return 0;
}
int sysctl_cpu_voltage_read(u8 chip_id, u8 loop, u32 slave_addr)
{
pmbus_vout_mode vout_mode;
u32 val = 0;
u32 ret;
if (chip_id >= CHIP_ID_NUM_MAX) {
pr_err("[sysctl pmbus] read chip_id range[0x0-0x3]is err!\n");
return SYSCTL_ERR_PARAM;
}
if (loop >= VOL_LOOP_NUM_MAX) {
pr_err("[sysctl pmbus] read voltage loop range[0x0-0x2]is err!\n");
return SYSCTL_ERR_PARAM;
}
if (slave_addr >= SLAVE_ADDR_MAX) {
pr_err("[sysctl pmbus] cpu_voltage_read slave_addr=0x%x err!\n", slave_addr);
return SYSCTL_ERR_PARAM;
}
/* read voltage mode */
ret = hi_vrd_info_get(chip_id, 0x20, loop, slave_addr, 0x1, (u32 *)&vout_mode);
if (ret)
return ret;
if (vout_mode.bits.vout_mode_surport != 0x1)
pr_err("[sysctl pmbus]Warning: voltage mode is not supported!\n");
/* read voltage vlave */
ret = hi_vrd_info_get (chip_id, 0x8b, loop, slave_addr, 0x2, (u32 *)&val);
if (ret)
return ret;
if (vout_mode.bits.vid_table == CPU_VOUT_MODE_VR125)
val = 2 * ((val - 1) * 5 + 250); /* 2 1 5 and 250 are the number of relationships. */
else if (vout_mode.bits.vid_table == CPU_VOUT_MODE_VR120)
val = (val - 1) * 5 + 250; /* 1 5 and 250 are the number of relationships. */
else
pr_err("vout mode[0x%x] is err, voltage is invalid!\n", vout_mode.bits.vid_table);
pr_info("voltage :%dmV!\n", val);
return 0;
}
static int sysctl_cpu_convert_vol_to_vid(u32 vid_table, u32 value, u32 *vid)
{
if (vid_table == CPU_VOUT_MODE_VR125) {
*vid = (value / 2 - 250) / 5 + 1; /* 2 1 5 and 250 are the number of relationships. */
} else if (vid_table == CPU_VOUT_MODE_VR120) {
*vid = (value - 250) / 5 + 1; /* 1 5 and 250 are the number of relationships. */
} else {
pr_err("voltage adjust vout mode[0x%x] is err!\n", vid_table);
return SYSCTL_ERR_FAILED;
}
return SYSCTL_ERR_OK;
}
int sysctl_cpu_voltage_adjust(u8 chip_id, u8 loop, u32 slave_addr, u32 value)
{
u32 ret;
u32 vid;
pmbus_vout_mode vout_mode;
void __iomem *base = NULL;
if ((chip_id >= CHIP_ID_NUM_MAX) ||
(slave_addr >= SLAVE_ADDR_MAX) ||
(value < CPU_VOL_MIN)) {
pr_err("[sysctl pmbus]cpu_voltage_adjust param err,chipid=0x%x,slave_addr=0x%x,value=0x%x!\n",
chip_id, slave_addr, value);
return SYSCTL_ERR_PARAM;
}
base = g_sysctl_pmbus_base[chip_id];
/* read voltage mode */
ret = hi_vrd_info_get(chip_id, 0x20, loop, slave_addr, 0x1, (u32 *)&vout_mode);
if (ret)
return ret;
if (vout_mode.bits.vout_mode_surport != 0x1)
pr_err("[sysctl pmbus]Warning: voltage mode is not supported!\n");
ret = sysctl_cpu_convert_vol_to_vid(vout_mode.bits.vid_table, value, &vid);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = InitPmbus(chip_id);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = sysctl_pmbus_cfg(chip_id, 0x0, 0x3f, slave_addr);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = sysctl_cpu_voltage_password_cfg (chip_id, slave_addr);
if (ret != SYSCTL_ERR_OK)
return ret;
ret = sysctl_pmbus_cfg(chip_id, 0x0, loop, slave_addr);
if (ret != SYSCTL_ERR_OK)
return ret;
his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3ffff);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x21);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0xff & vid);
his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | (0xff & (vid >> 0x8)));
udelay(100); /* Delay 100 subtleties */
his_sysctrl_reg_wr(base, PMBUS_WR_OPEN_OFFSET, 0x0);
his_sysctrl_reg_wr(base, AVS_WR_OPEN_OFFSET, 0x0);
return SYSCTL_ERR_OK;
}
int hip_sysctl_pmbus_init(void)
{
int ret;
ret = sysctl_pmbus_init();
if (ret != SYSCTL_ERR_OK)
pr_err("[ERROR] %s fail, ret:[0x%x].\n", __func__, ret);
return ret;
}
void hip_sysctl_pmbus_exit(void)
{
sysctl_pmbus_deinit();
pr_info("[INFO] hip sysctl pmbus exit.\n");
}
EXPORT_SYMBOL(sysctl_cpu_voltage_read);
EXPORT_SYMBOL(hi_vrd_info_get);
EXPORT_SYMBOL(sysctl_cpu_voltage_adjust);
EXPORT_SYMBOL(sysctl_pmbus_write);
EXPORT_SYMBOL(sysctl_pmbus_read);
EXPORT_SYMBOL(sysctl_pmbus_write_common);
EXPORT_SYMBOL(sysctl_pmbus_read_common);
EXPORT_SYMBOL(InitPmbus);
EXPORT_SYMBOL(DeInitPmbus);
drivers/soc/hisilicon/sysctl/sysctl_pmbus.h 已删除 100644 → 0
浏览文件 @ 463a23d0
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Hisilicon Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _HIS_SYSCTL_PMBUS_H_
#define _HIS_SYSCTL_PMBUS_H_
#define VOL_LOOP_NUM_MAX (0x3)
#define PAGE_NUM_MAX (0x6f)
#define DATA_NUM_MAX (0x4)
#define I2C_FIFO_DEPTH (256)
/* slave_addr use 1 fifo */
#define PMBUS_READ_LEN_MAX (I2C_FIFO_DEPTH - 1)
/* slave_addr use 2 fifo */
#define PMBUS_WRITE_LEN_MAX (I2C_FIFO_DEPTH - 2)
#define I2C_TX_ABRT (0x040)
#define I2C_TX_ABRT_SRC_REG (0x0880)
#define I2C_CLR_TX_ABRT_REG (0x0854)
#define I2C_STATUS_REG (0x0870)
#define I2C_TX_FIFO_EMPTY (0x04)
#define I2C_TX_FIFO_DATA_NUM_REG (0x0874)
#define I2C_SS_SCLHCNT 0x3db
#define I2C_SS_SCLLCNT 0x3e6
#define I2C_SS_SDA_HOLD_FS 0xfa
/* AVS_REG_GEN */
#define AVS_WR_OPEN_OFFSET 0x0004
#define AVS_INT_STATUS_OFFSET 0x0008
#define AVS_ERROR_INT_STATUS_OFFSET 0x000C
#define AVS_PARITY_INT_STATUS_OFFSET 0x0010
#define AVS_INT_CLEAR_OFFSET 0x0020
#define AVS_ERROR_INT_CLEAR_OFFSET 0x0024
#define AVS_INT_MASK_OFFSET 0x0034
/* PMBUSIF_REG_GEN */
#define I2C_CON_OFFSET 0x0800
#define I2C_DATA_CMD_OFFSET 0x0810
#define I2C_SS_SCL_HCNT_OFFSET 0x0814
#define I2C_SS_SCL_LCNT_OFFSET 0x0818
#define I2C_FS_SCL_HCNT_OFFSET 0x081C
#define I2C_FS_SCL_LCNT_OFFSET 0x0820
#define I2C_INTR_STAT_OFFSET 0x082C
#define I2C_INTR_MASK_OFFSET 0x0830
#define I2C_INTR_RAW_OFFSET 0x0834
#define I2C_ENABLE_OFFSET 0x086C
#define I2C_RXFLR_OFFSET 0x0878
#define I2C_SDA_HOLD_OFFSET 0x087C
#define I2C_SCL_SWITCH_OFFSET 0x08A0
#define I2C_SCL_SIM_OFFSET 0x08A4
#define I2C_LOCK_OFFSET 0x08AC
#define I2C_SDA_SWITCH_OFFSET 0x08B0
#define I2C_SDA_SIM_OFFSET 0x08B4
#define I2C_PMBUS_CTRL_OFFSET 0x0904
#define I2C_LOW_TIMEOUT_OFFSET 0x0908
#define I2C_PMBUS_SCL_DET_OFFSET 0x092C
#define I2C_PMBUS_IDLECNT_OFFSET 0x0930
#define I2C_PMBUS_RST_OFFSET 0x0934
/* PMBUS_PROC_REG_GEN */
#define PMBUS_REG_BASE (0x000094180000)
#define PMBUS_WR_OPEN_OFFSET 0x0A04
#define PMBUS_INT_OFFSET 0x0A08
#define PMBUS_INT_CLR_OFFSET 0x0A10
#define PMBUS_PROC_TIMEOUT_TH_OFFSET 0x0A1C
#define PMBUS_VOLTAGE_STABLE_OFFSET 0x0A20
#define READ_VOUD_INTERVAL_OFFSET 0x0A28
#define PMBUS_OTHER_CFG_OFFSET 0x0A2C
#define VOLTAGE_ADDR_CFG_OFFSET 0x0A30
#define VOLTAGE_CONVERT_CFG_OFFSET 0x0A34
#define STATUS_RPT_OFFSET 0x0AA4
#define STATUS_ERR_RPT_OFFSET 0x0AA8
struct pmbus_read_op {
u32 slave_addr;
u32 cmd_len;
u32 data_len;
u8 *cmd;
u8 *data;
};
/* Define the union pmbus_vout_mode */
typedef union {
/* Define the struct bits */
struct {
unsigned int vid_table : 5 ; /* [4..0] */
unsigned int vout_mode_surport : 3 ; /* [7..5] */
unsigned int reserved_0 : 24 ; /* [31..8] */
} bits;
/* Define an unsigned member */
unsigned int u32;
} pmbus_vout_mode;
enum {
CPU_VOUT_MODE_INVALID = 0,
CPU_VOUT_MODE_VR120,
CPU_VOUT_MODE_VR125,
CPU_VOUT_MODE_MAX,
};
int hip_sysctl_pmbus_init(void);
void hip_sysctl_pmbus_exit(void);
#endif
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