clk: imx7d: Fix the DDR PLL enable bit

Commit ad149724 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.
Reported-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

drivers/clk/imx/clk-pllv3.c

@@ -453,7 +453,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 		ops = &clk_pllv3_enet_ops;
 		break;
 	case IMX_PLLV3_DDR_IMX7:
-		pll->power_bit = IMX7_ENET_PLL_POWER;
+		pll->power_bit = IMX7_DDR_PLL_POWER;
 		ops = &clk_pllv3_av_ops;
 		break;
 	default: