configs: disable CONFIG_RODATA_FULL_DEFAULT_ENABLED
euler inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4VPIB CVE: NA ------------------------------------------------- If this config is enabled, block mapping is not used. The linear address page table is mapped to 4 KB. As a result, the TLB miss rate is high, affecting performance. For examples, tested by libMicro benchmark: enable disable Improve memsetP2_10m 3540.37760 2129.715200 66.2% memset_4k 0.38400 0.204800 87.5% mprot_twz8k 7.16800 3.072000 133.3% unmap_ra8k 7.93600 4.096000 93.8% unmap_wa128k 68.86400 33.024000 108.5% This additional enhancement can be turned on with rodata=full if this option is set to 'n'. Signed-off-by: NChao Liu <liuchao173@huawei.com> Reviewed-by: NKai Liu <kai.liu@suse.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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