提交 b11d4c1f 编写于 作者: P Paul Burton 提交者: Ralf Baechle

irqchip: mips-gic: Move various definitions to the driver

Move the definitions of macros used to convert between hardware IRQ
numbers & shared or local interrupt numbers into the irqchip driver,
which is all that should ever need to care about them.

Remove GIC_CPU_TO_VEC_OFFSET() in the process since it's never used.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17039/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 3ee50dcb
......@@ -10,8 +10,6 @@
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
#include <linux/irqchip/mips-gic.h>
/*
* Interrupts 0..15 are used for Malta ISA compatible interrupts
*/
......@@ -62,7 +60,4 @@
#define MSC01E_INT_PERFCTR 10
#define MSC01E_INT_CPUCTR 11
/* GIC external interrupts */
#define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3)
#endif /* !(_MIPS_MALTAINT_H) */
......@@ -23,6 +23,22 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
#define GIC_MAX_INTRS 256
/* Add 2 to convert GIC CPU pin to core interrupt */
#define GIC_CPU_PIN_OFFSET 2
/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
#define GIC_PIN_TO_VEC_OFFSET 1
/* Convert between local/shared IRQ number and GIC HW IRQ number. */
#define GIC_LOCAL_HWIRQ_BASE 0
#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
unsigned int gic_present;
void __iomem *mips_gic_base;
......
......@@ -11,8 +11,6 @@
#include <linux/clocksource.h>
#include <linux/ioport.h>
#define GIC_MAX_INTRS 256
/* GIC Address Space */
#define USM_VISIBLE_SECTION_OFS 0x10000
#define USM_VISIBLE_SECTION_SIZE 0x10000
......@@ -21,23 +19,6 @@
#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
/* Add 2 to convert GIC CPU pin to core interrupt */
#define GIC_CPU_PIN_OFFSET 2
/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
#define GIC_CPU_TO_VEC_OFFSET 2
/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
#define GIC_PIN_TO_VEC_OFFSET 1
/* Convert between local/shared IRQ number and GIC HW IRQ number. */
#define GIC_LOCAL_HWIRQ_BASE 0
#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
#ifdef CONFIG_MIPS_GIC
extern unsigned int gic_present;
......
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