提交 afdd8b61 编写于 作者: M Murali Karicheri 提交者: Santosh Shilimkar

ARM: keystone: dts: fix typo in the ddr3 pllclk node name

Fix following typo
 ddr3allclk -> ddr3apllclk
 ddr3bllclk -> ddr3bpllclk
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
上级 b8273f2e
......@@ -31,7 +31,7 @@ clocks {
reg-names = "control";
};
ddr3allclk: ddr3apllclk@2620360 {
ddr3apllclk: ddr3apllclk@2620360 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-clock";
clocks = <&refclkddr3a>;
......@@ -40,7 +40,7 @@ clocks {
reg-names = "control";
};
ddr3bllclk: ddr3bpllclk@2620368 {
ddr3bpllclk: ddr3bpllclk@2620368 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-clock";
clocks = <&refclkddr3b>;
......
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