arm64: dts: ti: k3-j7200: Correct the d-cache-sets info

stable inclusion
from stable-v5.10.94
commit a001a15ab3748deaf984076f0c4d96810258e182
bugzilla: https://gitee.com/openeuler/kernel/issues/I531X9

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a001a15ab3748deaf984076f0c4d96810258e182

--------------------------------

[ Upstream commit a172c869 ]

A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways
512 ways / 2 (Dcache is 2-way per set) = 256 sets.

So, correct the d-cache-sets info.

[1] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed88 ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: NPeng Fan <peng.fan@nxp.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NPratyush Yadav <p.yadav@ti.com>
Reviewed-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.comSigned-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>

arch/arm64/boot/dts/ti/k3-j7200.dtsi

@@ -60,7 +60,7 @@
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
+			d-cache-sets = <256>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -74,7 +74,7 @@
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
+			d-cache-sets = <256>;
 			next-level-cache = <&L2_0>;
 		};
 	};