提交 a8274e41 编写于 作者: V Valentin Schneider 提交者: Yang Yingliang

irqchip/gic-v2, v3: Prevent SW resends entirely

mainline inclusion
from mainline-5.10
commit 1b57d91b
category: bugfix
bugzilla: NA
CVE: NA

-------------------------------------------------

The GIC irqchips can now use a HW resend when a retrigger is invoked by
check_irq_resend(). However, should the HW resend fail, check_irq_resend()
will still attempt to trigger a SW resend, which is still a bad idea for
the GICs.

Prevent this from happening by setting IRQD_HANDLE_ENFORCE_IRQCTX on all
GIC IRQs. Technically per-cpu IRQs do not need this, as their flow handlers
never set IRQS_PENDING, but this aligns all IRQs wrt context enforcement:
this also forces all GIC IRQ handling to happen in IRQ context (as defined
by in_irq()).
Signed-off-by: NValentin Schneider <valentin.schneider@arm.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200730170321.31228-3-valentin.schneider@arm.comSigned-off-by: NLiao Chang <liaochang1@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 76704c53
...@@ -1322,6 +1322,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, ...@@ -1322,6 +1322,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw) irq_hw_number_t hw)
{ {
struct irq_chip *chip = &gic_chip; struct irq_chip *chip = &gic_chip;
struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
if (static_branch_likely(&supports_deactivate_key)) if (static_branch_likely(&supports_deactivate_key))
chip = &gic_eoimode1_chip; chip = &gic_eoimode1_chip;
...@@ -1348,7 +1349,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, ...@@ -1348,7 +1349,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_domain_set_info(d, irq, hw, chip, d->host_data, irq_domain_set_info(d, irq, hw, chip, d->host_data,
handle_fasteoi_irq, NULL, NULL); handle_fasteoi_irq, NULL, NULL);
irq_set_probe(irq); irq_set_probe(irq);
irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); irqd_set_single_target(irqd);
} }
/* LPIs */ /* LPIs */
if (hw >= 8192 && hw < GIC_ID_NR) { if (hw >= 8192 && hw < GIC_ID_NR) {
...@@ -1358,6 +1359,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, ...@@ -1358,6 +1359,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
handle_fasteoi_irq, NULL, NULL); handle_fasteoi_irq, NULL, NULL);
} }
/* Prevents SW retriggers which mess up the ACK/EOI ordering */
irqd_set_handle_enforce_irqctx(irqd);
return 0; return 0;
} }
......
...@@ -978,6 +978,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, ...@@ -978,6 +978,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw) irq_hw_number_t hw)
{ {
struct gic_chip_data *gic = d->host_data; struct gic_chip_data *gic = d->host_data;
struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
if (hw < 32) { if (hw < 32) {
irq_set_percpu_devid(irq); irq_set_percpu_devid(irq);
...@@ -988,8 +989,11 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, ...@@ -988,8 +989,11 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
handle_fasteoi_irq, NULL, NULL); handle_fasteoi_irq, NULL, NULL);
irq_set_probe(irq); irq_set_probe(irq);
irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); irqd_set_single_target(irqd);
} }
/* Prevents SW retriggers which mess up the ACK/EOI ordering */
irqd_set_handle_enforce_irqctx(irqd);
return 0; return 0;
} }
......
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