提交 a493f74a 编写于 作者: Z zhenpengzheng 提交者: Zheng Zengkai

net: txgbe: Add support for Netswift 10G NIC

driver inclusion
category: feature
bugzilla: 50777
CVE: NA

-------------------------------------------------------------------------
This patch contains main code of Netswift 10G NIC Driver which supports
devices as follows:
1) Netswift SP1000A 8088:1001[VID:DID]
2) Netswift WX1820AL 8088:2001[VID:DID]
Signed-off-by: Nzhenpengzheng <zhenpengzheng@net-swift.com>
Signed-off-by: NZhen Lei <thunder.leizhen@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
上级 abdcf183
无相关合并请求
......@@ -83,6 +83,7 @@ source "drivers/net/ethernet/i825xx/Kconfig"
source "drivers/net/ethernet/ibm/Kconfig"
source "drivers/net/ethernet/intel/Kconfig"
source "drivers/net/ethernet/xscale/Kconfig"
source "drivers/net/ethernet/netswift/Kconfig"
config JME
tristate "JMicron(R) PCI-Express Gigabit Ethernet support"
......
......@@ -95,3 +95,4 @@ obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/
obj-$(CONFIG_NET_VENDOR_PENSANDO) += pensando/
obj-$(CONFIG_NET_VENDOR_NETSWIFT) += netswift/
# SPDX-License-Identifier: GPL-2.0-only
#
# Netswift network device configuration
#
config NET_VENDOR_NETSWIFT
bool "netswift devices"
default y
help
If you have a network (Ethernet) card belonging to this class, say Y.
Note that the answer to this question doesn't directly affect the
kernel: saying N will just cause the configurator to skip all
the questions about Netswift NICs. If you say Y, you will be asked for
your specific card in the following questions.
if NET_VENDOR_NETSWIFT
source "drivers/net/ethernet/netswift/txgbe/Kconfig"
endif # NET_VENDOR_NETSWIFT
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Netswift network device drivers.
#
obj-$(CONFIG_TXGBE) += txgbe/
#
# Netswift driver configuration
#
config TXGBE
tristate "Netswift 10G Network Interface Card"
default n
depends on PCI_MSI && NUMA && PCI_IOV && DCB
help
This driver supports Netswift 10G Ethernet cards.
To compile this driver as part of the kernel, choose Y here.
If unsure, choose N.
The default is N.
# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
#
# Makefile for the Netswift 10GbE PCI Express ethernet driver
#
obj-$(CONFIG_TXGBE) += txgbe.o
txgbe-objs := txgbe_main.o txgbe_ethtool.o \
txgbe_hw.o txgbe_phy.o txgbe_bp.o \
txgbe_mbx.o txgbe_mtd.o txgbe_param.o txgbe_lib.o txgbe_ptp.o
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/*
* WangXun 10 Gigabit PCI Express Linux driver
* Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*/
#ifndef _TXGBE_BP_H_
#define _TXGBE_BP_H_
#include "txgbe.h"
#include "txgbe_hw.h"
#define CL72_KR_TRAINING_ON
/* Backplane AN73 Base Page Ability struct*/
typedef struct TBKPAN73ABILITY {
unsigned int nextPage; //Next Page (bit0)
unsigned int linkAbility; //Link Ability (bit[7:0])
unsigned int fecAbility; //FEC Request (bit1), FEC Enable (bit0)
unsigned int currentLinkMode; //current link mode for local device
} bkpan73ability;
int txgbe_kr_intr_handle(struct txgbe_adapter *adapter);
void txgbe_bp_down_event(struct txgbe_adapter *adapter);
void txgbe_bp_watchdog_event(struct txgbe_adapter *adapter);
int txgbe_bp_mode_setting(struct txgbe_adapter *adapter);
void txgbe_bp_close_protect(struct txgbe_adapter *adapter);
#endif
/*
* WangXun 10 Gigabit PCI Express Linux driver
* Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* based on ixgbe_dcb.h, Copyright(c) 1999 - 2017 Intel Corporation.
* Contact Information:
* Linux NICS <linux.nics@intel.com>
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*/
#ifndef _TXGBE_DCB_H_
#define _TXGBE_DCB_H_
#include "txgbe_type.h"
#endif /* _TXGBE_DCB_H_ */
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/*
* WangXun 10 Gigabit PCI Express Linux driver
* Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*/
#ifndef _TXGBE_HW_H_
#define _TXGBE_HW_H_
#define TXGBE_EMC_INTERNAL_DATA 0x00
#define TXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
#define TXGBE_EMC_DIODE1_DATA 0x01
#define TXGBE_EMC_DIODE1_THERM_LIMIT 0x19
#define TXGBE_EMC_DIODE2_DATA 0x23
#define TXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
#define TXGBE_EMC_DIODE3_DATA 0x2A
#define TXGBE_EMC_DIODE3_THERM_LIMIT 0x30
/**
* Packet Type decoding
**/
/* txgbe_dec_ptype.mac: outer mac */
enum txgbe_dec_ptype_mac {
TXGBE_DEC_PTYPE_MAC_IP = 0,
TXGBE_DEC_PTYPE_MAC_L2 = 2,
TXGBE_DEC_PTYPE_MAC_FCOE = 3,
};
/* txgbe_dec_ptype.[e]ip: outer&encaped ip */
#define TXGBE_DEC_PTYPE_IP_FRAG (0x4)
enum txgbe_dec_ptype_ip {
TXGBE_DEC_PTYPE_IP_NONE = 0,
TXGBE_DEC_PTYPE_IP_IPV4 = 1,
TXGBE_DEC_PTYPE_IP_IPV6 = 2,
TXGBE_DEC_PTYPE_IP_FGV4 =
(TXGBE_DEC_PTYPE_IP_FRAG | TXGBE_DEC_PTYPE_IP_IPV4),
TXGBE_DEC_PTYPE_IP_FGV6 =
(TXGBE_DEC_PTYPE_IP_FRAG | TXGBE_DEC_PTYPE_IP_IPV6),
};
/* txgbe_dec_ptype.etype: encaped type */
enum txgbe_dec_ptype_etype {
TXGBE_DEC_PTYPE_ETYPE_NONE = 0,
TXGBE_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
TXGBE_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
TXGBE_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
TXGBE_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
};
/* txgbe_dec_ptype.proto: payload proto */
enum txgbe_dec_ptype_prot {
TXGBE_DEC_PTYPE_PROT_NONE = 0,
TXGBE_DEC_PTYPE_PROT_UDP = 1,
TXGBE_DEC_PTYPE_PROT_TCP = 2,
TXGBE_DEC_PTYPE_PROT_SCTP = 3,
TXGBE_DEC_PTYPE_PROT_ICMP = 4,
TXGBE_DEC_PTYPE_PROT_TS = 5, /* time sync */
};
/* txgbe_dec_ptype.layer: payload layer */
enum txgbe_dec_ptype_layer {
TXGBE_DEC_PTYPE_LAYER_NONE = 0,
TXGBE_DEC_PTYPE_LAYER_PAY2 = 1,
TXGBE_DEC_PTYPE_LAYER_PAY3 = 2,
TXGBE_DEC_PTYPE_LAYER_PAY4 = 3,
};
struct txgbe_dec_ptype {
u32 ptype:8;
u32 known:1;
u32 mac:2; /* outer mac */
u32 ip:3; /* outer ip*/
u32 etype:3; /* encaped type */
u32 eip:3; /* encaped ip */
u32 prot:4; /* payload proto */
u32 layer:3; /* payload layer */
};
typedef struct txgbe_dec_ptype txgbe_dptype;
void txgbe_dcb_get_rtrup2tc(struct txgbe_hw *hw, u8 *map);
u16 txgbe_get_pcie_msix_count(struct txgbe_hw *hw);
s32 txgbe_init_hw(struct txgbe_hw *hw);
s32 txgbe_start_hw(struct txgbe_hw *hw);
s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw);
s32 txgbe_read_pba_string(struct txgbe_hw *hw, u8 *pba_num,
u32 pba_num_size);
s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr);
s32 txgbe_get_bus_info(struct txgbe_hw *hw);
void txgbe_set_pci_config_data(struct txgbe_hw *hw, u16 link_status);
void txgbe_set_lan_id_multi_port_pcie(struct txgbe_hw *hw);
s32 txgbe_stop_adapter(struct txgbe_hw *hw);
s32 txgbe_led_on(struct txgbe_hw *hw, u32 index);
s32 txgbe_led_off(struct txgbe_hw *hw, u32 index);
s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u64 pools,
u32 enable_addr);
s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index);
s32 txgbe_init_rx_addrs(struct txgbe_hw *hw);
s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
u32 mc_addr_count,
txgbe_mc_addr_itr func, bool clear);
s32 txgbe_update_uc_addr_list(struct txgbe_hw *hw, u8 *addr_list,
u32 addr_count, txgbe_mc_addr_itr func);
s32 txgbe_enable_mc(struct txgbe_hw *hw);
s32 txgbe_disable_mc(struct txgbe_hw *hw);
s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw);
s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw);
s32 txgbe_fc_enable(struct txgbe_hw *hw);
bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw);
void txgbe_fc_autoneg(struct txgbe_hw *hw);
s32 txgbe_setup_fc(struct txgbe_hw *hw);
s32 txgbe_validate_mac_addr(u8 *mac_addr);
s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask);
void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask);
s32 txgbe_disable_pcie_master(struct txgbe_hw *hw);
s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr);
s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr);
s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq);
s32 txgbe_set_vmdq_san_mac(struct txgbe_hw *hw, u32 vmdq);
s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq);
s32 txgbe_insert_mac_addr(struct txgbe_hw *hw, u8 *addr, u32 vmdq);
s32 txgbe_init_uta_tables(struct txgbe_hw *hw);
s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan,
u32 vind, bool vlan_on);
s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
bool vlan_on, bool *vfta_changed);
s32 txgbe_clear_vfta(struct txgbe_hw *hw);
s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan);
s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
u16 *wwpn_prefix);
void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int pf);
void txgbe_set_vlan_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf);
void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
bool enable, int vf);
s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps);
void txgbe_set_rxpba(struct txgbe_hw *hw, int num_pb, u32 headroom,
int strategy);
s32 txgbe_set_fw_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min,
u8 build, u8 ver);
s32 txgbe_reset_hostif(struct txgbe_hw *hw);
u8 txgbe_calculate_checksum(u8 *buffer, u32 length);
s32 txgbe_host_interface_command(struct txgbe_hw *hw, u32 *buffer,
u32 length, u32 timeout, bool return_data);
void txgbe_clear_tx_pending(struct txgbe_hw *hw);
void txgbe_stop_mac_link_on_d3(struct txgbe_hw *hw);
bool txgbe_mng_present(struct txgbe_hw *hw);
bool txgbe_check_mng_access(struct txgbe_hw *hw);
s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw);
s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw);
void txgbe_enable_rx(struct txgbe_hw *hw);
void txgbe_disable_rx(struct txgbe_hw *hw);
s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
u32 speed,
bool autoneg_wait_to_complete);
int txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit);
/* @txgbe_api.h */
s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw);
s32 txgbe_init_fdir_signature(struct txgbe_hw *hw, u32 fdirctrl);
s32 txgbe_init_fdir_perfect(struct txgbe_hw *hw, u32 fdirctrl,
bool cloud_mode);
s32 txgbe_fdir_add_signature_filter(struct txgbe_hw *hw,
union txgbe_atr_hash_dword input,
union txgbe_atr_hash_dword common,
u8 queue);
s32 txgbe_fdir_set_input_mask(struct txgbe_hw *hw,
union txgbe_atr_input *input_mask, bool cloud_mode);
s32 txgbe_fdir_write_perfect_filter(struct txgbe_hw *hw,
union txgbe_atr_input *input,
u16 soft_id, u8 queue, bool cloud_mode);
s32 txgbe_fdir_erase_perfect_filter(struct txgbe_hw *hw,
union txgbe_atr_input *input,
u16 soft_id);
s32 txgbe_fdir_add_perfect_filter(struct txgbe_hw *hw,
union txgbe_atr_input *input,
union txgbe_atr_input *mask,
u16 soft_id,
u8 queue,
bool cloud_mode);
void txgbe_atr_compute_perfect_hash(union txgbe_atr_input *input,
union txgbe_atr_input *mask);
u32 txgbe_atr_compute_sig_hash(union txgbe_atr_hash_dword input,
union txgbe_atr_hash_dword common);
s32 txgbe_get_link_capabilities(struct txgbe_hw *hw,
u32 *speed, bool *autoneg);
enum txgbe_media_type txgbe_get_media_type(struct txgbe_hw *hw);
void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw);
void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw);
void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw);
void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
u32 speed);
s32 txgbe_setup_mac_link(struct txgbe_hw *hw, u32 speed,
bool autoneg_wait_to_complete);
void txgbe_init_mac_link_ops(struct txgbe_hw *hw);
s32 txgbe_reset_hw(struct txgbe_hw *hw);
s32 txgbe_identify_phy(struct txgbe_hw *hw);
s32 txgbe_init_phy_ops(struct txgbe_hw *hw);
s32 txgbe_enable_rx_dma(struct txgbe_hw *hw, u32 regval);
s32 txgbe_init_ops(struct txgbe_hw *hw);
s32 txgbe_setup_eee(struct txgbe_hw *hw, bool enable_eee);
s32 txgbe_init_flash_params(struct txgbe_hw *hw);
s32 txgbe_read_flash_buffer(struct txgbe_hw *hw, u32 offset,
u32 dwords, u32 *data);
s32 txgbe_write_flash_buffer(struct txgbe_hw *hw, u32 offset,
u32 dwords, u32 *data);
s32 txgbe_read_eeprom(struct txgbe_hw *hw,
u16 offset, u16 *data);
s32 txgbe_read_eeprom_buffer(struct txgbe_hw *hw, u16 offset,
u16 words, u16 *data);
s32 txgbe_init_eeprom_params(struct txgbe_hw *hw);
s32 txgbe_update_eeprom_checksum(struct txgbe_hw *hw);
s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw);
s32 txgbe_validate_eeprom_checksum(struct txgbe_hw *hw,
u16 *checksum_val);
s32 txgbe_update_flash(struct txgbe_hw *hw);
s32 txgbe_write_ee_hostif_buffer(struct txgbe_hw *hw,
u16 offset, u16 words, u16 *data);
s32 txgbe_write_ee_hostif(struct txgbe_hw *hw, u16 offset,
u16 data);
s32 txgbe_read_ee_hostif_buffer(struct txgbe_hw *hw,
u16 offset, u16 words, u16 *data);
s32 txgbe_read_ee_hostif(struct txgbe_hw *hw, u16 offset, u16 *data);
u32 txgbe_rd32_epcs(struct txgbe_hw *hw, u32 addr);
void txgbe_wr32_epcs(struct txgbe_hw *hw, u32 addr, u32 data);
void txgbe_wr32_ephy(struct txgbe_hw *hw, u32 addr, u32 data);
u32 rd32_ephy(struct txgbe_hw *hw, u32 addr);
s32 txgbe_upgrade_flash_hostif(struct txgbe_hw *hw, u32 region,
const u8 *data, u32 size);
s32 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg);
s32 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg);
s32 txgbe_set_link_to_kx(struct txgbe_hw *hw,
u32 speed,
bool autoneg);
#endif /* _TXGBE_HW_H_ */
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/*
* WangXun 10 Gigabit PCI Express Linux driver
* Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* based on ixgbe_mbx.c, Copyright(c) 1999 - 2017 Intel Corporation.
* Contact Information:
* Linux NICS <linux.nics@intel.com>
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*/
#include "txgbe.h"
#include "txgbe_mbx.h"
/**
* txgbe_read_mbx - Reads a message from the mailbox
* @hw: pointer to the HW structure
* @msg: The message buffer
* @size: Length of buffer
* @mbx_id: id of mailbox to read
*
* returns SUCCESS if it successfuly read message from buffer
**/
int txgbe_read_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
{
struct txgbe_mbx_info *mbx = &hw->mbx;
int err = TXGBE_ERR_MBX;
/* limit read to size of mailbox */
if (size > mbx->size)
size = mbx->size;
err = TCALL(hw, mbx.ops.read, msg, size, mbx_id);
return err;
}
/**
* txgbe_write_mbx - Write a message to the mailbox
* @hw: pointer to the HW structure
* @msg: The message buffer
* @size: Length of buffer
* @mbx_id: id of mailbox to write
*
* returns SUCCESS if it successfully copied message into the buffer
**/
int txgbe_write_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
{
struct txgbe_mbx_info *mbx = &hw->mbx;
int err = 0;
if (size > mbx->size) {
err = TXGBE_ERR_MBX;
ERROR_REPORT2(TXGBE_ERROR_ARGUMENT,
"Invalid mailbox message size %d", size);
} else
err = TCALL(hw, mbx.ops.write, msg, size, mbx_id);
return err;
}
/**
* txgbe_check_for_msg - checks to see if someone sent us mail
* @hw: pointer to the HW structure
* @mbx_id: id of mailbox to check
*
* returns SUCCESS if the Status bit was found or else ERR_MBX
**/
int txgbe_check_for_msg(struct txgbe_hw *hw, u16 mbx_id)
{
int err = TXGBE_ERR_MBX;
err = TCALL(hw, mbx.ops.check_for_msg, mbx_id);
return err;
}
/**
* txgbe_check_for_ack - checks to see if someone sent us ACK
* @hw: pointer to the HW structure
* @mbx_id: id of mailbox to check
*
* returns SUCCESS if the Status bit was found or else ERR_MBX
**/
int txgbe_check_for_ack(struct txgbe_hw *hw, u16 mbx_id)
{
int err = TXGBE_ERR_MBX;
err = TCALL(hw, mbx.ops.check_for_ack, mbx_id);
return err;
}
/**
* txgbe_check_for_rst - checks to see if other side has reset
* @hw: pointer to the HW structure
* @mbx_id: id of mailbox to check
*
* returns SUCCESS if the Status bit was found or else ERR_MBX
**/
int txgbe_check_for_rst(struct txgbe_hw *hw, u16 mbx_id)
{
struct txgbe_mbx_info *mbx = &hw->mbx;
int err = TXGBE_ERR_MBX;
if (mbx->ops.check_for_rst)
err = mbx->ops.check_for_rst(hw, mbx_id);
return err;
}
/**
* txgbe_poll_for_msg - Wait for message notification
* @hw: pointer to the HW structure
* @mbx_id: id of mailbox to write
*
* returns SUCCESS if it successfully received a message notification
**/
int txgbe_poll_for_msg(struct txgbe_hw *hw, u16 mbx_id)
{
struct txgbe_mbx_info *mbx = &hw->mbx;
int countdown = mbx->timeout;
if (!countdown || !mbx->ops.check_for_msg)
goto out;
while (countdown && TCALL(hw, mbx.ops.check_for_msg, mbx_id)) {
countdown--;
if (!countdown)
break;
udelay(mbx->udelay);
}
if (countdown == 0)
ERROR_REPORT2(TXGBE_ERROR_POLLING,
"Polling for VF%d mailbox message timedout", mbx_id);
out:
return countdown ? 0 : TXGBE_ERR_MBX;
}
/**
* txgbe_poll_for_ack - Wait for message acknowledgement
* @hw: pointer to the HW structure
* @mbx_id: id of mailbox to write
*
* returns SUCCESS if it successfully received a message acknowledgement
**/
int txgbe_poll_for_ack(struct txgbe_hw *hw, u16 mbx_id)
{
struct txgbe_mbx_info *mbx = &hw->mbx;
int countdown = mbx->timeout;
if (!countdown || !mbx->ops.check_for_ack)
goto out;
while (countdown && TCALL(hw, mbx.ops.check_for_ack, mbx_id)) {
countdown--;
if (!countdown)
break;
udelay(mbx->udelay);
}
if (countdown == 0)
ERROR_REPORT2(TXGBE_ERROR_POLLING,
"Polling for VF%d mailbox ack timedout", mbx_id);
out:
return countdown ? 0 : TXGBE_ERR_MBX;
}
int txgbe_check_for_bit_pf(struct txgbe_hw *hw, u32 mask, int index)
{
u32 mbvficr = rd32(hw, TXGBE_MBVFICR(index));
int err = TXGBE_ERR_MBX;
if (mbvficr & mask) {
err = 0;
wr32(hw, TXGBE_MBVFICR(index), mask);
}
return err;
}
/**
* txgbe_check_for_msg_pf - checks to see if the VF has sent mail
* @hw: pointer to the HW structure
* @vf: the VF index
*
* returns SUCCESS if the VF has set the Status bit or else ERR_MBX
**/
int txgbe_check_for_msg_pf(struct txgbe_hw *hw, u16 vf)
{
int err = TXGBE_ERR_MBX;
int index = TXGBE_MBVFICR_INDEX(vf);
u32 vf_bit = vf % 16;
if (!txgbe_check_for_bit_pf(hw, TXGBE_MBVFICR_VFREQ_VF1 << vf_bit,
index)) {
err = 0;
hw->mbx.stats.reqs++;
}
return err;
}
/**
* txgbe_check_for_ack_pf - checks to see if the VF has ACKed
* @hw: pointer to the HW structure
* @vf: the VF index
*
* returns SUCCESS if the VF has set the Status bit or else ERR_MBX
**/
int txgbe_check_for_ack_pf(struct txgbe_hw *hw, u16 vf)
{
int err = TXGBE_ERR_MBX;
int index = TXGBE_MBVFICR_INDEX(vf);
u32 vf_bit = vf % 16;
if (!txgbe_check_for_bit_pf(hw, TXGBE_MBVFICR_VFACK_VF1 << vf_bit,
index)) {
err = 0;
hw->mbx.stats.acks++;
}
return err;
}
/**
* txgbe_check_for_rst_pf - checks to see if the VF has reset
* @hw: pointer to the HW structure
* @vf: the VF index
*
* returns SUCCESS if the VF has set the Status bit or else ERR_MBX
**/
int txgbe_check_for_rst_pf(struct txgbe_hw *hw, u16 vf)
{
u32 reg_offset = (vf < 32) ? 0 : 1;
u32 vf_shift = vf % 32;
u32 vflre = 0;
int err = TXGBE_ERR_MBX;
vflre = rd32(hw, TXGBE_VFLRE(reg_offset));
if (vflre & (1 << vf_shift)) {
err = 0;
wr32(hw, TXGBE_VFLREC(reg_offset), (1 << vf_shift));
hw->mbx.stats.rsts++;
}
return err;
}
/**
* txgbe_obtain_mbx_lock_pf - obtain mailbox lock
* @hw: pointer to the HW structure
* @vf: the VF index
*
* return SUCCESS if we obtained the mailbox lock
**/
int txgbe_obtain_mbx_lock_pf(struct txgbe_hw *hw, u16 vf)
{
int err = TXGBE_ERR_MBX;
u32 mailbox;
/* Take ownership of the buffer */
wr32(hw, TXGBE_PXMAILBOX(vf), TXGBE_PXMAILBOX_PFU);
/* reserve mailbox for vf use */
mailbox = rd32(hw, TXGBE_PXMAILBOX(vf));
if (mailbox & TXGBE_PXMAILBOX_PFU)
err = 0;
else
ERROR_REPORT2(TXGBE_ERROR_POLLING,
"Failed to obtain mailbox lock for PF%d", vf);
return err;
}
/**
* txgbe_write_mbx_pf - Places a message in the mailbox
* @hw: pointer to the HW structure
* @msg: The message buffer
* @size: Length of buffer
* @vf: the VF index
*
* returns SUCCESS if it successfully copied message into the buffer
**/
int txgbe_write_mbx_pf(struct txgbe_hw *hw, u32 *msg, u16 size,
u16 vf)
{
int err;
u16 i;
/* lock the mailbox to prevent pf/vf race condition */
err = txgbe_obtain_mbx_lock_pf(hw, vf);
if (err)
goto out_no_write;
/* flush msg and acks as we are overwriting the message buffer */
txgbe_check_for_msg_pf(hw, vf);
txgbe_check_for_ack_pf(hw, vf);
/* copy the caller specified message to the mailbox memory buffer */
for (i = 0; i < size; i++)
wr32a(hw, TXGBE_PXMBMEM(vf), i, msg[i]);
/* Interrupt VF to tell it a message has been sent and release buffer*/
/* set mirrored mailbox flags */
wr32a(hw, TXGBE_PXMBMEM(vf), TXGBE_VXMAILBOX_SIZE, TXGBE_PXMAILBOX_STS);
wr32(hw, TXGBE_PXMAILBOX(vf), TXGBE_PXMAILBOX_STS);
/* update stats */
hw->mbx.stats.msgs_tx++;
out_no_write:
return err;
}
/**
* txgbe_read_mbx_pf - Read a message from the mailbox
* @hw: pointer to the HW structure
* @msg: The message buffer
* @size: Length of buffer
* @vf: the VF index
*
* This function copies a message from the mailbox buffer to the caller's
* memory buffer. The presumption is that the caller knows that there was
* a message due to a VF request so no polling for message is needed.
**/
int txgbe_read_mbx_pf(struct txgbe_hw *hw, u32 *msg, u16 size,
u16 vf)
{
int err;
u16 i;
/* lock the mailbox to prevent pf/vf race condition */
err = txgbe_obtain_mbx_lock_pf(hw, vf);
if (err)
goto out_no_read;
/* copy the message to the mailbox memory buffer */
for (i = 0; i < size; i++)
msg[i] = rd32a(hw, TXGBE_PXMBMEM(vf), i);
/* Acknowledge the message and release buffer */
/* set mirrored mailbox flags */
wr32a(hw, TXGBE_PXMBMEM(vf), TXGBE_VXMAILBOX_SIZE, TXGBE_PXMAILBOX_ACK);
wr32(hw, TXGBE_PXMAILBOX(vf), TXGBE_PXMAILBOX_ACK);
/* update stats */
hw->mbx.stats.msgs_rx++;
out_no_read:
return err;
}
/**
* txgbe_init_mbx_params_pf - set initial values for pf mailbox
* @hw: pointer to the HW structure
*
* Initializes the hw->mbx struct to correct values for pf mailbox
*/
void txgbe_init_mbx_params_pf(struct txgbe_hw *hw)
{
struct txgbe_mbx_info *mbx = &hw->mbx;
mbx->timeout = 0;
mbx->udelay = 0;
mbx->size = TXGBE_VXMAILBOX_SIZE;
mbx->ops.read = txgbe_read_mbx_pf;
mbx->ops.write = txgbe_write_mbx_pf;
mbx->ops.check_for_msg = txgbe_check_for_msg_pf;
mbx->ops.check_for_ack = txgbe_check_for_ack_pf;
mbx->ops.check_for_rst = txgbe_check_for_rst_pf;
mbx->stats.msgs_tx = 0;
mbx->stats.msgs_rx = 0;
mbx->stats.reqs = 0;
mbx->stats.acks = 0;
mbx->stats.rsts = 0;
}
/*
* WangXun 10 Gigabit PCI Express Linux driver
* Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* based on ixgbe_mbx.h, Copyright(c) 1999 - 2017 Intel Corporation.
* Contact Information:
* Linux NICS <linux.nics@intel.com>
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*/
#ifndef _TXGBE_MBX_H_
#define _TXGBE_MBX_H_
#define TXGBE_VXMAILBOX_SIZE (16 - 1)
/**
* VF Registers
**/
#define TXGBE_VXMAILBOX 0x00600
#define TXGBE_VXMAILBOX_REQ ((0x1) << 0) /* Request for PF Ready bit */
#define TXGBE_VXMAILBOX_ACK ((0x1) << 1) /* Ack PF message received */
#define TXGBE_VXMAILBOX_VFU ((0x1) << 2) /* VF owns the mailbox buffer */
#define TXGBE_VXMAILBOX_PFU ((0x1) << 3) /* PF owns the mailbox buffer */
#define TXGBE_VXMAILBOX_PFSTS ((0x1) << 4) /* PF wrote a message in the MB */
#define TXGBE_VXMAILBOX_PFACK ((0x1) << 5) /* PF ack the previous VF msg */
#define TXGBE_VXMAILBOX_RSTI ((0x1) << 6) /* PF has reset indication */
#define TXGBE_VXMAILBOX_RSTD ((0x1) << 7) /* PF has indicated reset done */
#define TXGBE_VXMAILBOX_R2C_BITS (TXGBE_VXMAILBOX_RSTD | \
TXGBE_VXMAILBOX_PFSTS | TXGBE_VXMAILBOX_PFACK)
#define TXGBE_VXMBMEM 0x00C00 /* 16*4B */
/**
* PF Registers
**/
#define TXGBE_PXMAILBOX(i) (0x00600 + (4 * (i))) /* i=[0,63] */
#define TXGBE_PXMAILBOX_STS ((0x1) << 0) /* Initiate message send to VF */
#define TXGBE_PXMAILBOX_ACK ((0x1) << 1) /* Ack message recv'd from VF */
#define TXGBE_PXMAILBOX_VFU ((0x1) << 2) /* VF owns the mailbox buffer */
#define TXGBE_PXMAILBOX_PFU ((0x1) << 3) /* PF owns the mailbox buffer */
#define TXGBE_PXMAILBOX_RVFU ((0x1) << 4) /* Reset VFU - used when VF stuck*/
#define TXGBE_PXMBMEM(i) (0x5000 + (64 * (i))) /* i=[0,63] */
#define TXGBE_VFLRP(i) (0x00490 + (4 * (i))) /* i=[0,1] */
#define TXGBE_VFLRE(i) (0x004A0 + (4 * (i))) /* i=[0,1] */
#define TXGBE_VFLREC(i) (0x004A8 + (4 * (i))) /* i=[0,1] */
/* SR-IOV specific macros */
#define TXGBE_MBVFICR(i) (0x00480 + (4 * (i))) /* i=[0,3] */
#define TXGBE_MBVFICR_INDEX(vf) ((vf) >> 4)
#define TXGBE_MBVFICR_VFREQ_MASK (0x0000FFFF) /* bits for VF messages */
#define TXGBE_MBVFICR_VFREQ_VF1 (0x00000001) /* bit for VF 1 message */
#define TXGBE_MBVFICR_VFACK_MASK (0xFFFF0000) /* bits for VF acks */
#define TXGBE_MBVFICR_VFACK_VF1 (0x00010000) /* bit for VF 1 ack */
/**
* Messages
**/
/* If it's a TXGBE_VF_* msg then it originates in the VF and is sent to the
* PF. The reverse is true if it is TXGBE_PF_*.
* Message ACK's are the value or'd with 0xF0000000
*/
#define TXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with
* this are the ACK */
#define TXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with
* this are the NACK */
#define TXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still
* clear to send requests */
#define TXGBE_VT_MSGINFO_SHIFT 16
/* bits 23:16 are used for extra info for certain messages */
#define TXGBE_VT_MSGINFO_MASK (0xFF << TXGBE_VT_MSGINFO_SHIFT)
/* definitions to support mailbox API version negotiation */
/*
* each element denotes a version of the API; existing numbers may not
* change; any additions must go at the end
*/
enum txgbe_pfvf_api_rev {
txgbe_mbox_api_null,
txgbe_mbox_api_10, /* API version 1.0, linux/freebsd VF driver */
txgbe_mbox_api_11, /* API version 1.1, linux/freebsd VF driver */
txgbe_mbox_api_12, /* API version 1.2, linux/freebsd VF driver */
txgbe_mbox_api_13, /* API version 1.3, linux/freebsd VF driver */
txgbe_mbox_api_20, /* API version 2.0, solaris Phase1 VF driver */
txgbe_mbox_api_unknown, /* indicates that API version is not known */
};
/* mailbox API, legacy requests */
#define TXGBE_VF_RESET 0x01 /* VF requests reset */
#define TXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
#define TXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
#define TXGBE_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */
/* mailbox API, version 1.0 VF requests */
#define TXGBE_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */
#define TXGBE_VF_SET_MACVLAN 0x06 /* VF requests PF for unicast filter */
#define TXGBE_VF_API_NEGOTIATE 0x08 /* negotiate API version */
/* mailbox API, version 1.1 VF requests */
#define TXGBE_VF_GET_QUEUES 0x09 /* get queue configuration */
/* mailbox API, version 1.2 VF requests */
#define TXGBE_VF_GET_RETA 0x0a /* VF request for RETA */
#define TXGBE_VF_GET_RSS_KEY 0x0b /* get RSS key */
#define TXGBE_VF_UPDATE_XCAST_MODE 0x0c
#define TXGBE_VF_BACKUP 0x8001 /* VF requests backup */
/* mode choices for IXGBE_VF_UPDATE_XCAST_MODE */
enum txgbevf_xcast_modes {
TXGBEVF_XCAST_MODE_NONE = 0,
TXGBEVF_XCAST_MODE_MULTI,
TXGBEVF_XCAST_MODE_ALLMULTI,
TXGBEVF_XCAST_MODE_PROMISC,
};
/* GET_QUEUES return data indices within the mailbox */
#define TXGBE_VF_TX_QUEUES 1 /* number of Tx queues supported */
#define TXGBE_VF_RX_QUEUES 2 /* number of Rx queues supported */
#define TXGBE_VF_TRANS_VLAN 3 /* Indication of port vlan */
#define TXGBE_VF_DEF_QUEUE 4 /* Default queue offset */
/* length of permanent address message returned from PF */
#define TXGBE_VF_PERMADDR_MSG_LEN 4
/* word in permanent address message with the current multicast type */
#define TXGBE_VF_MC_TYPE_WORD 3
#define TXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */
/* mailbox API, version 2.0 VF requests */
#define TXGBE_VF_API_NEGOTIATE 0x08 /* negotiate API version */
#define TXGBE_VF_GET_QUEUES 0x09 /* get queue configuration */
#define TXGBE_VF_ENABLE_MACADDR 0x0A /* enable MAC address */
#define TXGBE_VF_DISABLE_MACADDR 0x0B /* disable MAC address */
#define TXGBE_VF_GET_MACADDRS 0x0C /* get all configured MAC addrs */
#define TXGBE_VF_SET_MCAST_PROMISC 0x0D /* enable multicast promiscuous */
#define TXGBE_VF_GET_MTU 0x0E /* get bounds on MTU */
#define TXGBE_VF_SET_MTU 0x0F /* set a specific MTU */
/* mailbox API, version 2.0 PF requests */
#define TXGBE_PF_TRANSPARENT_VLAN 0x0101 /* enable transparent vlan */
#define TXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
#define TXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
int txgbe_read_mbx(struct txgbe_hw *, u32 *, u16, u16);
int txgbe_write_mbx(struct txgbe_hw *, u32 *, u16, u16);
int txgbe_read_posted_mbx(struct txgbe_hw *, u32 *, u16, u16);
int txgbe_write_posted_mbx(struct txgbe_hw *, u32 *, u16, u16);
int txgbe_check_for_msg(struct txgbe_hw *, u16);
int txgbe_check_for_ack(struct txgbe_hw *, u16);
int txgbe_check_for_rst(struct txgbe_hw *, u16);
void txgbe_init_mbx_ops(struct txgbe_hw *hw);
void txgbe_init_mbx_params_vf(struct txgbe_hw *);
void txgbe_init_mbx_params_pf(struct txgbe_hw *);
#endif /* _TXGBE_MBX_H_ */
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/*
* WangXun 10 Gigabit PCI Express Linux driver
* Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* based on ixgbe_phy.h, Copyright(c) 1999 - 2017 Intel Corporation.
* Contact Information:
* Linux NICS <linux.nics@intel.com>
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*/
#ifndef _TXGBE_PHY_H_
#define _TXGBE_PHY_H_
#include "txgbe.h"
#define TXGBE_I2C_EEPROM_DEV_ADDR 0xA0
#define TXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
#define TXGBE_I2C_EEPROM_BANK_LEN 0xFF
/* EEPROM byte offsets */
#define TXGBE_SFF_IDENTIFIER 0x0
#define TXGBE_SFF_IDENTIFIER_SFP 0x3
#define TXGBE_SFF_VENDOR_OUI_BYTE0 0x25
#define TXGBE_SFF_VENDOR_OUI_BYTE1 0x26
#define TXGBE_SFF_VENDOR_OUI_BYTE2 0x27
#define TXGBE_SFF_1GBE_COMP_CODES 0x6
#define TXGBE_SFF_10GBE_COMP_CODES 0x3
#define TXGBE_SFF_CABLE_TECHNOLOGY 0x8
#define TXGBE_SFF_CABLE_SPEC_COMP 0x3C
#define TXGBE_SFF_SFF_8472_SWAP 0x5C
#define TXGBE_SFF_SFF_8472_COMP 0x5E
#define TXGBE_SFF_SFF_8472_OSCB 0x6E
#define TXGBE_SFF_SFF_8472_ESCB 0x76
#define TXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD
#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
#define TXGBE_SFF_QSFP_CONNECTOR 0x82
#define TXGBE_SFF_QSFP_10GBE_COMP 0x83
#define TXGBE_SFF_QSFP_1GBE_COMP 0x86
#define TXGBE_SFF_QSFP_CABLE_LENGTH 0x92
#define TXGBE_SFF_QSFP_DEVICE_TECH 0x93
/* Bitmasks */
#define TXGBE_SFF_DA_PASSIVE_CABLE 0x4
#define TXGBE_SFF_DA_ACTIVE_CABLE 0x8
#define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
#define TXGBE_SFF_1GBASESX_CAPABLE 0x1
#define TXGBE_SFF_1GBASELX_CAPABLE 0x2
#define TXGBE_SFF_1GBASET_CAPABLE 0x8
#define TXGBE_SFF_10GBASESR_CAPABLE 0x10
#define TXGBE_SFF_10GBASELR_CAPABLE 0x20
#define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
#define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8
#define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0
#define TXGBE_SFF_ADDRESSING_MODE 0x4
#define TXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
#define TXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
#define TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
#define TXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
#define TXGBE_I2C_EEPROM_READ_MASK 0x100
#define TXGBE_I2C_EEPROM_STATUS_MASK 0x3
#define TXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
#define TXGBE_I2C_EEPROM_STATUS_PASS 0x1
#define TXGBE_I2C_EEPROM_STATUS_FAIL 0x2
#define TXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
#define TXGBE_CS4227 0xBE /* CS4227 address */
#define TXGBE_CS4227_GLOBAL_ID_LSB 0
#define TXGBE_CS4227_SCRATCH 2
#define TXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5
#define TXGBE_CS4227_SCRATCH_VALUE 0x5aa5
#define TXGBE_CS4227_RETRIES 5
#define TXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to program speed */
#define TXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to program EDC */
#define TXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to program speed */
#define TXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */
#define TXGBE_CS4227_EDC_MODE_CX1 0x0002
#define TXGBE_CS4227_EDC_MODE_SR 0x0004
#define TXGBE_CS4227_RESET_HOLD 500 /* microseconds */
#define TXGBE_CS4227_RESET_DELAY 500 /* milliseconds */
#define TXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */
#define TXGBE_PE 0xE0 /* Port expander address */
#define TXGBE_PE_OUTPUT 1 /* Output register offset */
#define TXGBE_PE_CONFIG 3 /* Config register offset */
#define TXGBE_PE_BIT1 (1 << 1)
/* Flow control defines */
#define TXGBE_TAF_SYM_PAUSE (0x1)
#define TXGBE_TAF_ASM_PAUSE (0x2)
/* Bit-shift macros */
#define TXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
#define TXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
#define TXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
#define TXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
#define TXGBE_SFF_VENDOR_OUI_FTL 0x00906500
#define TXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
#define TXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
/* I2C SDA and SCL timing parameters for standard mode */
#define TXGBE_I2C_T_HD_STA 4
#define TXGBE_I2C_T_LOW 5
#define TXGBE_I2C_T_HIGH 4
#define TXGBE_I2C_T_SU_STA 5
#define TXGBE_I2C_T_HD_DATA 5
#define TXGBE_I2C_T_SU_DATA 1
#define TXGBE_I2C_T_RISE 1
#define TXGBE_I2C_T_FALL 1
#define TXGBE_I2C_T_SU_STO 4
#define TXGBE_I2C_T_BUF 5
/* SFP+ SFF-8472 Compliance */
#define TXGBE_SFF_SFF_8472_UNSUP 0x00
enum txgbe_phy_type txgbe_get_phy_type_from_id(struct txgbe_hw *hw);
s32 txgbe_get_phy_id(struct txgbe_hw *hw);
s32 txgbe_reset_phy(struct txgbe_hw *hw);
s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data);
s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data);
s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data);
s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data);
u32 txgbe_setup_phy_link(struct txgbe_hw *hw, u32 speed_set, bool autoneg_wait_to_complete);
u32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
u32 speed,
bool autoneg_wait_to_complete);
s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
u32 *speed,
bool *autoneg);
s32 txgbe_check_reset_blocked(struct txgbe_hw *hw);
s32 txgbe_identify_module(struct txgbe_hw *hw);
s32 txgbe_identify_sfp_module(struct txgbe_hw *hw);
s32 txgbe_tn_check_overtemp(struct txgbe_hw *hw);
s32 txgbe_init_i2c(struct txgbe_hw *hw);
s32 txgbe_clear_i2c(struct txgbe_hw *hw);
s32 txgbe_switch_i2c_slave_addr(struct txgbe_hw *hw, u8 dev_addr);
s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data);
s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data);
s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data);
s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
u8 eeprom_data);
s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
u8 *sff8472_data);
s32 txgbe_init_external_phy(struct txgbe_hw *hw);
s32 txgbe_set_phy_pause_advertisement(struct txgbe_hw *hw, u32 pause_bit);
s32 txgbe_get_phy_advertised_pause(struct txgbe_hw *hw, u8 *pause_bit);
s32 txgbe_get_lp_advertised_pause(struct txgbe_hw *hw, u8 *pause_bit);
MTD_STATUS txgbe_read_mdio(
MTD_DEV * dev,
MTD_U16 port,
MTD_U16 mmd,
MTD_U16 reg,
MTD_U16 *value);
MTD_STATUS txgbe_write_mdio(
MTD_DEV * dev,
MTD_U16 port,
MTD_U16 mmd,
MTD_U16 reg,
MTD_U16 value);
#endif /* _TXGBE_PHY_H_ */
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