x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors
L3 cache size, associativity and shared_cpu information need to be adapted to show information for an internal node instead of the entire physical package. Signed-off-by: NAndreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
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