perf vendor events: Update Silvermont

Events are still at version 14:
    https://download.01.org/perfmon/SLM
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

The addition of a floating-point.json is due to events having
their topic better identified by the converter script.

Tested:

Not tested on a Silvermont, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
Reviewed-by: NKan Liang <kan.liang@linux.intel.com>
Signed-off-by: NIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-23-irogers@google.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>

tools/perf/pmu-events/arch/x86/silvermont/floating-point.json

+[
+    {
+        "BriefDescription": "Stalls due to FP assists",
+        "Counter": "0,1",
+        "EventCode": "0xC3",
+        "EventName": "MACHINE_CLEARS.FP_ASSIST",
+        "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x4"
+    }
+]
\ No newline at end of file

tools/perf/pmu-events/arch/x86/silvermont/frontend.json

 [
     {
-        "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.",
-        "EventCode": "0x80",
+        "BriefDescription": "Counts the number of baclears",
         "Counter": "0,1",
-        "UMask": "0x3",
-        "EventName": "ICACHE.ACCESSES",
+        "EventCode": "0xE6",
+        "EventName": "BACLEARS.ALL",
+        "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branch.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Instruction fetches"
+        "UMask": "0x1"
     },
     {
-        "PublicDescription": "This event counts all instruction fetches from the instruction cache.",
-        "EventCode": "0x80",
+        "BriefDescription": "Counts the number of JCC baclears",
         "Counter": "0,1",
-        "UMask": "0x1",
-        "EventName": "ICACHE.HIT",
+        "EventCode": "0xE6",
+        "EventName": "BACLEARS.COND",
+        "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Instruction fetches from Icache"
+        "UMask": "0x10"
     },
     {
-        "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
+        "BriefDescription": "Counts the number of RETURN baclears",
+        "Counter": "0,1",
+        "EventCode": "0xE6",
+        "EventName": "BACLEARS.RETURN",
+        "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclears.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction",
+        "Counter": "0,1",
+        "EventCode": "0xE9",
+        "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
+        "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Instruction fetches",
+        "Counter": "0,1",
         "EventCode": "0x80",
+        "EventName": "ICACHE.ACCESSES",
+        "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "Instruction fetches from Icache",
         "Counter": "0,1",
-        "UMask": "0x2",
-        "EventName": "ICACHE.MISSES",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.HIT",
+        "PublicDescription": "This event counts all instruction fetches from the instruction cache.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Icache miss"
+        "UMask": "0x1"
     },
     {
-        "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",
-        "EventCode": "0xE7",
+        "BriefDescription": "Icache miss",
         "Counter": "0,1",
-        "UMask": "0x1",
-        "EventName": "MS_DECODED.MS_ENTRY",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.MISSES",
+        "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count."
+        "UMask": "0x2"
     },
     {
-        "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.",
-        "EventCode": "0xE9",
+        "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count.",
         "Counter": "0,1",
-        "UMask": "0x1",
-        "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
+        "EventCode": "0xE7",
+        "EventName": "MS_DECODED.MS_ENTRY",
+        "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction"
+        "UMask": "0x1"
     }
 ]
\ No newline at end of file

tools/perf/pmu-events/arch/x86/silvermont/memory.json

 [
     {
-        "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.",
-        "EventCode": "0xC3",
+        "BriefDescription": "Stalls due to Memory ordering",
         "Counter": "0,1",
-        "UMask": "0x2",
+        "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
+        "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Stalls due to Memory ordering"
+        "UMask": "0x2"
     }
 ]
\ No newline at end of file

tools/perf/pmu-events/arch/x86/silvermont/other.json

 [
     {
-        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
-        "EventCode": "0x86",
+        "BriefDescription": "Cycles code-fetch stalled due to any reason.",
         "Counter": "0,1",
-        "UMask": "0x2",
-        "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
+        "EventCode": "0x86",
+        "EventName": "FETCH_STALL.ALL",
+        "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss."
+        "UMask": "0x3f"
     },
     {
-        "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
-        "EventCode": "0x86",
+        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
         "Counter": "0,1",
-        "UMask": "0x3f",
-        "EventName": "FETCH_STALL.ALL",
+        "EventCode": "0x86",
+        "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
+        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Cycles code-fetch stalled due to any reason."
+        "UMask": "0x2"
     }
 ]
\ No newline at end of file

tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json

 [
     {
-        "PEBS": "1",
-        "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.",
-        "EventCode": "0x04",
+        "BriefDescription": "Loads missed DTLB",
         "Counter": "0,1",
-        "UMask": "0x8",
+        "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
+        "PEBS": "1",
+        "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Loads missed DTLB"
+        "UMask": "0x8"
     },
     {
-        "PublicDescription": "This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
-        "EventCode": "0x05",
+        "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
         "Counter": "0,1",
-        "UMask": "0x1",
-        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
-        "SampleAfterValue": "100003",
-        "BriefDescription": "D-side page-walks",
-        "EdgeDetect": "1"
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.CYCLES",
+        "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x3"
     },
     {
-        "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
-        "EventCode": "0x05",
+        "BriefDescription": "Duration of D-side page-walks in core cycles",
         "Counter": "0,1",
-        "UMask": "0x1",
+        "EventCode": "0x05",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
+        "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Duration of D-side page-walks in core cycles"
+        "UMask": "0x1"
     },
     {
-        "PublicDescription": "This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
-        "EventCode": "0x05",
+        "BriefDescription": "D-side page-walks",
         "Counter": "0,1",
-        "UMask": "0x2",
-        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
+        "EdgeDetect": "1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
+        "PublicDescription": "This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
         "SampleAfterValue": "100003",
-        "BriefDescription": "I-side page-walks",
-        "EdgeDetect": "1"
+        "UMask": "0x1"
     },
     {
-        "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
-        "EventCode": "0x05",
+        "BriefDescription": "Duration of I-side page-walks in core cycles",
         "Counter": "0,1",
-        "UMask": "0x2",
+        "EventCode": "0x05",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
+        "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Duration of I-side page-walks in core cycles"
+        "UMask": "0x2"
     },
     {
-        "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
-        "EventCode": "0x05",
+        "BriefDescription": "I-side page-walks",
         "Counter": "0,1",
-        "UMask": "0x3",
-        "EventName": "PAGE_WALKS.WALKS",
+        "EdgeDetect": "1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
+        "PublicDescription": "This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
         "SampleAfterValue": "100003",
-        "BriefDescription": "Total page walks that are completed (I-side and D-side)",
-        "EdgeDetect": "1"
+        "UMask": "0x2"
     },
     {
-        "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
-        "EventCode": "0x05",
+        "BriefDescription": "Total page walks that are completed (I-side and D-side)",
         "Counter": "0,1",
-        "UMask": "0x3",
-        "EventName": "PAGE_WALKS.CYCLES",
-        "SampleAfterValue": "200003",
-        "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)"
+        "EdgeDetect": "1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.WALKS",
+        "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x3"
     }
 ]
\ No newline at end of file