Revert "net: hns3: add tm flush when setting tm"

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I7ON9Y
CVE: NA

----------------------------------------------------------------------

This reverts commit b62afba4.
Signed-off-by: NJiantao Xiao <xiaojiantao1@h-partners.com>

drivers/net/ethernet/hisilicon/hns3/hnae3.h

@@ -105,7 +105,6 @@ enum HNAE3_DEV_CAP_BITS {
 	HNAE3_DEV_SUPPORT_WOL_B,
 	HNAE3_DEV_SUPPORT_VF_FAULT_B,
 	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,
-	HNAE3_DEV_SUPPORT_TM_FLUSH_B,
 };
 
 #define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -180,9 +179,6 @@ enum HNAE3_DEV_CAP_BITS {
 #define hnae3_ae_dev_notify_pkt_supported(ae_dev) \
 	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)
 
-#define hnae3_ae_dev_tm_flush_supported(hdev) \
-	test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)
-
 enum HNAE3_PF_CAP_BITS {
 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
 };

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

@@ -157,7 +157,6 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
 	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
 	{HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B},
 	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},
-	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},
 };
 
 static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

@@ -153,7 +153,6 @@ enum hclge_opcode_type {
 	HCLGE_OPC_TM_INTERNAL_STS	= 0x0850,
 	HCLGE_OPC_TM_INTERNAL_CNT	= 0x0851,
 	HCLGE_OPC_TM_INTERNAL_STS_1	= 0x0852,
-	HCLGE_OPC_TM_FLUSH		= 0x0872,
 
 	/* Packet buffer allocate commands */
 	HCLGE_OPC_TX_BUFF_ALLOC		= 0x0901,
@@ -351,7 +350,6 @@ enum HCLGE_COMM_CAP_BITS {
 	HCLGE_COMM_CAP_LANE_NUM_B = 27,
 	HCLGE_COMM_CAP_WOL_B = 28,
 	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,
-	HCLGE_COMM_CAP_TM_FLUSH_B = 31,
 };
 
 enum HCLGE_COMM_API_CAP_BITS {

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

@@ -415,9 +415,6 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
 	}, {
 		.name = "support vf fault detect",
 		.cap_bit = HNAE3_DEV_SUPPORT_VF_FAULT_B,
-	}, {
-		.name = "support tm flush",
-		.cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B,
 	}
 };
 

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

@@ -227,10 +227,6 @@ static int hclge_notify_down_uinit(struct hclge_dev *hdev)
 	if (ret)
 		return ret;
 
-	ret = hclge_tm_flush_cfg(hdev, true);
-	if (ret)
-		return ret;
-
 	return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
 }
 
@@ -242,10 +238,6 @@ static int hclge_notify_init_up(struct hclge_dev *hdev)
 	if (ret)
 		return ret;
 
-	ret = hclge_tm_flush_cfg(hdev, false);
-	if (ret)
-		return ret;
-
 	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 }
 
@@ -332,7 +324,6 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 	struct net_device *netdev = h->kinfo.netdev;
 	struct hclge_dev *hdev = vport->back;
 	u8 i, j, pfc_map, *prio_tc;
-	int last_bad_ret = 0;
 	int ret;
 
 	if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))
@@ -370,28 +361,13 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 	if (ret)
 		return ret;
 
-	ret = hclge_tm_flush_cfg(hdev, true);
-	if (ret)
-		return ret;
-
-	/* No matter whether the following operations are performed
-	 * successfully or not, disabling the tm flush and notify
-	 * the network status to up are necessary.
-	 * Do not return immediately.
-	 */
 	ret = hclge_buffer_alloc(hdev);
-	if (ret)
-		last_bad_ret = ret;
-
-	ret = hclge_tm_flush_cfg(hdev, false);
-	if (ret)
-		last_bad_ret = ret;
-
-	ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
-	if (ret)
-		last_bad_ret = ret;
+	if (ret) {
+		hclge_notify_client(hdev, HNAE3_UP_CLIENT);
+		return ret;
+	}
 
-	return last_bad_ret;
+	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 }
 
 static int hclge_ieee_setapp(struct hnae3_handle *h, struct dcb_app *app)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

@@ -1485,11 +1485,7 @@ int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
 		return ret;
 
 	/* Cfg schd mode for each level schd */
-	ret = hclge_tm_schd_mode_hw(hdev);
-	if (ret)
-		return ret;
-
-	return hclge_tm_flush_cfg(hdev, false);
+	return hclge_tm_schd_mode_hw(hdev);
 }
 
 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
@@ -2119,28 +2115,3 @@ int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
 
 	return 0;
 }
-
-int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable)
-{
-	struct hclge_desc desc;
-	int ret;
-
-	if (!hnae3_ae_dev_tm_flush_supported(hdev))
-		return 0;
-
-	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_FLUSH, false);
-
-	desc.data[0] = cpu_to_le32(enable ? HCLGE_TM_FLUSH_EN_MSK : 0);
-
-	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
-	if (ret) {
-		dev_err(&hdev->pdev->dev,
-			"failed to config tm flush, ret = %d\n", ret);
-		return ret;
-	}
-
-	if (enable)
-		msleep(HCLGE_TM_FLUSH_TIME_MS);
-
-	return ret;
-}

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

@@ -33,9 +33,6 @@ enum hclge_opcode_type;
 #define HCLGE_DSCP_MAP_TC_BD_NUM	2
 #define HCLGE_DSCP_TC_SHIFT(n)		(((n) & 1) * 4)
 
-#define HCLGE_TM_FLUSH_TIME_MS	10
-#define HCLGE_TM_FLUSH_EN_MSK	BIT(0)
-
 struct hclge_pg_to_pri_link_cmd {
 	u8 pg_id;
 	u8 rsvd1[3];
@@ -278,5 +275,4 @@ int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
 			     struct hclge_tm_shaper_para *para);
 int hclge_up_to_tc_map(struct hclge_dev *hdev);
 int hclge_dscp_to_tc_map(struct hclge_dev *hdev);
-int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable);
 #endif