未验证 提交 a1b1e988 编写于 作者: A Akshu Agrawal 提交者: Mark Brown

ASoC: AMD: Change MCLK to 48Mhz

25Mhz MCLK which was earlier used was of spread type.
Thus, we were not getting accurate rate. The 48Mhz system
clk is of non-spread type and we are changing to it to get
accurate rate.
Signed-off-by: NAkshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
上级 c736cbd3
......@@ -42,7 +42,7 @@
#include "../codecs/da7219.h"
#include "../codecs/da7219-aad.h"
#define CZ_PLAT_CLK 25000000
#define CZ_PLAT_CLK 48000000
#define DUAL_CHANNEL 2
static struct snd_soc_jack cz_jack;
......
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