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提交 9e5f3ffc 编写于 作者: L Linus Torvalds
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Merge tag 'devicetree-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:

 - Refactor arch kdump DT related code to a common implementation

 - Add fw_devlink tracking for 'phy-handle', 'leds', 'backlight',
   'resets', and 'pwm' properties

 - Various clean-ups to DT FDT code

 - Fix a runtime error for !CONFIG_SYSFS

 - Convert Synopsys DW PCI and derivative binding docs to schemas. Add
   Toshiba Visconti PCIe binding.

 - Convert a bunch of memory controller bindings to schemas

 - Covert eeprom-93xx46, Samsung Exynos TRNG, Samsung Exynos IRQ
   combiner, arm-charlcd, img-ascii-lcd, UniPhier eFuse, Xilinx Zynq
   MPSoC FPGA, Xilinx Zynq MPSoC reset, Mediatek mmsys, Gemini boards,
   brcm,iproc-i2c, faraday,ftpci100, and ks8851 net to DT schema.

 - Extend nvmem bindings to handle bit offsets in unit-addresses

 - Add DT schemas for HiKey 970 PCIe PHY

 - Remove unused ZTE, energymicro,efm32-timer, and Exynos SATA bindings

 - Enable dtc pci_device_reg warning by default

 - Fixes for handling 'unevaluatedProperties' in preparation to enable
   pending support in the tooling for jsonschema 2020-12 draft

* tag 'devicetree-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (78 commits)
  dt-bindings: display: remove zte,vou.txt binding doc
  dt-bindings: hwmon: merge max1619 into trivial devices
  dt-bindings: mtd-physmap: Add 'arm,vexpress-flash' compatible
  dt-bindings: PCI: imx6: convert the imx pcie controller to dtschema
  dt-bindings: Use 'enum' instead of 'oneOf' plus 'const' entries
  dt-bindings: Add vendor prefix for Topic Embedded Systems
  of: fdt: Rename reserve_elfcorehdr() to fdt_reserve_elfcorehdr()
  arm64: kdump: Remove custom linux,usable-memory-range handling
  arm64: kdump: Remove custom linux,elfcorehdr handling
  riscv: Remove non-standard linux,elfcorehdr handling
  of: fdt: Use IS_ENABLED(CONFIG_BLK_DEV_INITRD) instead of #ifdef
  of: fdt: Add generic support for handling usable memory range property
  of: fdt: Add generic support for handling elf core headers property
  crash_dump: Make elfcorehdr address/size symbols always visible
  dt-bindings: memory: convert Samsung Exynos DMC to dtschema
  dt-bindings: devfreq: event: convert Samsung Exynos PPMU to dtschema
  dt-bindings: devfreq: event: convert Samsung Exynos NoCP to dtschema
  kbuild: Enable dtc 'pci_device_reg' warning by default
  dt-bindings: soc: remove obsolete zte zx header
  dt-bindings: clock: remove obsolete zte zx header
  ...
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Documentation/devicetree/bindings/Makefile
浏览文件 @ 9e5f3ffc
......@@ -28,7 +28,7 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = ($(find_cmd) | \
......
Documentation/devicetree/bindings/arm/gemini.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Cortina systems Gemini platforms
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
produced by Storlink Semiconductor around 2005. The company was renamed
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
It was derived from earlier products from Storm named SL3316 (Centroid) and
SL3512 (Bulverde).
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
in turn acquired by Inphi, who seem to have discontinued this product family.
Many of the IP blocks used in the SoC comes from Faraday Technology.
Required properties (in root node):
compatible = "cortina,gemini";
Required nodes:
- soc: the SoC should be represented by a simple bus encompassing all the
onchip devices, this is referred to as the soc bus node.
- syscon: the soc bus node must have a system controller node pointing to the
global control registers, with the compatible string
"cortina,gemini-syscon", "syscon";
Required properties on the syscon:
- reg: syscon register location and size.
- #clock-cells: should be set to <1> - the system controller is also a
clock provider.
- #reset-cells: should be set to <1> - the system controller is also a
reset line provider.
The clock sources have shorthand defines in the include file:
<dt-bindings/clock/cortina,gemini-clock.h>
The reset lines have shorthand defines in the include file:
<dt-bindings/reset/cortina,gemini-reset.h>
- timer: the soc bus node must have a timer node pointing to the SoC timer
block, with the compatible string "cortina,gemini-timer"
See: clocksource/cortina,gemini-timer.txt
- interrupt-controller: the sob bus node must have an interrupt controller
node pointing to the SoC interrupt controller block, with the compatible
string "cortina,gemini-interrupt-controller"
See interrupt-controller/cortina,gemini-interrupt-controller.txt
Example:
/ {
model = "Foo Gemini Machine";
compatible = "cortina,gemini";
#address-cells = <1>;
#size-cells = <1>;
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
interrupt-parent = <&intcon>;
syscon: syscon@40000000 {
compatible = "cortina,gemini-syscon", "syscon";
reg = <0x40000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
resets = <&syscon GEMINI_RESET_UART>;
clocks = <&syscon GEMINI_CLK_UART>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
};
timer@43000000 {
compatible = "cortina,gemini-timer";
reg = <0x43000000 0x1000>;
interrupt-parent = <&intcon>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
resets = <&syscon GEMINI_RESET_TIMER>;
/* APB clock or RTC clock */
clocks = <&syscon GEMINI_CLK_APB>,
<&syscon GEMINI_CLK_RTC>;
clock-names = "PCLK", "EXTCLK";
syscon = <&syscon>;
};
intcon: interrupt-controller@48000000 {
compatible = "cortina,gemini-interrupt-controller";
reg = <0x48000000 0x1000>;
resets = <&syscon GEMINI_RESET_INTCON0>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
Documentation/devicetree/bindings/arm/gemini.yaml 0 → 100644
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/gemini.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina systems Gemini platforms
description: |
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
produced by Storlink Semiconductor around 2005. The company was renamed
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
It was derived from earlier products from Storm named SL3316 (Centroid) and
SL3512 (Bulverde).
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
in turn acquired by Inphi, who seem to have discontinued this product family.
Many of the IP blocks used in the SoC comes from Faraday Technology.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Storlink Semiconductor Gemini324 EV-Board also known
as Storm Semiconductor SL93512R_BRD
items:
- const: storlink,gemini324
- const: storm,sl93512r
- const: cortina,gemini
- description: D-Link DIR-685 Xtreme N Storage Router
items:
- const: dlink,dir-685
- const: cortina,gemini
- description: D-Link DNS-313 1-Bay Network Storage Enclosure
items:
- const: dlink,dns-313
- const: cortina,gemini
- description: Edimax NS-2502
items:
- const: edimax,ns-2502
- const: cortina,gemini
- description: ITian Square One SQ201
items:
- const: itian,sq201
- const: cortina,gemini
- description: Raidsonic NAS IB-4220-B
items:
- const: raidsonic,ib-4220-b
- const: cortina,gemini
- description: SSI 1328
items:
- const: ssi,1328
- const: cortina,gemini
- description: Teltonika RUT1xx Mobile Router
items:
- const: teltonika,rut1xx
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-111
items:
- const: wiligear,wiliboard-wbd111
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-222
items:
- const: wiligear,wiliboard-wbd222
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-111 - old incorrect binding
items:
- const: wiliboard,wbd111
- const: cortina,gemini
deprecated: true
- description: Wiligear Wiliboard WBD-222 - old incorrect binding
items:
- const: wiliboard,wbd222
- const: cortina,gemini
deprecated: true
additionalProperties: true
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt 已删除 100644 → 0
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Mediatek mmsys controller
============================
The Mediatek mmsys system controller provides clock control, routing control,
and miscellaneous control in mmsys partition.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt2712-mmsys", "syscon"
- "mediatek,mt6765-mmsys", "syscon"
- "mediatek,mt6779-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8167-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- "mediatek,mt8183-mmsys", "syscon"
- #clock-cells: Must be 1
For the clock control, the mmsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 0 → 100644
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek mmsys controller
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
The MediaTek mmsys system controller provides clock control, routing control,
and miscellaneous control in mmsys partition.
properties:
$nodename:
pattern: "^syscon@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-mmsys
- mediatek,mt2712-mmsys
- mediatek,mt6765-mmsys
- mediatek,mt6779-mmsys
- mediatek,mt6797-mmsys
- mediatek,mt8167-mmsys
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
- const: mediatek,mt2701-mmsys
- const: syscon
reg:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/ata/exynos-sata.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* Samsung AHCI SATA Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- phys : Must contain exactly one entry as specified
in phy-bindings.txt
- phy-names : Must be "sata-phy"
Optional properties:
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Shall be "sata" for the external SATA bus clock,
and "sclk_sata" for the internal controller clock.
Example:
sata@122f0000 {
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122f0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
};
Documentation/devicetree/bindings/auxdisplay/arm,versatile-lcd.yaml 0 → 100644
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/arm,versatile-lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Character LCD
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Rob Herring <robh@kernel.org>
description:
This binding defines the character LCD interface found on ARM Versatile AB
and PB reference platforms.
properties:
compatible:
const: arm,versatile-lcd
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
lcd@10008000 {
compatible = "arm,versatile-lcd";
reg = <0x10008000 0x1000>;
};
Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
ARM Versatile Character LCD
-----------------------------------------------------
This binding defines the character LCD interface found on ARM Versatile AB
and PB reference platforms.
Required properties:
- compatible : "arm,versatile-clcd"
- reg : Location and size of character LCD registers
Optional properties:
- interrupts - single interrupt for character LCD. The character LCD can
operate in polled mode without an interrupt.
Example:
lcd@10008000 {
compatible = "arm,versatile-lcd";
reg = <0x10008000 0x1000>;
};
Documentation/devicetree/bindings/auxdisplay/img,ascii-lcd.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/img,ascii-lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASCII LCD displays on Imagination Technologies boards
maintainers:
- Paul Burton <paulburton@kernel.org>
properties:
compatible:
enum:
- img,boston-lcd
- mti,malta-lcd
- mti,sead3-lcd
reg:
maxItems: 1
offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset in bytes to the LCD registers within the system controller
required:
- compatible
oneOf:
- required:
- reg
- required:
- offset
if:
properties:
compatible:
contains:
const: img,boston-lcd
then:
required:
- reg
else:
required:
- offset
additionalProperties: false
examples:
- |
lcd: lcd@17fff000 {
compatible = "img,boston-lcd";
reg = <0x17fff000 0x8>;
};
Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Binding for ASCII LCD displays on Imagination Technologies boards
Required properties:
- compatible : should be one of:
"img,boston-lcd"
"mti,malta-lcd"
"mti,sead3-lcd"
Required properties for "img,boston-lcd":
- reg : memory region locating the device registers
Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
- regmap: phandle of the system controller containing the LCD registers
- offset: offset in bytes to the LCD registers within the system controller
The layout of the registers & properties of the display are determined
from the compatible string, making this binding somewhat trivial.
Documentation/devicetree/bindings/chosen.txt
浏览文件 @ 9e5f3ffc
......@@ -79,9 +79,9 @@ a different secondary CPU release mechanism)
linux,usable-memory-range
-------------------------
This property (arm64 only) holds a base address and size, describing a
limited region in which memory may be considered available for use by
the kernel. Memory outside of this range is not available for use.
This property holds a base address and size, describing a limited region in
which memory may be considered available for use by the kernel. Memory outside
of this range is not available for use.
This property describes a limitation: memory within this range is only
valid when also described through another mechanism that the kernel
......@@ -106,9 +106,9 @@ respectively, of the root node.
linux,elfcorehdr
----------------
This property (currently used only on arm64) holds the memory range,
the address and the size, of the elf core header which mainly describes
the panicked kernel's memory layout as PT_LOAD segments of elf format.
This property holds the memory range, the address and the size, of the elf
core header which mainly describes the panicked kernel's memory layout as
PT_LOAD segments of elf format.
e.g.
/ {
......
Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* Samsung Exynos NoC (Network on Chip) Probe device
The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
NoC provides the primitive values to get the performance data. The packets
that the Network on Chip (NoC) probes detects are transported over
the network infrastructure to observer units. You can configure probes to
capture packets with header or data on the data request response network,
or as traffic debug or statistic collectors. Exynos542x bus has multiple
NoC probes to provide bandwidth information about behavior of the SoC
that you can use while analyzing system performance.
Required properties:
- compatible: Should be "samsung,exynos5420-nocp"
- reg: physical base address of each NoC Probe and length of memory mapped region.
Optional properties:
- clock-names : the name of clock used by the NoC Probe, "nocp"
- clocks : phandles for clock specified in "clock-names" property
Example : NoC Probe nodes in Device Tree are listed below.
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
};
Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* Samsung Exynos PPMU (Platform Performance Monitoring Unit) device
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
each IP. PPMU provides the primitive values to get performance data. These
PPMU events provide information of the SoC's behaviors so that you may
use to analyze system performance, to make behaviors visible and to count
usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
The Exynos PPMU driver uses the devfreq-event class to provide event data
to various devfreq devices. The devfreq devices would use the event data when
derterming the current state of each IP.
Required properties for PPMU device:
- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
- reg: physical base address of each PPMU and length of memory mapped region.
Optional properties for PPMU device:
- clock-names : the name of clock used by the PPMU, "ppmu"
- clocks : phandles for clock specified in "clock-names" property
Required properties for 'events' child node of PPMU device:
- event-name : the unique event name among PPMU device
Optional properties for 'events' child node of PPMU device:
- event-data-type : Define the type of data which shell be counted
by the counter. You can check include/dt-bindings/pmu/exynos_ppmu.h for
all possible type, i.e. count read requests, count write data in bytes,
etc. This field is optional and when it is missing, the driver code
will use default data type.
Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
ppmu_dmc0: ppmu_dmc0@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
status = "disabled";
};
ppmu_dmc1: ppmu_dmc1@106b0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106b0000 0x2000>;
status = "disabled";
};
ppmu_cpu: ppmu_cpu@106c0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106c0000 0x2000>;
status = "disabled";
};
ppmu_rightbus: ppmu_rightbus@112a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x112a0000 0x2000>;
clocks = <&cmu CLK_PPMURIGHT>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_leftbus: ppmu_leftbus0@116a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x116a0000 0x2000>;
clocks = <&cmu CLK_PPMULEFT>;
clock-names = "ppmu";
status = "disabled";
};
Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
&ppmu_dmc0 {
status = "okay";
events {
ppmu_dmc0_3: ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
};
ppmu_dmc0_2: ppmu-event2-dmc0 {
event-name = "ppmu-event2-dmc0";
};
ppmu_dmc0_1: ppmu-event1-dmc0 {
event-name = "ppmu-event1-dmc0";
};
ppmu_dmc0_0: ppmu-event0-dmc0 {
event-name = "ppmu-event0-dmc0";
};
};
};
&ppmu_dmc1 {
status = "okay";
events {
ppmu_dmc1_3: ppmu-event3-dmc1 {
event-name = "ppmu-event3-dmc1";
};
};
};
&ppmu_leftbus {
status = "okay";
events {
ppmu_leftbus_3: ppmu-event3-leftbus {
event-name = "ppmu-event3-leftbus";
};
};
};
&ppmu_rightbus {
status = "okay";
events {
ppmu_rightbus_3: ppmu-event3-rightbus {
event-name = "ppmu-event3-rightbus";
};
};
};
Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10480000 0x2000>;
status = "disabled";
};
ppmu_d0_general: ppmu_d0_general@10490000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10490000 0x2000>;
status = "disabled";
};
ppmu_d0_rt: ppmu_d0_rt@104a0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104a0000 0x2000>;
status = "disabled";
};
ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104b0000 0x2000>;
status = "disabled";
};
ppmu_d1_general: ppmu_d1_general@104c0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104c0000 0x2000>;
status = "disabled";
};
ppmu_d1_rt: ppmu_d1_rt@104d0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104d0000 0x2000>;
status = "disabled";
};
Example4 : 'event-data-type' in exynos4412-ppmu-common.dtsi are listed below.
&ppmu_dmc0 {
status = "okay";
events {
ppmu_dmc0_3: ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
event-data-type = <(PPMU_RO_DATA_CNT |
PPMU_WO_DATA_CNT)>;
};
};
};
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos NoC (Network on Chip) Probe
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
NoC provides the primitive values to get the performance data. The packets
that the Network on Chip (NoC) probes detects are transported over the
network infrastructure to observer units. You can configure probes to capture
packets with header or data on the data request response network, or as
traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
to provide bandwidth information about behavior of the SoC that you can use
while analyzing system performance.
properties:
compatible:
const: samsung,exynos5420-nocp
clock-names:
items:
- const: nocp
clocks:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10ca1000 0x200>;
};
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
each IP. PPMU provides the primitive values to get performance data. These
PPMU events provide information of the SoC's behaviors so that you may use to
analyze system performance, to make behaviors visible and to count usages of
each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
Exynos PPMU driver uses the devfreq-event class to provide event data to
various devfreq devices. The devfreq devices would use the event data when
derterming the current state of each IP.
properties:
compatible:
enum:
- samsung,exynos-ppmu
- samsung,exynos-ppmu-v2
clock-names:
items:
- const: ppmu
clocks:
maxItems: 1
reg:
maxItems: 1
events:
type: object
patternProperties:
'^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
type: object
properties:
event-name:
description: |
The unique event name among PPMU device
$ref: /schemas/types.yaml#/definitions/string
event-data-type:
description: |
Define the type of data which shell be counted by the counter.
You can check include/dt-bindings/pmu/exynos_ppmu.h for all
possible type, i.e. count read requests, count write data in
bytes, etc. This field is optional and when it is missing, the
driver code will use default data type.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- event-name
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
// PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
#include <dt-bindings/clock/exynos3250.h>
ppmu_dmc0: ppmu@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
events {
ppmu_dmc0_3: ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
};
ppmu_dmc0_2: ppmu-event2-dmc0 {
event-name = "ppmu-event2-dmc0";
};
ppmu_dmc0_1: ppmu-event1-dmc0 {
event-name = "ppmu-event1-dmc0";
};
ppmu_dmc0_0: ppmu-event0-dmc0 {
event-name = "ppmu-event0-dmc0";
};
};
};
ppmu_rightbus: ppmu@112a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x112a0000 0x2000>;
clocks = <&cmu CLK_PPMURIGHT>;
clock-names = "ppmu";
events {
ppmu_rightbus_3: ppmu-event3-rightbus {
event-name = "ppmu-event3-rightbus";
};
};
};
- |
// PPMUv2 nodes in Exynos5433
ppmu_d0_cpu: ppmu@10480000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10480000 0x2000>;
};
ppmu_d0_general: ppmu@10490000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10490000 0x2000>;
events {
ppmu_event0_d0_general: ppmu-event0-d0-general {
event-name = "ppmu-event0-d0-general";
};
};
};
ppmu_d0_rt: ppmu@104a0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104a0000 0x2000>;
};
ppmu_d1_cpu: ppmu@104b0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104b0000 0x2000>;
};
ppmu_d1_general: ppmu@104c0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104c0000 0x2000>;
};
ppmu_d1_rt: ppmu@104d0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104d0000 0x2000>;
};
- |
// PPMUv1 nodes with event-data-type for Exynos4412
#include <dt-bindings/pmu/exynos_ppmu.h>
ppmu@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
clocks = <&clock 400>;
clock-names = "ppmu";
events {
ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
event-data-type = <(PPMU_RO_DATA_CNT |
PPMU_WO_DATA_CNT)>;
};
};
};
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
浏览文件 @ 9e5f3ffc
......@@ -174,7 +174,6 @@ examples:
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
ports {
#address-cells = <1>;
......@@ -233,7 +232,6 @@ examples:
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
ports {
#address-cells = <1>;
......
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
浏览文件 @ 9e5f3ffc
......@@ -37,7 +37,8 @@ properties:
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Video port for MIPI DSI Channel-A input
properties:
......@@ -57,7 +58,8 @@ properties:
- const: 4
port@1:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Video port for MIPI DSI Channel-B input
properties:
......
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
浏览文件 @ 9e5f3ffc
......@@ -27,6 +27,7 @@ properties:
- fsl,imx6ul-lcdif
- fsl,imx7d-lcdif
- fsl,imx8mm-lcdif
- fsl,imx8mn-lcdif
- fsl,imx8mq-lcdif
- const: fsl,imx6sx-lcdif
......
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
浏览文件 @ 9e5f3ffc
......@@ -89,7 +89,8 @@ properties:
properties:
port@0:
$ref: "/schemas/graph.yaml#/properties/port"
$ref: "/schemas/graph.yaml#/$defs/port-base"
unevaluatedProperties: false
description: |
Input endpoints of the controller.
properties:
......@@ -104,7 +105,8 @@ properties:
enum: [ 0, 1, 2, 3 ]
port@1:
$ref: "/schemas/graph.yaml#/properties/port"
$ref: "/schemas/graph.yaml#/$defs/port-base"
unevaluatedProperties: false
description: |
Output endpoints of the controller.
properties:
......
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
浏览文件 @ 9e5f3ffc
......@@ -14,9 +14,9 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-10nm
- const: qcom,dsi-phy-10nm-8998
enum:
- qcom,dsi-phy-10nm
- qcom,dsi-phy-10nm-8998
reg:
items:
......
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
浏览文件 @ 9e5f3ffc
......@@ -14,9 +14,9 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-14nm
- const: qcom,dsi-phy-14nm-660
enum:
- qcom,dsi-phy-14nm
- qcom,dsi-phy-14nm-660
reg:
items:
......
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
浏览文件 @ 9e5f3ffc
......@@ -14,8 +14,7 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-20nm
const: qcom,dsi-phy-20nm
reg:
items:
......
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
浏览文件 @ 9e5f3ffc
......@@ -14,10 +14,10 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-28nm-hpm
- const: qcom,dsi-phy-28nm-lp
- const: qcom,dsi-phy-28nm-8960
enum:
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-lp
- qcom,dsi-phy-28nm-8960
reg:
items:
......
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
浏览文件 @ 9e5f3ffc
......@@ -70,7 +70,6 @@ examples:
avee-supply = <&ppvarp_lcd>;
pp1800-supply = <&pp1800_lcd>;
backlight = <&backlight_lcd0>;
status = "okay";
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
......
Documentation/devicetree/bindings/display/zte,vou.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
ZTE VOU Display Controller
This is a display controller found on ZTE ZX296718 SoC. It includes multiple
Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
handling scaling, color space conversion etc. VOU also integrates the support
for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
* Master VOU node
It must be the parent node of all the sub-device nodes.
Required properties:
- compatible: should be "zte,zx296718-vou"
- #address-cells: should be <1>
- #size-cells: should be <1>
- ranges: list of address translations between VOU and sub-devices
* VOU DPC device
Required properties:
- compatible: should be "zte,zx296718-dpc"
- reg: Physical base address and length of DPC register regions, one for each
entry in 'reg-names'
- reg-names: The names of register regions. The following regions are required:
"osd"
"timing_ctrl"
"dtrc"
"vou_ctrl"
"otfppu"
- interrupts: VOU DPC interrupt number to CPU
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. The following clocks are required:
"aclk"
"ppu_wclk"
"main_wclk"
"aux_wclk"
* HDMI output device
Required properties:
- compatible: should be "zte,zx296718-hdmi"
- reg: Physical base address and length of the HDMI device IO region
- interrupts : HDMI interrupt number to CPU
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. The following clocks are required:
"osc_cec"
"osc_clk"
"xclk"
* TV Encoder output device
Required properties:
- compatible: should be "zte,zx296718-tvenc"
- reg: Physical base address and length of the TVENC device IO region
- zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
integer cells. The first cell is the offset of SYSCTRL register used
to control TV Encoder DAC power, and the second cell is the bit mask.
* VGA output device
Required properties:
- compatible: should be "zte,zx296718-vga"
- reg: Physical base address and length of the VGA device IO region
- interrupts : VGA interrupt number to CPU
- clocks: Phandle with clock-specifier pointing to VGA I2C clock.
- clock-names: Must be "i2c_wclk".
- zte,vga-power-control: the phandle to SYSCTRL block followed by two
integer cells. The first cell is the offset of SYSCTRL register used
to control VGA DAC power, and the second cell is the bit mask.
Example:
vou: vou@1440000 {
compatible = "zte,zx296718-vou";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1440000 0x10000>;
dpc: dpc@0 {
compatible = "zte,zx296718-dpc";
reg = <0x0000 0x1000>, <0x1000 0x1000>,
<0x5000 0x1000>, <0x6000 0x1000>,
<0xa000 0x1000>;
reg-names = "osd", "timing_ctrl",
"dtrc", "vou_ctrl",
"otfppu";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
clock-names = "aclk", "ppu_wclk",
"main_wclk", "aux_wclk";
};
vga: vga@8000 {
compatible = "zte,zx296718-vga";
reg = <0x8000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VGA_I2C_WCLK>;
clock-names = "i2c_wclk";
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
};
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
clocks = <&topcrm HDMI_OSC_CEC>,
<&topcrm HDMI_OSC_CLK>,
<&topcrm HDMI_XCLK>;
clock-names = "osc_cec", "osc_clk", "xclk";
};
tvenc: tvenc@2000 {
compatible = "zte,zx296718-tvenc";
reg = <0x2000 0x1000>;
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
};
};
Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml
浏览文件 @ 9e5f3ffc
......@@ -19,12 +19,12 @@ properties:
description: The cell is the request line number.
compatible:
oneOf:
- const: allwinner,sun6i-a31-dma
- const: allwinner,sun8i-a23-dma
- const: allwinner,sun8i-a83t-dma
- const: allwinner,sun8i-h3-dma
- const: allwinner,sun8i-v3s-dma
enum:
- allwinner,sun6i-a31-dma
- allwinner,sun8i-a23-dma
- allwinner,sun8i-a83t-dma
- allwinner,sun8i-h3-dma
- allwinner,sun8i-v3s-dma
reg:
maxItems: 1
......
Documentation/devicetree/bindings/firmware/arm,scpi.yaml
浏览文件 @ 9e5f3ffc
......@@ -131,9 +131,9 @@ properties:
properties:
compatible:
oneOf:
- const: arm,scpi-dvfs-clocks
- const: arm,scpi-variable-clocks
enum:
- arm,scpi-dvfs-clocks
- arm,scpi-variable-clocks
'#clock-cells':
const: 1
......
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
Programmable Logic (PL). The configuration uses the firmware interface.
Required properties:
- compatible: should contain "xlnx,zynqmp-pcap-fpga"
Example for full FPGA configuration:
fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
};
};
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings
maintainers:
- Nava kishore Manne <navam@xilinx.com>
description: |
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
configure the Programmable Logic (PL). The configuration uses the
firmware interface.
properties:
compatible:
const: xlnx,zynqmp-pcap-fpga
required:
- compatible
additionalProperties: false
examples:
- |
firmware {
zynqmp_firmware: zynqmp-firmware {
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
};
};
...
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
浏览文件 @ 9e5f3ffc
......@@ -20,6 +20,7 @@ properties:
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
reg:
......
Documentation/devicetree/bindings/hwmon/max1619.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Bindings for MAX1619 Temperature Sensor
Required properties:
- compatible : "maxim,max1619"
- reg : I2C address, one of 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, or
0x4d, 0x4e
Example:
temp@4c {
compatible = "maxim,max1619";
reg = <0x4c>;
};
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Broadcom iProc I2C controller
Required properties:
- compatible:
Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c"
- reg:
Define the base and range of the I/O address space that contain the iProc
I2C controller registers
- clock-frequency:
This is the I2C bus clock. Need to be either 100000 or 400000
- #address-cells:
Always 1 (for I2C addresses)
- #size-cells:
Always 0
Optional properties:
- interrupts:
Should contain the I2C interrupt. For certain revisions of the I2C
controller, I2C interrupt is unwired to the interrupt controller. In such
case, this property should be left unspecified, and driver will fall back
to polling mode
- brcm,ape-hsls-addr-mask:
Required for "brcm,iproc-nic-i2c". Host view of address mask into the
'APE' co-processor. Value must be unsigned, 32-bit
Example:
i2c0: i2c@18008000 {
compatible = "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
codec: wm8750@1a {
compatible = "wlf,wm8750";
reg = <0x1a>;
};
};
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/brcm,iproc-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom iProc I2C controller
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
enum:
- brcm,iproc-i2c
- brcm,iproc-nic-i2c
reg:
maxItems: 1
clock-frequency:
enum: [ 100000, 400000 ]
interrupts:
description: |
Should contain the I2C interrupt. For certain revisions of the I2C
controller, I2C interrupt is unwired to the interrupt controller. In such
case, this property should be left unspecified, and driver will fall back
to polling mode
maxItems: 1
brcm,ape-hsls-addr-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: Host view of address mask into the 'APE' co-processor
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:
compatible:
contains:
const: brcm,iproc-nic-i2c
then:
required:
- brcm,ape-hsls-addr-mask
unevaluatedProperties: false
required:
- reg
- clock-frequency
- '#address-cells'
- '#size-cells'
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@18008000 {
compatible = "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
wm8750@1a {
compatible = "wlf,wm8750";
reg = <0x1a>;
};
};
Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml
浏览文件 @ 9e5f3ffc
......@@ -72,11 +72,11 @@ additionalProperties: false
if:
properties:
compatible:
oneOf:
- const: ti,omap2420-i2c
- const: ti,omap2430-i2c
- const: ti,omap3-i2c
- const: ti,omap4-i2c
enum:
- ti,omap2420-i2c
- ti,omap2430-i2c
- ti,omap3-i2c
- ti,omap4-i2c
then:
properties:
......
Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
浏览文件 @ 9e5f3ffc
......@@ -19,10 +19,10 @@ allOf:
properties:
compatible:
oneOf:
- const: loongson,liointc-1.0
- const: loongson,liointc-1.0a
- const: loongson,liointc-2.0
enum:
- loongson,liointc-1.0
- loongson,liointc-1.0a
- loongson,liointc-2.0
reg:
minItems: 1
......
Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* Samsung Exynos Interrupt Combiner Controller
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt request
for the group. The interrupt request from each group are connected to a parent
interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Up to eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt
is usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register
can accommodate up to 4 interrupt combiners (with each combiner supporting
up to 8 interrupt sources).
Required properties:
- compatible: should be "samsung,exynos4210-combiner".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <2>. The meaning of the cells are
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
- reg: Base address and size of interrupt combiner registers.
- interrupts: The list of interrupts generated by the combiners which are then
connected to a parent interrupt controller. The format of the interrupt
specifier depends in the interrupt parent controller.
Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
Example:
The following is a an example from the Exynos4210 SoC dtsi file.
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Interrupt Combiner Controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt
request for the group. The interrupt request from each group are connected to
a parent interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Up to eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt is
usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register can
accommodate up to 4 interrupt combiners (with each combiner supporting up to
8 interrupt sources).
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
const: samsung,exynos4210-combiner
interrupt-controller: true
interrupts:
minItems: 8
maxItems: 32
"#interrupt-cells":
description: |
The meaning of the cells are:
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
const: 2
reg:
maxItems: 1
samsung,combiner-nr:
description: |
The number of interrupt combiners supported. Should match number
of interrupts set in "interrupts" property.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 8
maximum: 32
default: 16
required:
- compatible
- interrupt-controller
- interrupts
- "#interrupt-cells"
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
浏览文件 @ 9e5f3ffc
......@@ -46,7 +46,7 @@ properties:
AM437x family of SoCs,
AM57xx family of SoCs
66AK2G family of SoCs
Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
reg:
maxItems: 1
......@@ -95,6 +95,8 @@ properties:
- AM65x and J721E SoCs have "host_intr5", "host_intr6" and
"host_intr7" interrupts connected to MPU, and other ICSSG
instances.
- AM64x SoCs have all the 8 host interrupts connected to various
other SoC entities
required:
- compatible
......
Documentation/devicetree/bindings/media/atmel,isc.yaml
浏览文件 @ 9e5f3ffc
......@@ -44,7 +44,8 @@ properties:
const: isc-mck
port:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port node, single endpoint describing the input pad.
......
Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
浏览文件 @ 9e5f3ffc
......@@ -83,10 +83,10 @@ properties:
link-frequencies: true
data-lanes: true
bus-type:
oneOf:
- const: 1 # CSI-2 C-PHY
- const: 3 # CCP2
- const: 4 # CSI-2 D-PHY
enum:
- 1 # CSI-2 C-PHY
- 3 # CCP2
- 4 # CSI-2 D-PHY
required:
- link-frequencies
......
Documentation/devicetree/bindings/media/microchip,xisc.yaml
浏览文件 @ 9e5f3ffc
......@@ -52,7 +52,7 @@ properties:
of the data and clock lines.
port:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
description:
Input port node, single endpoint describing the input pad.
......
Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml
浏览文件 @ 9e5f3ffc
......@@ -200,8 +200,6 @@ examples:
clock-names = "pclk", "wrap", "phy", "axi";
power-domains = <&mipi_pd>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
......
Documentation/devicetree/bindings/media/renesas,drif.yaml
浏览文件 @ 9e5f3ffc
......@@ -96,7 +96,7 @@ properties:
Indicates that the channel acts as primary among the bonded channels.
port:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Child port node corresponding to the data input. The port node must
......@@ -242,7 +242,6 @@ examples:
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
......
Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
The DDR controller of the AR7xxx and AR9xxx families provides an interface
to flush the FIFO between various devices and the DDR. This is mainly used
by the IRQ controller to flush the FIFO before running the interrupt handler
of such devices.
Required properties:
- compatible: has to be "qca,<soc-type>-ddr-controller",
"qca,[ar7100|ar7240]-ddr-controller" as fallback.
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
fallback, otherwise "qca,ar7240-ddr-controller" should be used.
- reg: Base address and size of the controller's memory area
- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
the write buffer channel index, should be 1.
Example:
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9132-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
...
interrupt-controller {
...
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
DDR PHY Front End (DPFE) for Broadcom STB
=========================================
DPFE and the DPFE firmware provide an interface for the host CPU to
communicate with the DCPU, which resides inside the DDR PHY.
There are three memory regions for interacting with the DCPU. These are
specified in a single reg property.
Required properties:
- compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"
or "brcm,dpfe-cpu"
- reg: must reference three register ranges
- start address and length of the DCPU register space
- start address and length of the DCPU data memory space
- start address and length of the DCPU instruction memory space
- reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";
they must be in the same order as the register declarations
Example:
dpfe_cpu0: dpfe-cpu@f1132000 {
compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
reg = <0xf1132000 0x180
0xf1134000 0x1000
0xf1138000 0x4000>;
reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
};
Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/brcm,dpfe-cpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DDR PHY Front End (DPFE) for Broadcom STB
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Markus Mayer <mmayer@broadcom.com>
properties:
compatible:
items:
- enum:
- brcm,bcm7271-dpfe-cpu
- brcm,bcm7268-dpfe-cpu
- const: brcm,dpfe-cpu
reg:
items:
- description: DCPU register space
- description: DCPU data memory space
- description: DCPU instruction memory space
reg-names:
items:
- const: dpfe-cpu
- const: dpfe-dmem
- const: dpfe-imem
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
dpfe-cpu@f1132000 {
compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
reg = <0xf1132000 0x180>,
<0xf1134000 0x1000>,
<0xf1138000 0x4000>;
reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
};
Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
memory chips are connected. The driver is to monitor the controller in runtime
and switch frequency and voltage. To monitor the usage of the controller in
runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
is able to measure the current load of the memory.
When 'userspace' governor is used for the driver, an application is able to
switch the DMC and memory frequency.
Required properties for DMC device for Exynos5422:
- compatible: Should be "samsung,exynos5422-dmc".
- clocks : list of clock specifiers, must contain an entry for each
required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
"fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
"mout_mclk_cdrex" entries
- devfreq-events : phandles for PPMU devices connected to this DMC.
- vdd-supply : phandle for voltage regulator which is connected.
- reg : registers of two CDREX controllers.
- operating-points-v2 : phandle for OPPs described in v2 definition.
- device-handle : phandle of the connected DRAM memory device. For more
information please refer to documentation file:
Documentation/devicetree/bindings/ddr/lpddr3.txt
- devfreq-events : phandles of the PPMU events used by the controller.
- samsung,syscon-clk : phandle of the clock register set used by the controller,
these registers are used for enabling a 'pause' feature and are not
exposed by clock framework but they must be used in a safe way.
The register offsets are in the driver code and specyfic for this SoC
type.
Optional properties for DMC device for Exynos5422:
- interrupt-parent : The parent interrupt controller.
- interrupts : Contains the IRQ line numbers for the DMC internal performance
event counters in DREX0 and DREX1 channels. Align with specification of the
interrupt line(s) in the interrupt-parent controller.
- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
same as in the 'interrupts' list above.
Example:
ppmu_dmc0_0: ppmu@10d00000 {
compatible = "samsung,exynos-ppmu";
reg = <0x10d00000 0x2000>;
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
clock-names = "ppmu";
events {
ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
event-name = "ppmu-event3-dmc0_0";
};
};
};
dmc: memory-controller@10c20000 {
compatible = "samsung,exynos5422-dmc";
reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
clocks = <&clock CLK_FOUT_SPLL>,
<&clock CLK_MOUT_SCLK_SPLL>,
<&clock CLK_FF_DOUT_SPLL2>,
<&clock CLK_FOUT_BPLL>,
<&clock CLK_MOUT_BPLL>,
<&clock CLK_SCLK_BPLL>,
<&clock CLK_MOUT_MX_MSPLL_CCORE>,
<&clock CLK_MOUT_MCLK_CDREX>;
clock-names = "fout_spll",
"mout_sclk_spll",
"ff_dout_spll2",
"fout_bpll",
"mout_bpll",
"sclk_bpll",
"mout_mx_mspll_ccore",
"mout_mclk_cdrex";
operating-points-v2 = <&dmc_opp_table>;
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
device-handle = <&samsung_K3QF2F20DB>;
vdd-supply = <&buck1_reg>;
samsung,syscon-clk = <&clock>;
interrupt-parent = <&combiner>;
interrupts = <16 0>, <16 1>;
interrupt-names = "drex_0", "drex_1";
};
Documentation/devicetree/bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU SDRAM controller
maintainers:
- Jan Luebbe <jlu@pengutronix.de>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: marvell,armada-xp-sdram-controller
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Device Tree bindings for MVEBU SDRAM controllers
The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
differs from one SoC variant to another, but they also share a number
of commonalities.
For now, this Device Tree binding documentation only documents the
Armada XP SDRAM controller.
Required properties:
- compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
- reg: a resource specifier for the register space, which should
include all SDRAM controller registers as per the datasheet.
Example:
sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
The DDR controller of the AR7xxx and AR9xxx families provides an interface to
flush the FIFO between various devices and the DDR. This is mainly used by
the IRQ controller to flush the FIFO before running the interrupt handler of
such devices.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-ddr-controller
- const: qca,ar7240-ddr-controller
- items:
- enum:
- qca,ar7100-ddr-controller
- qca,ar7240-ddr-controller
"#qca,ddr-wb-channel-cells":
description: |
Specifies the number of cells needed to encode the write buffer channel
index.
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
reg:
maxItems: 1
required:
- compatible
- "#qca,ddr-wb-channel-cells"
- reg
additionalProperties: false
examples:
- |
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9132-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
interrupt-controller {
// ...
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* H8/300 bus controller
Required properties:
- compatible: Must be "renesas,h8300-bsc".
- reg: Base address and length of BSC registers.
Example.
bsc: memory-controller@fee01e {
compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
reg = <0xfee01e 8>;
};
Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: H8/300 bus controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Yoshinori Sato <ysato@users.sourceforge.jp>
properties:
compatible:
items:
- enum:
- renesas,h8300h-bsc
- renesas,h8s-bsc
- const: renesas,h8300-bsc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@fee01e {
compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
reg = <0xfee01e 8>;
};
Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
浏览文件 @ 9e5f3ffc
......@@ -61,12 +61,23 @@ patternProperties:
type: object
properties:
compatible:
enum:
- cfi-flash
- jedec,spi-nor
contains:
enum:
- cfi-flash
- jedec,spi-nor
unevaluatedProperties: false
required:
- compatible
- reg
- reg-names
- clocks
- power-domains
- resets
- '#address-cells'
- '#size-cells'
examples:
- |
#include <dt-bindings/clock/renesas-cpg-mssr.h>
......
Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: |
Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
Controller device
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Lukasz Luba <lukasz.luba@arm.com>
description: |
The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
DRAM memory chips are connected. The driver is to monitor the controller in
runtime and switch frequency and voltage. To monitor the usage of the
controller in runtime, the driver uses the PPMU (Platform Performance
Monitoring Unit), which is able to measure the current load of the memory.
When 'userspace' governor is used for the driver, an application is able to
switch the DMC and memory frequency.
properties:
compatible:
items:
- const: samsung,exynos5422-dmc
clock-names:
items:
- const: fout_spll
- const: mout_sclk_spll
- const: ff_dout_spll2
- const: fout_bpll
- const: mout_bpll
- const: sclk_bpll
- const: mout_mx_mspll_ccore
- const: mout_mclk_cdrex
clocks:
minItems: 8
maxItems: 8
devfreq-events:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
minItems: 1
maxItems: 16
description: phandles of the PPMU events used by the controller.
device-handle:
$ref: '/schemas/types.yaml#/definitions/phandle'
description: |
phandle of the connected DRAM memory device. For more information please
refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
operating-points-v2: true
interrupts:
items:
- description: DMC internal performance event counters in DREX0
- description: DMC internal performance event counters in DREX1
interrupt-names:
items:
- const: drex_0
- const: drex_1
reg:
items:
- description: registers of DREX0
- description: registers of DREX1
samsung,syscon-clk:
$ref: '/schemas/types.yaml#/definitions/phandle'
description: |
Phandle of the clock register set used by the controller, these registers
are used for enabling a 'pause' feature and are not exposed by clock
framework but they must be used in a safe way. The register offsets are
in the driver code and specyfic for this SoC type.
vdd-supply: true
required:
- compatible
- clock-names
- clocks
- devfreq-events
- device-handle
- reg
- samsung,syscon-clk
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
ppmu_dmc0_0: ppmu@10d00000 {
compatible = "samsung,exynos-ppmu";
reg = <0x10d00000 0x2000>;
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
clock-names = "ppmu";
events {
ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
event-name = "ppmu-event3-dmc0_0";
};
};
};
memory-controller@10c20000 {
compatible = "samsung,exynos5422-dmc";
reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
clocks = <&clock CLK_FOUT_SPLL>,
<&clock CLK_MOUT_SCLK_SPLL>,
<&clock CLK_FF_DOUT_SPLL2>,
<&clock CLK_FOUT_BPLL>,
<&clock CLK_MOUT_BPLL>,
<&clock CLK_SCLK_BPLL>,
<&clock CLK_MOUT_MX_MSPLL_CCORE>,
<&clock CLK_MOUT_MCLK_CDREX>;
clock-names = "fout_spll",
"mout_sclk_spll",
"ff_dout_spll2",
"fout_bpll",
"mout_bpll",
"sclk_bpll",
"mout_mx_mspll_ccore",
"mout_mclk_cdrex";
operating-points-v2 = <&dmc_opp_table>;
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
device-handle = <&samsung_K3QF2F20DB>;
vdd-supply = <&buck1_reg>;
samsung,syscon-clk = <&clock>;
interrupt-parent = <&combiner>;
interrupts = <16 0>, <16 1>;
interrupt-names = "drex_0", "drex_1";
};
Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys IntelliDDR Multi Protocol memory controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
description: |
The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
32-bit bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
These both ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
properties:
compatible:
enum:
- xlnx,zynq-ddrc-a05
- xlnx,zynqmp-ddrc-2.40a
interrupts:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
const: xlnx,zynqmp-ddrc-2.40a
then:
required:
- interrupts
else:
properties:
interrupts: false
additionalProperties: false
examples:
- |
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
- |
axi {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 112 4>;
};
};
Documentation/devicetree/bindings/memory-controllers/synopsys.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
These both ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
Required properties:
- compatible: One of:
- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
- reg: Should contain DDR controller registers location and length.
Required properties for "xlnx,zynqmp-ddrc-2.40a":
- interrupts: Property with a value describing the interrupt number.
Example:
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
mc: memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 112 4>;
};
Documentation/devicetree/bindings/memory-controllers/ti,da8xx-ddrctl.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,da8xx-ddrctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments da8xx DDR2/mDDR memory controller
maintainers:
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
properties:
compatible:
const: ti,da850-ddr-controller
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@b0000000 {
compatible = "ti,da850-ddr-controller";
reg = <0xb0000000 0xe8>;
};
Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features
a set of registers which allow to tweak the controller's behavior.
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
Required properties:
- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards
- reg: a tuple containing the base address of the memory
controller and the size of the memory area to map
Example for da850 shown below.
ddrctl {
compatible = "ti,da850-ddr-controller";
reg = <0xb0000000 0xe8>;
};
Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml
浏览文件 @ 9e5f3ffc
......@@ -11,9 +11,9 @@ maintainers:
properties:
compatible:
oneOf:
- const: ti,lp87565
- const: ti,lp87565-q1
enum:
- ti,lp87565
- ti,lp87565-q1
reg:
description: I2C slave address
......
Documentation/devicetree/bindings/misc/eeprom-93xx46.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
EEPROMs (SPI) compatible with Microchip Technology 93xx46 family.
Required properties:
- compatible : shall be one of:
"atmel,at93c46"
"atmel,at93c46d"
"atmel,at93c56"
"atmel,at93c66"
"eeprom-93xx46"
"microchip,93lc46b"
- data-size : number of data bits per word (either 8 or 16)
Optional properties:
- read-only : parameter-less property which disables writes to the EEPROM
- select-gpios : if present, specifies the GPIO that will be asserted prior to
each access to the EEPROM (e.g. for SPI bus multiplexing)
Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
apply. In particular, "reg" and "spi-max-frequency" properties must be given.
Example:
eeprom@0 {
compatible = "eeprom-93xx46";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <8>;
select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
};
Documentation/devicetree/bindings/misc/eeprom-93xx46.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/eeprom-93xx46.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip 93xx46 SPI compatible EEPROM family dt bindings
maintainers:
- Cory Tusar <cory.tusar@pid1solutions.com>
properties:
compatible:
enum:
- atmel,at93c46
- atmel,at93c46d
- atmel,at93c56
- atmel,at93c66
- eeprom-93xx46
- microchip,93lc46b
data-size:
description: number of data bits per word
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
reg:
description: chip select of EEPROM
maxItems: 1
spi-max-frequency: true
spi-cs-high: true
read-only:
description:
parameter-less property which disables writes to the EEPROM
type: boolean
select-gpios:
description:
specifies the GPIO that needs to be asserted prior to each access
of EEPROM (e.g. for SPI bus multiplexing)
maxItems: 1
required:
- compatible
- reg
- data-size
- spi-max-frequency
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
compatible = "eeprom-93xx46";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cs-high;
data-size = <8>;
select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/mtd/gpmc-nor.txt
浏览文件 @ 9e5f3ffc
......@@ -10,7 +10,7 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
16-bit devices and so must be either 1 or 2 bytes.
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
- gpmc,cs-on-ns: Chip-select assertion time
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
......@@ -21,7 +21,7 @@ Required properties:
- gpmc,access-ns: Start cycle to first data capture (read access)
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
- reg: Chip-select, base address (relative to chip-select)
and size of NOR flash. Note that base address will be
typically 0 as this is the start of the chip-select.
......
Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
浏览文件 @ 9e5f3ffc
......@@ -23,6 +23,7 @@ properties:
- amd,s29gl256n
- amd,s29gl512n
- arm,versatile-flash
- arm,vexpress-flash
- cortina,gemini-flash
- cypress,hyperflash
- ge,imp3a-firmware-mirror
......
Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml
浏览文件 @ 9e5f3ffc
......@@ -116,7 +116,6 @@ examples:
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,tso;
status = "okay";
mdio0 {
#address-cells = <1>;
......
Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml
浏览文件 @ 9e5f3ffc
......@@ -71,7 +71,6 @@ examples:
ethernet@c8009000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc8009000 0x1000>;
status = "disabled";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
intel,npe-handle = <&npe 1>;
......@@ -82,7 +81,6 @@ examples:
ethernet@c800c000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800c000 0x1000>;
status = "disabled";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
intel,npe-handle = <&npe 2>;
......
Documentation/devicetree/bindings/net/micrel,ks8851.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/micrel,ks8851.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Micrel KS8851 Ethernet MAC (SPI and Parallel bus options)
maintainers:
- Marek Vasut <marex@denx.de>
properties:
compatible:
enum:
- micrel,ks8851 # SPI bus option
- micrel,ks8851-mll # Parallel bus option
interrupts:
maxItems: 1
reg:
minItems: 1
items:
- description: SPI or Parallel bus hardware address
- description: Parallel bus command mode address
reset-gpios:
maxItems: 1
description:
The reset_n input pin
vdd-supply:
description: |
Analog 3.3V supply for Ethernet MAC
vdd-io-supply:
description: |
Digital 1.8V IO supply for Ethernet MAC
required:
- compatible
- reg
- interrupts
allOf:
- $ref: ethernet-controller.yaml#
- if:
properties:
compatible:
contains:
const: micrel,ks8851
then:
properties:
reg:
maxItems: 1
- if:
properties:
compatible:
contains:
const: micrel,ks8851-mll
then:
properties:
reg:
minItems: 2
unevaluatedProperties: false
examples:
- |
/* SPI bus option */
spi {
#address-cells = <1>;
#size-cells = <0>;
ethernet@0 {
compatible = "micrel,ks8851";
reg = <0>;
interrupt-parent = <&msmgpio>;
interrupts = <90 8>;
vdd-supply = <&ext_l2>;
vdd-io-supply = <&pm8921_lvs6>;
reset-gpios = <&msmgpio 89 0>;
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
/* Parallel bus option */
memory-controller {
#address-cells = <2>;
#size-cells = <1>;
ethernet@1,0 {
compatible = "micrel,ks8851-mll";
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
interrupt-parent = <&gpioc>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
};
};
Documentation/devicetree/bindings/net/micrel-ks8851.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
Micrel KS8851 Ethernet mac (MLL)
Required properties:
- compatible = "micrel,ks8851-mll" of parallel interface
- reg : 2 physical address and size of registers for data and command
- interrupts : interrupt connection
Micrel KS8851 Ethernet mac (SPI)
Required properties:
- compatible = "micrel,ks8851" or the deprecated "ks8851"
- reg : chip select number
- interrupts : interrupt connection
Optional properties:
- vdd-supply: analog 3.3V supply for Ethernet mac
- vdd-io-supply: digital 1.8V IO supply for Ethernet mac
- reset-gpios: reset_n input pin
Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
浏览文件 @ 9e5f3ffc
......@@ -67,7 +67,7 @@ Example:
compatible = "ethernet-phy-id0007.0570";
vsc8531,vddmac = <3300>;
vsc8531,edge-slowdown = <7>;
vsc8531,led-0-mode = <LINK_1000_ACTIVITY>;
vsc8531,led-1-mode = <LINK_100_ACTIVITY>;
vsc8531,led-0-mode = <VSC8531_LINK_1000_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_100_ACTIVITY>;
load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
};
Documentation/devicetree/bindings/net/nfc/samsung,s3fwrn5.yaml
浏览文件 @ 9e5f3ffc
......@@ -90,14 +90,11 @@ examples:
# UART example on Raspberry Pi
- |
uart0 {
status = "okay";
nfc {
compatible = "samsung,s3fwrn82";
en-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
wake-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
Documentation/devicetree/bindings/net/qca,ar71xx.yaml
浏览文件 @ 9e5f3ffc
......@@ -101,8 +101,6 @@ examples:
phy-mode = "gmii";
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
......@@ -148,32 +146,24 @@ examples:
reg = <0x1>;
phy-handle = <&phy_port0>;
phy-mode = "internal";
status = "disabled";
};
switch_port2: port@2 {
reg = <0x2>;
phy-handle = <&phy_port1>;
phy-mode = "internal";
status = "disabled";
};
switch_port3: port@3 {
reg = <0x3>;
phy-handle = <&phy_port2>;
phy-mode = "internal";
status = "disabled";
};
switch_port4: port@4 {
reg = <0x4>;
phy-handle = <&phy_port3>;
phy-mode = "internal";
status = "disabled";
};
};
......@@ -183,34 +173,29 @@ examples:
interrupt-parent = <&switch10>;
phy_port0: phy@0 {
phy_port0: ethernet-phy@0 {
reg = <0x0>;
interrupts = <0>;
status = "disabled";
};
phy_port1: phy@1 {
phy_port1: ethernet-phy@1 {
reg = <0x1>;
interrupts = <0>;
status = "disabled";
};
phy_port2: phy@2 {
phy_port2: ethernet-phy@2 {
reg = <0x2>;
interrupts = <0>;
status = "disabled";
};
phy_port3: phy@3 {
phy_port3: ethernet-phy@3 {
reg = <0x3>;
interrupts = <0>;
status = "disabled";
};
phy_port4: phy@4 {
phy_port4: ethernet-phy@4 {
reg = <0x4>;
interrupts = <0>;
status = "disabled";
};
};
};
......
Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
浏览文件 @ 9e5f3ffc
......@@ -17,10 +17,10 @@ description:
properties:
compatible:
oneOf:
- const: "realtek,rtl8723bs-bt"
- const: "realtek,rtl8723cs-bt"
- const: "realtek,rtl8822cs-bt"
enum:
- realtek,rtl8723bs-bt
- realtek,rtl8723cs-bt
- realtek,rtl8822cs-bt
device-wake-gpios:
maxItems: 1
......
Documentation/devicetree/bindings/net/renesas,etheravb.yaml
浏览文件 @ 9e5f3ffc
......@@ -43,23 +43,20 @@ properties:
- renesas,etheravb-r8a779a0 # R-Car V3U
- const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
- items:
- enum:
- renesas,r9a07g044-gbeth # RZ/G2{L,LC}
- const: renesas,rzg2l-gbeth # RZ/G2L
reg: true
interrupts: true
interrupt-names: true
clocks:
minItems: 1
items:
- description: AVB functional clock
- description: Optional TXC reference clock
clocks: true
clock-names:
minItems: 1
items:
- const: fck
- const: refclk
clock-names: true
iommus:
maxItems: 1
......@@ -145,14 +142,20 @@ allOf:
properties:
compatible:
contains:
const: renesas,etheravb-rcar-gen2
enum:
- renesas,etheravb-rcar-gen2
- renesas,rzg2l-gbeth
then:
properties:
interrupts:
maxItems: 1
minItems: 1
maxItems: 3
interrupt-names:
minItems: 1
items:
- const: mux
- const: fil
- const: arp_ns
rx-internal-delay-ps: false
else:
properties:
......@@ -208,6 +211,36 @@ allOf:
tx-internal-delay-ps:
const: 2000
- if:
properties:
compatible:
contains:
const: renesas,rzg2l-gbeth
then:
properties:
clocks:
items:
- description: Main clock
- description: Register access clock
- description: Reference clock for RGMII
clock-names:
items:
- const: axi
- const: chi
- const: refclk
else:
properties:
clocks:
minItems: 1
items:
- description: AVB functional clock
- description: Optional TXC reference clock
clock-names:
minItems: 1
items:
- const: fck
- const: refclk
additionalProperties: false
examples:
......
Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
浏览文件 @ 9e5f3ffc
......@@ -53,10 +53,10 @@ properties:
"#size-cells": true
compatible:
oneOf:
- const: ti,am654-cpsw-nuss
- const: ti,j721e-cpsw-nuss
- const: ti,am642-cpsw-nuss
enum:
- ti,am654-cpsw-nuss
- ti,j721e-cpsw-nuss
- ti,am642-cpsw-nuss
reg:
maxItems: 1
......
Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
浏览文件 @ 9e5f3ffc
......@@ -45,9 +45,9 @@ properties:
pattern: "^cpts@[0-9a-f]+$"
compatible:
oneOf:
- const: ti,am65-cpts
- const: ti,j721e-cpts
enum:
- ti,am65-cpts
- ti,j721e-cpts
reg:
maxItems: 1
......
Documentation/devicetree/bindings/nvmem/nvmem.yaml
浏览文件 @ 9e5f3ffc
......@@ -40,7 +40,7 @@ properties:
maxItems: 1
patternProperties:
"^.*@[0-9a-f]+$":
"@[0-9a-f]+(,[0-7])?$":
type: object
properties:
......
Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier eFuse bindings
maintainers:
- Keiji Hayashibara <hayashibara.keiji@socionext.com>
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- $ref: "nvmem.yaml#"
properties:
"#address-cells": true
"#size-cells": true
compatible:
const: socionext,uniphier-efuse
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
// The UniPhier eFuse should be a subnode of a "soc-glue" node.
soc-glue@5f900000 {
compatible = "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x68>;
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
usb_rterm0: trim@54,4 {
reg = <0x54 1>;
bits = <4 2>;
};
usb_rterm1: trim@55,4 {
reg = <0x55 1>;
bits = <4 2>;
};
usb_rterm2: trim@58,4 {
reg = <0x58 1>;
bits = <4 2>;
};
usb_rterm3: trim@59,4 {
reg = <0x59 1>;
bits = <4 2>;
};
usb_sel_t0: trim@54,0 {
reg = <0x54 1>;
bits = <0 4>;
};
usb_sel_t1: trim@55,0 {
reg = <0x55 1>;
bits = <0 4>;
};
usb_sel_t2: trim@58,0 {
reg = <0x58 1>;
bits = <0 4>;
};
usb_sel_t3: trim@59,0 {
reg = <0x59 1>;
bits = <0 4>;
};
usb_hs_i0: trim@56,0 {
reg = <0x56 1>;
bits = <0 4>;
};
usb_hs_i2: trim@5a,0 {
reg = <0x5a 1>;
bits = <0 4>;
};
};
};
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= UniPhier eFuse device tree bindings =
This UniPhier eFuse must be under soc-glue.
Required properties:
- compatible: should be "socionext,uniphier-efuse"
- reg: should contain the register location and length
= Data cells =
Are child nodes of efuse, bindings of which as described in
bindings/nvmem/nvmem.txt
Example:
soc-glue@5f900000 {
compatible = "socionext,uniphier-ld20-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x68>;
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
usb_mon: usb-mon@54 {
reg = <0x54 0xc>;
};
};
};
= Data consumers =
Are device nodes which consume nvmem data cells.
Example:
usb {
...
nvmem-cells = <&usb_mon>;
nvmem-cell-names = "usb_mon";
}
Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
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......@@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller
Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here:
......@@ -33,7 +33,7 @@ Required properties:
- phy-names: must contain "pcie"
- device_type:
should be "pci". As specified in designware-pcie.txt
should be "pci". As specified in snps,dw-pcie.yaml
Example configuration:
......
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
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* Axis ARTPEC-6 PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
......
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* Synopsys DesignWare PCIe interface
Required properties:
- compatible:
"snps,dw-pcie" for RC mode;
"snps,dw-pcie-ep" for EP mode;
- reg: For designware cores version < 4.80 contains the configuration
address space. For designware core version >= 4.80, contains
the configuration and ATU address space
- reg-names: Must be "config" for the PCIe configuration space and "atu" for
the ATU address space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>
- device_type: set to "pci"
- ranges: ranges for the PCI memory and I/O regions
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map: standard PCI
properties to define the mapping of the PCIe interface to interrupt
numbers.
EP mode:
- num-ib-windows: number of inbound address translation windows
- num-ob-windows: number of outbound address translation windows
Optional properties:
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
- reset-gpio: GPIO pin number of power good signal
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
- snps,enable-cdm-check: This is a boolean property and if present enables
automatic checking of CDM (Configuration Dependent Module) registers
for data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers, DMA and iATU (internal Address
Translation Unit) registers.
RC mode:
- num-viewport: number of view ports configured in hardware. If a platform
does not specify it, the driver assumes 2.
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
to specify this property, to keep backwards compatibility a range of
0x00-0xff is assumed if not present)
EP mode:
- max-functions: maximum number of functions that can be configured
Example configuration:
pcie: pcie@dfc00000 {
compatible = "snps,dw-pcie";
reg = <0xdfc00000 0x0001000>, /* IP registers */
<0xd0000000 0x0002000>; /* Configuration space */
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
interrupts = <25>, <24>;
#interrupt-cells = <1>;
num-lanes = <1>;
};
or
pcie: pcie@dfc00000 {
compatible = "snps,dw-pcie-ep";
reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
<0xdfc01000 0x0001000>, /* IP registers 2 */
<0xd0000000 0x2000000>; /* Configuration space */
reg-names = "dbi", "dbi2", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <2>;
num-lanes = <1>;
};
Documentation/devicetree/bindings/pci/faraday,ftpci100.txt 已删除 100644 → 0
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Faraday Technology FTPCI100 PCI Host Bridge
This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
is a generic IP block from Faraday Technology. It exists in two variants:
plain and dual PCI. The plain version embeds a cascading interrupt controller
into the host bridge. The dual version routes the interrupts to the host
chips interrupt controller.
The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
Technology) and product ID 0x4321.
Mandatory properties:
- compatible: ranging from specific to generic, should be one of
"cortina,gemini-pci", "faraday,ftpci100"
"cortina,gemini-pci-dual", "faraday,ftpci100-dual"
"faraday,ftpci100"
"faraday,ftpci100-dual"
- reg: memory base and size for the host bridge
- #address-cells: set to <3>
- #size-cells: set to <2>
- #interrupt-cells: set to <1>
- bus-range: set to <0x00 0xff>
- device_type, set to "pci"
- ranges: see pci.txt
- interrupt-map-mask: see pci.txt
- interrupt-map: see pci.txt
- dma-ranges: three ranges for the inbound memory region. The ranges must
be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
pre-fetchable.
Optional properties:
- clocks: when present, this should contain the peripheral clock (PCLK) and the
PCI clock (PCICLK). If these are not present, they are assumed to be
hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
- clock-names: when present, this should contain "PCLK" for the peripheral
clock and "PCICLK" for the PCI-side clock.
Mandatory subnodes:
- For "faraday,ftpci100" a node representing the interrupt-controller inside the
host bridge is mandatory. It has the following mandatory properties:
- interrupt: see interrupt-controller/interrupts.txt
- interrupt-controller: see interrupt-controller/interrupts.txt
- #address-cells: set to <0>
- #interrupt-cells: set to <1>
I/O space considerations:
The plain variant has 128MiB of non-prefetchable memory space, whereas the
"dual" variant has 64MiB. Take this into account when describing the ranges.
Interrupt map considerations:
The "dual" variant will get INT A, B, C, D from the system interrupt controller
and should point to respective interrupt in that controller in its
interrupt-map.
The code which is the only documentation of how the Faraday PCI (the non-dual
variant) interrupts assigns the default interrupt mapping/swizzling has
typically been like this, doing the swizzling on the interrupt controller side
rather than in the interconnect:
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
<0x4800 0 0 2 &pci_intc 1>,
<0x4800 0 0 3 &pci_intc 2>,
<0x4800 0 0 4 &pci_intc 3>,
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
<0x5000 0 0 2 &pci_intc 2>,
<0x5000 0 0 3 &pci_intc 3>,
<0x5000 0 0 4 &pci_intc 0>,
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
<0x5800 0 0 2 &pci_intc 3>,
<0x5800 0 0 3 &pci_intc 0>,
<0x5800 0 0 4 &pci_intc 1>,
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
<0x6000 0 0 2 &pci_intc 0>,
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
Example:
pci@50000000 {
compatible = "cortina,gemini-pci", "faraday,ftpci100";
reg = <0x50000000 0x100>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */
<26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */
<27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */
<28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
bus-range = <0x00 0xff>;
ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
<0x01000000 0 0 0x50000000 0 0x00100000>,
/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
/* DMA ranges */
dma-ranges =
/* 128MiB at 0x00000000-0x07ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
/* 64MiB at 0x00000000-0x03ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
/* 64MiB at 0x00000000-0x03ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
<0x4800 0 0 2 &pci_intc 1>,
<0x4800 0 0 3 &pci_intc 2>,
<0x4800 0 0 4 &pci_intc 3>,
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
<0x5000 0 0 2 &pci_intc 2>,
<0x5000 0 0 3 &pci_intc 3>,
<0x5000 0 0 4 &pci_intc 0>,
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
<0x5800 0 0 2 &pci_intc 3>,
<0x5800 0 0 3 &pci_intc 0>,
<0x5800 0 0 4 &pci_intc 1>,
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
<0x6000 0 0 2 &pci_intc 0>,
<0x6000 0 0 3 &pci_intc 0>,
<0x6000 0 0 4 &pci_intc 0>;
pci_intc: interrupt-controller {
interrupt-parent = <&intcon>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml 0 → 100644
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/faraday,ftpci100.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTPCI100 PCI Host Bridge
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
is a generic IP block from Faraday Technology. It exists in two variants:
plain and dual PCI. The plain version embeds a cascading interrupt controller
into the host bridge. The dual version routes the interrupts to the host
chips interrupt controller.
The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
Technology) and product ID 0x4321.
I/O space considerations:
The plain variant has 128MiB of non-prefetchable memory space, whereas the
"dual" variant has 64MiB. Take this into account when describing the ranges.
Interrupt map considerations:
The "dual" variant will get INT A, B, C, D from the system interrupt controller
and should point to respective interrupt in that controller in its interrupt-map.
The code which is the only documentation of how the Faraday PCI (the non-dual
variant) interrupts assigns the default interrupt mapping/swizzling has
typically been like this, doing the swizzling on the interrupt controller side
rather than in the interconnect:
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
<0x4800 0 0 2 &pci_intc 1>,
<0x4800 0 0 3 &pci_intc 2>,
<0x4800 0 0 4 &pci_intc 3>,
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
<0x5000 0 0 2 &pci_intc 2>,
<0x5000 0 0 3 &pci_intc 3>,
<0x5000 0 0 4 &pci_intc 0>,
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
<0x5800 0 0 2 &pci_intc 3>,
<0x5800 0 0 3 &pci_intc 0>,
<0x5800 0 0 4 &pci_intc 1>,
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
<0x6000 0 0 2 &pci_intc 0>,
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
oneOf:
- items:
- const: cortina,gemini-pci
- const: faraday,ftpci100
- items:
- const: cortina,gemini-pci-dual
- const: faraday,ftpci100-dual
- const: faraday,ftpci100
- const: faraday,ftpci100-dual
reg:
maxItems: 1
"#address-cells":
const: 3
"#interrupt-cells":
const: 1
ranges:
minItems: 2
dma-ranges:
minItems: 3
description: |
three ranges for the inbound memory region. The ranges must
be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
pre-fetchable.
clocks:
items:
- description: peripheral clock (PCLK)
- description: PCI clock (PCICLK).
description: |
If these are not present, they are assumed to be
hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
clock-names:
items:
- const: PCLK
- const: PCICLK
interrupt-controller:
type: object
required:
- reg
- compatible
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
- dma-ranges
if:
properties:
compatible:
contains:
const: faraday,ftpci100
then:
required:
- interrupt-controller
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pci@50000000 {
compatible = "cortina,gemini-pci", "faraday,ftpci100";
reg = <0x50000000 0x100>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
bus-range = <0x00 0xff>;
ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
<0x01000000 0 0 0x50000000 0 0x00100000>,
/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
/* DMA ranges */
dma-ranges =
/* 128MiB at 0x00000000-0x07ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
/* 64MiB at 0x00000000-0x03ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
/* 64MiB at 0x00000000-0x03ffffff */
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
<0x4800 0 0 2 &pci_intc 1>,
<0x4800 0 0 3 &pci_intc 2>,
<0x4800 0 0 4 &pci_intc 3>,
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
<0x5000 0 0 2 &pci_intc 2>,
<0x5000 0 0 3 &pci_intc 3>,
<0x5000 0 0 4 &pci_intc 0>,
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
<0x5800 0 0 2 &pci_intc 3>,
<0x5800 0 0 3 &pci_intc 0>,
<0x5800 0 0 4 &pci_intc 1>,
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
<0x6000 0 0 2 &pci_intc 0>,
<0x6000 0 0 3 &pci_intc 0>,
<0x6000 0 0 4 &pci_intc 0>;
pci_intc: interrupt-controller {
interrupt-parent = <&intcon>;
interrupt-controller;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt 已删除 100644 → 0
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* Freescale i.MX6 PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible:
- "fsl,imx6q-pcie"
- "fsl,imx6sx-pcie",
- "fsl,imx6qp-pcie"
- "fsl,imx7d-pcie"
- "fsl,imx8mq-pcie"
- reg: base address and length of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
- "msi": The interrupt that is asserted when an MSI is received
- clock-names: Must include the following additional entries:
- "pcie_phy"
Optional properties:
- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs
do not meet gen2 jitter requirements and thus for gen2 capability a gen2
compliant clock generator should be used and configured.
- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
signal. It's not polarity aware and defaults to active-low reset sequence
(L=reset state, H=operation state).
- reset-gpio-active-high: If present then the reset sequence using the GPIO
specified in the "reset-gpio" property is reversed (H=reset state,
L=operation state).
- vpcie-supply: Should specify the regulator in charge of PCIe port power.
The regulator will be enabled when initializing the PCIe host and
disabled either as part of the init process or when shutting down the
host.
- vph-supply: Should specify the regulator in charge of VPH one of the three
PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage
supplies.
Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:
- "pcie_inbound_axi"
- power-domains: Must be set to phandles pointing to the DISPLAY and
PCIE_PHY power domains
- power-domain-names: Must be "pcie", "pcie_phy"
Additional required properties for imx7d-pcie and imx8mq-pcie:
- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
IP block
- reset-names: Must contain the following entries:
- "pciephy"
- "apps"
- "turnoff"
- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
Additional required properties for imx8mq-pcie:
- clock-names: Must include the following additional entries:
- "pcie_aux"
Example:
pcie@01000000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
0x81000000 0 0 0x01f80000 0 0x00010000
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 144>, <&clks 206>, <&clks 189>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
};
* Freescale i.MX7d PCIe PHY
This is the PHY associated with the IMX7d PCIe controller. It's used by the
PCI-e controller via the fsl,imx7d-pcie-phy phandle.
Required properties:
- compatible:
- "fsl,imx7d-pcie-phy"
- reg: base address and length of the PCIe PHY controller
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX6 PCIe host controller
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
- Richard Zhu <hongxing.zhu@nxp.com>
description: |+
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
enum:
- fsl,imx6q-pcie
- fsl,imx6sx-pcie
- fsl,imx6qp-pcie
- fsl,imx7d-pcie
- fsl,imx8mq-pcie
reg:
items:
- description: Data Bus Interface (DBI) registers.
- description: PCIe configuration space region.
reg-names:
items:
- const: dbi
- const: config
interrupts:
items:
- description: builtin MSI controller.
interrupt-names:
minItems: 1
items:
- const: msi
clocks:
minItems: 3
items:
- description: PCIe bridge clock.
- description: PCIe bus clock.
- description: PCIe PHY clock.
- description: Additional required clock entry for imx6sx-pcie,
imx8mq-pcie.
clock-names:
minItems: 3
items:
- const: pcie
- const: pcie_bus
- const: pcie_phy
- const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
num-lanes:
const: 1
fsl,imx7d-pcie-phy:
$ref: /schemas/types.yaml#/definitions/phandle
description: A phandle to an fsl,imx7d-pcie-phy node. Additional
required properties for imx7d-pcie and imx8mq-pcie.
power-domains:
items:
- description: The phandle pointing to the DISPLAY domain for
imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
imx8mq-pcie.
- description: The phandle pointing to the PCIE_PHY power domains
for imx6sx-pcie.
power-domain-names:
items:
- const: pcie
- const: pcie_phy
resets:
maxItems: 3
description: Phandles to PCIe-related reset lines exposed by SRC
IP block. Additional required by imx7d-pcie and imx8mq-pcie.
reset-names:
items:
- const: pciephy
- const: apps
- const: turnoff
fsl,tx-deemph-gen1:
description: Gen1 De-emphasis value (optional required).
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
fsl,tx-deemph-gen2-3p5db:
description: Gen2 (3.5db) De-emphasis value (optional required).
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
fsl,tx-deemph-gen2-6db:
description: Gen2 (6db) De-emphasis value (optional required).
$ref: /schemas/types.yaml#/definitions/uint32
default: 20
fsl,tx-swing-full:
description: Gen2 TX SWING FULL value (optional required).
$ref: /schemas/types.yaml#/definitions/uint32
default: 127
fsl,tx-swing-low:
description: TX launch amplitude swing_low value (optional required).
$ref: /schemas/types.yaml#/definitions/uint32
default: 127
fsl,max-link-speed:
description: Specify PCI Gen for link capability (optional required).
Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
requirements and thus for gen2 capability a gen2 compliant clock
generator should be used and configured.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4]
default: 1
reset-gpio:
description: Should specify the GPIO for controlling the PCI bus device
reset signal. It's not polarity aware and defaults to active-low reset
sequence (L=reset state, H=operation state) (optional required).
reset-gpio-active-high:
description: If present then the reset sequence using the GPIO
specified in the "reset-gpio" property is reversed (H=reset state,
L=operation state) (optional required).
vpcie-supply:
description: Should specify the regulator in charge of PCIe port power.
The regulator will be enabled when initializing the PCIe host and
disabled either as part of the init process or when shutting down
the host (optional required).
vph-supply:
description: Should specify the regulator in charge of VPH one of
the three PCIe PHY powers. This regulator can be supplied by both
1.8v and 3.3v voltage supplies (optional required).
required:
- compatible
- reg
- reg-names
- "#address-cells"
- "#size-cells"
- device_type
- bus-range
- ranges
- num-lanes
- interrupts
- interrupt-names
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie: pcie@1ffc000 {
compatible = "fsl,imx6q-pcie";
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
<0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
};
...
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon Kirin SoCs PCIe host DT description
maintainers:
- Xiaowei Song <songxiaowei@hisilicon.com>
- Binghui Wang <wangbinghui@hisilicon.com>
description: |
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
contains:
enum:
- hisilicon,kirin960-pcie
- hisilicon,kirin970-pcie
reg:
description: |
Should contain dbi, apb, config registers location and length.
For hisilicon,kirin960-pcie, it should also contain phy.
minItems: 3
maxItems: 4
reg-names:
minItems: 3
maxItems: 4
hisilicon,clken-gpios:
description: |
Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
mini-PCIe slots.
required:
- compatible
- reg
- reg-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
#include <dt-bindings/clock/hi3670-clock.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie@f4000000 {
compatible = "hisilicon,kirin960-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>,
<0x0 0xff3fe000 0x0 0x1000>,
<0x0 0xf3f20000 0x0 0x40000>,
<0x0 0xf5000000 0x0 0x2000>;
reg-names = "dbi", "apb", "phy", "config";
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0x0 0x00000000
0x0 0xf6000000
0x0 0x02000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupts = <0 283 4>;
interrupt-names = "msi";
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
"pcie_apb_sys", "pcie_aclk";
};
pcie@f5000000 {
compatible = "hisilicon,kirin970-pcie";
reg = <0x0 0xf4000000 0x0 0x1000000>,
<0x0 0xfc180000 0x0 0x1000>,
<0x0 0xf5000000 0x0 0x2000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
phys = <&pcie_phy>;
ranges = <0x02000000 0x0 0x00000000
0x0 0xf6000000
0x0 0x02000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio7 0 0>;
hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
reg = <0 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0,0 { // Lane 0: upstream
reg = <0 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@1,0 { // Lane 4: M.2
reg = <0x0800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio3 1 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
pcie@5,0 { // Lane 5: Mini PCIe
reg = <0x2800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio27 4 0 >;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
pcie@7,0 { // Lane 6: Ethernet
reg = <0x03800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio25 2 0 >;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
};
};
Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
浏览文件 @ 9e5f3ffc
......@@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description
The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
It shares common functions with the DesignWare PCIe core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here:
......
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
浏览文件 @ 9e5f3ffc
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe RC controller on Intel Gateway SoCs
maintainers:
- Dilip Kota <eswara.kota@linux.intel.com>
- Rahul Tanwar <rtanwar@maxlinear.com>
select:
properties:
......@@ -17,21 +17,15 @@ select:
required:
- compatible
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
items:
- const: intel,lgm-pcie
- const: snps,dw-pcie
device_type:
const: pci
"#address-cells":
const: 3
"#size-cells":
const: 2
reg:
items:
- description: Controller control and status registers.
......@@ -62,30 +56,13 @@ properties:
reset-gpios:
maxItems: 1
linux,pci-domain: true
num-lanes:
maximum: 2
description: Number of lanes to use for this port.
'#interrupt-cells':
const: 1
interrupt-map-mask:
description: Standard PCI IRQ mapping properties.
interrupt-map:
description: Standard PCI IRQ mapping properties.
max-link-speed:
description: Specify PCI Gen for link capability.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4]
default: 1
bus-range:
description: Range of bus numbers associated with this controller.
reset-assert-ms:
description: |
Delay after asserting reset to the PCIe device.
......@@ -94,9 +71,6 @@ properties:
required:
- compatible
- device_type
- "#address-cells"
- "#size-cells"
- reg
- reg-names
- ranges
......@@ -109,7 +83,7 @@ required:
- interrupt-map
- interrupt-map-mask
additionalProperties: false
unevaluatedProperties: false
examples:
- |
......
Documentation/devicetree/bindings/pci/kirin-pcie.txt 已删除 100644 → 0
浏览文件 @ 6104dde0
HiSilicon Kirin SoCs PCIe host DT description
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Additional properties are described here:
Required properties
- compatible:
"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
- reg: Should contain rc_dbi, apb, phy, config registers location and length.
- reg-names: Must include the following entries:
"dbi": controller configuration registers;
"apb": apb Ctrl register defined by Kirin;
"phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
Optional properties:
Example based on kirin960:
pcie@f4000000 {
compatible = "hisilicon,kirin-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
<0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
reg-names = "dbi","apb","phy", "config";
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
<0x0 0 0 2 &gic 0 0 0 283 4>,
<0x0 0 0 3 &gic 0 0 0 284 4>,
<0x0 0 0 4 &gic 0 0 0 285 4>;
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
clock-names = "pcie_phy_ref", "pcie_aux",
"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
reset-gpios = <&gpio11 1 0 >;
};
Documentation/devicetree/bindings/pci/layerscape-pci.txt
浏览文件 @ 9e5f3ffc
Freescale Layerscape PCIe controller
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.
......
Documentation/devicetree/bindings/pci/loongson.yaml
浏览文件 @ 9e5f3ffc
......@@ -17,10 +17,10 @@ allOf:
properties:
compatible:
oneOf:
- const: loongson,ls2k-pci
- const: loongson,ls7a-pci
- const: loongson,rs780e-pci
enum:
- loongson,ls2k-pci
- loongson,ls7a-pci
- loongson,rs780e-pci
reg:
minItems: 1
......
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
浏览文件 @ 9e5f3ffc
NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
This PCIe controller is based on the Synopsis Designware PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
and thus inherits all the common properties defined in snps,dw-pcie.yaml and
snps,dw-pcie-ep.yaml.
Some of the controller instances are dual mode where in they can work either
in root port mode or endpoint mode but one at a time.
......@@ -22,7 +23,7 @@ Required properties:
property.
- reg-names: Must include the following entries:
"appl": Controller's application logic registers
"config": As per the definition in designware-pcie.txt
"config": As per the definition in snps,dw-pcie.yaml
"atu_dma": iATU and DMA registers. This is where the iATU (internal Address
Translation Unit) registers of the PCIe core are made available
for SW access.
......
Documentation/devicetree/bindings/pci/pci-armada8k.txt
浏览文件 @ 9e5f3ffc
* Marvell Armada 7K/8K PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties:
- compatible: "marvell,armada8k-pcie"
......
Documentation/devicetree/bindings/pci/pcie-al.txt
浏览文件 @ 9e5f3ffc
......@@ -2,7 +2,7 @@
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
PCI core. It inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Properties of the host controller node that differ from it are:
......
Documentation/devicetree/bindings/pci/qcom,pcie.txt
浏览文件 @ 9e5f3ffc
......@@ -34,22 +34,22 @@
- device_type:
Usage: required
Value type: <string>
Definition: Should be "pci". As specified in designware-pcie.txt
Definition: Should be "pci". As specified in snps,dw-pcie.yaml
- #address-cells:
Usage: required
Value type: <u32>
Definition: Should be 3. As specified in designware-pcie.txt
Definition: Should be 3. As specified in snps,dw-pcie.yaml
- #size-cells:
Usage: required
Value type: <u32>
Definition: Should be 2. As specified in designware-pcie.txt
Definition: Should be 2. As specified in snps,dw-pcie.yaml
- ranges:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt
Definition: As specified in snps,dw-pcie.yaml
- interrupts:
Usage: required
......@@ -64,17 +64,17 @@
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: Should be 1. As specified in designware-pcie.txt
Definition: Should be 1. As specified in snps,dw-pcie.yaml
- interrupt-map-mask:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt
Definition: As specified in snps,dw-pcie.yaml
- interrupt-map:
Usage: required
Value type: <prop-encoded-array>
Definition: As specified in designware-pcie.txt
Definition: As specified in snps,dw-pcie.yaml
- clocks:
Usage: required
......
Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
浏览文件 @ 9e5f3ffc
......@@ -13,10 +13,10 @@ maintainers:
description: |+
Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
designware-pcie.txt.
snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
浏览文件 @ 9e5f3ffc
......@@ -10,14 +10,14 @@ description: |+
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
- Greentime Hu <greentime.hu@sifive.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare PCIe endpoint interface
maintainers:
- Jingoo Han <jingoohan1@gmail.com>
- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
description: |
Synopsys DesignWare PCIe host controller endpoint
allOf:
- $ref: /schemas/pci/pci-ep.yaml#
properties:
compatible:
anyOf:
- {}
- const: snps,dw-pcie-ep
reg:
description: |
It should contain Data Bus Interface (dbi) and config registers for all
versions.
For designware core version >= 4.80, it may contain ATU address space.
minItems: 2
maxItems: 4
reg-names:
minItems: 2
maxItems: 4
items:
enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
reset-gpio:
description: GPIO pin number of PERST# signal
maxItems: 1
deprecated: true
reset-gpios:
description: GPIO controlled connection to PERST# signal
maxItems: 1
snps,enable-cdm-check:
type: boolean
description: |
This is a boolean property and if present enables
automatic checking of CDM (Configuration Dependent Module) registers
for data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers, DMA and iATU (internal Address
Translation Unit) registers.
num-ib-windows:
description: number of inbound address translation windows
maxItems: 1
deprecated: true
num-ob-windows:
description: number of outbound address translation windows
maxItems: 1
deprecated: true
max-functions:
$ref: /schemas/types.yaml#/definitions/uint32
description: maximum number of functions that can be configured
required:
- reg
- reg-names
- compatible
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <1>;
#size-cells = <1>;
pcie-ep@dfd00000 {
compatible = "snps,dw-pcie-ep";
reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
<0xdfc01000 0x0001000>, /* IP registers 2 */
<0xd0000000 0x2000000>; /* Configuration space */
reg-names = "dbi", "dbi2", "addr_space";
};
};
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml 0 → 100644
浏览文件 @ 9e5f3ffc
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare PCIe interface
maintainers:
- Jingoo Han <jingoohan1@gmail.com>
- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
description: |
Synopsys DesignWare PCIe host controller
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
anyOf:
- {}
- const: snps,dw-pcie
reg:
description: |
It should contain Data Bus Interface (dbi) and config registers for all
versions.
For designware core version >= 4.80, it may contain ATU address space.
minItems: 2
maxItems: 5
reg-names:
minItems: 2
maxItems: 5
items:
enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
ulreg, smu, mpu, apb, phy ]
num-lanes:
description: |
number of lanes to use (this property should be specified unless
the link is brought already up in firmware)
maximum: 16
reset-gpio:
description: GPIO pin number of PERST# signal
maxItems: 1
deprecated: true
reset-gpios:
description: GPIO controlled connection to PERST# signal
maxItems: 1
interrupts: true
interrupt-names: true
clocks: true
snps,enable-cdm-check:
type: boolean
description: |
This is a boolean property and if present enables
automatic checking of CDM (Configuration Dependent Module) registers
for data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers, DMA and iATU (internal Address
Translation Unit) registers.
num-viewport:
description: |
number of view ports configured in hardware. If a platform
does not specify it, the driver autodetects it.
deprecated: true
unevaluatedProperties: false
required:
- reg
- reg-names
- compatible
examples:
- |
bus {
#address-cells = <1>;
#size-cells = <1>;
pcie@dfc00000 {
device_type = "pci";
compatible = "snps,dw-pcie";
reg = <0xdfc00000 0x0001000>, /* IP registers */
<0xd0000000 0x0002000>; /* Configuration space */
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
<0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
interrupts = <25>, <24>;
#interrupt-cells = <1>;
num-lanes = <1>;
};
};
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
浏览文件 @ 9e5f3ffc
......@@ -10,13 +10,13 @@ description: |
UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- $ref: "pci-ep.yaml#"
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/ti-pci.txt
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......@@ -12,7 +12,7 @@ PCIe DesignWare Controller
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
- num-lanes as specified in ../designware-pcie.txt
- num-lanes as specified in ../snps,dw-pcie.yaml
- ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
module and the register offset to specify lane
selection.
......@@ -32,7 +32,7 @@ HOST MODE
device_type,
ranges,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
interrupt-map : as specified in ../snps,dw-pcie.yaml
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
should contain the register offset within syscon
and the 2nd argument should contain the bit field
......
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