PCI: Add MCFG quirks for some Hisilicon Chip host controllers

euler inclusion
category: bugfix
bugzilla: 46851
CVE: NA

-------------------------------------------------

The PCIe controller in some Hisilicon Chip is not completely ECAM-compliant.
Part of its PCIe cores do not support ECAM.
Signed-off-by: NXiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Nyangerkun <yangerkun@huawei.com>
Acked-by: NXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: NChen Jun <chenjun102@huawei.com>

drivers/acpi/pci_mcfg.c

@@ -77,6 +77,10 @@ static struct mcfg_fixup mcfg_quirks[] = {
 	HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),
 	HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),
 	HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),
+	HISI_QUAD_DOM("HIP12   ", 0x20, &hisi_pcie_ops),
+	HISI_QUAD_DOM("HIP12   ", 0x24, &hisi_pcie_ops),
+	HISI_QUAD_DOM("HIP12   ", 0x28, &hisi_pcie_ops),
+	HISI_QUAD_DOM("HIP12   ", 0x2c, &hisi_pcie_ops),
 
 #define THUNDER_PEM_RES(addr, node) \
 	DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)