vc4_hdmi: Adjust CEC ref clock based on its input clock

raspberrypi inclusion
category: feature
bugzilla: 50432

--------------------------------

2711 uses a fixed 27MHz input, earlier models use the HSM clock
Signed-off-by: NDom Cobley <popcornmix@gmail.com>
Signed-off-by: NFang Yafen <yafen@iscas.ac.cn>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>

drivers/gpu/drm/vc4/vc4_hdmi.c

@@ -80,8 +80,12 @@
 # define VC4_HD_M_ENABLE			BIT(0)
 
 #define CEC_CLOCK_FREQ 40000
+/* Threshold for adjusting the BVB clock */
 #define VC4_HSM_MID_CLOCK 149985000
 
+/* Fixed HVS4 HSM clock rate */
+#define VC4_HSM_CLOCK 163682864
+
 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = (struct drm_info_node *)m->private;
@@ -812,8 +816,7 @@ static u32 vc4_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixe
 	 * clock, so make it constant to avoid having to reconfigure CEC on
 	 * every mode change.
 	 */
-
-	return 163682864;
+	return VC4_HSM_CLOCK;
 }
 
 static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
@@ -1470,6 +1473,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
 	struct cec_connector_info conn_info;
 	struct platform_device *pdev = vc4_hdmi->pdev;
 	u32 value;
+	u32 clk_cnt;
 	int ret;
 
 	if (!vc4_hdmi->variant->cec_available)
@@ -1494,8 +1498,9 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
 	 * divider: the hsm_clock rate and this divider setting will
 	 * give a 40 kHz CEC clock.
 	 */
+	clk_cnt = vc4_hdmi->variant->cec_input_clock / CEC_CLOCK_FREQ;
 	value |= VC4_HDMI_CEC_ADDR_MASK |
-		 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+		 ((clk_cnt - 1) << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
 	HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 	ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
 					vc4_cec_irq_handler,
@@ -1871,6 +1876,7 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
 	.debugfs_name		= "hdmi_regs",
 	.card_name		= "vc4-hdmi",
 	.max_pixel_clock	= 162000000,
+	.cec_input_clock	= VC4_HSM_CLOCK,
 	.cec_available		= true,
 	.registers		= vc4_hdmi_fields,
 	.num_registers		= ARRAY_SIZE(vc4_hdmi_fields),
@@ -1894,6 +1900,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
 	.debugfs_name		= "hdmi0_regs",
 	.card_name		= "vc4-hdmi-0",
 	.max_pixel_clock	= 297000000,
+	.cec_input_clock	= 27000000,
 	.registers		= vc5_hdmi_hdmi0_fields,
 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
 	.phy_lane_mapping	= {
@@ -1923,6 +1930,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
 	.debugfs_name		= "hdmi1_regs",
 	.card_name		= "vc4-hdmi-1",
 	.max_pixel_clock	= 297000000,
+	.cec_input_clock	= 27000000,
 	.registers		= vc5_hdmi_hdmi1_fields,
 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
 	.phy_lane_mapping	= {

drivers/gpu/drm/vc4/vc4_hdmi.h

@@ -49,6 +49,9 @@ struct vc4_hdmi_variant {
 	/* Maximum pixel clock supported by the controller (in Hz) */
 	unsigned long long max_pixel_clock;
 
+	/* Input clock frequency of CEC block (in Hz) */
+	unsigned long cec_input_clock;
+
 	/* List of the registers available on that variant */
 	const struct vc4_hdmi_register *registers;