mailbox: add control_by_sw for mt8195

To make sure the GCE request signal to SPM is not trigger by
other HW modules and cause suspend premature wake.

Set 0x7 (the bit 0~2 as 1) to GCE_GCTL_VALUE, to configure the
request signal control by SW and release the request to SPM.
Signed-off-by: Njason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: NTzung-Bi Shih <tzungbi@google.com>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

drivers/mailbox/mtk-cmdq-mailbox.c

@@ -666,7 +666,7 @@ static const struct gce_plat gce_plat_v5 = {
 static const struct gce_plat gce_plat_v6 = {
 	.thread_nr = 24,
 	.shift = 3,
-	.control_by_sw = false,
+	.control_by_sw = true,
 	.gce_num = 2
 };