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提交 915ec1e2 编写于 作者: R Ralf Baechle
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MIPS: atomic_*(): Change type of intermediate variables. 

This shaves of 1912 bytes of an IP27 defconfig kernel and avoids
unexpected overflow behaviour in atomic_sub_if_positive.  Apply the same
changes to the atomic64_* functions for consistency.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 c7c1e384
隐藏空白更改
内联 并排
Showing with 26 addition and 26 deletion
arch/mips/include/asm/atomic.h
浏览文件 @ 915ec1e2
......@@ -50,7 +50,7 @@
static __inline__ void atomic_add(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -95,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
static __inline__ void atomic_sub(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -107,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -135,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
*/
static __inline__ int atomic_add_return(int i, atomic_t * v)
{
unsigned long result;
int result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -154,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -187,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
static __inline__ int atomic_sub_return(int i, atomic_t * v)
{
unsigned long result;
int result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -247,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
*/
static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
{
unsigned long result;
int result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -270,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
int temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -429,7 +429,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
static __inline__ void atomic64_add(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -441,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -474,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
static __inline__ void atomic64_sub(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -486,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -514,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
*/
static __inline__ long atomic64_add_return(long i, atomic64_t * v)
{
unsigned long result;
long result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -533,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -566,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
{
unsigned long result;
long result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -585,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -626,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
*/
static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
{
unsigned long result;
long result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......@@ -649,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
long temp;
__asm__ __volatile__(
" .set mips3 \n"
......
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