drm/i915: add LCPLL control registers

Those are used to control the display core clock.

v2: change the enable bit setting, spotted by Rodrigo Vivi.
Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/i915_reg.h

@@ -4180,4 +4180,11 @@
 #define  PIPE_CLK_SEL_DISABLED	(0x0<<29)
 #define  PIPE_CLK_SEL_PORT(x)	((x+1)<<29)
 
+/* LCPLL Control */
+#define LCPLL_CTL				0x130040
+#define  LCPLL_PLL_DISABLE		(1<<31)
+#define  LCPLL_PLL_LOCK			(1<<30)
+#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
+#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
+
 #endif /* _I915_REG_H_ */