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909aa10e
编写于
6月 19, 2015
作者:
M
Michael Turquette
浏览文件
操作
浏览文件
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差异文件
Merge branch 'ccf/atmel-fixes-for-4.1' of
https://github.com/bbrezillon/linux-at91
into clk-fixes
上级
0f57d867
28df9c2f
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
16 addition
and
8 deletion
+16
-8
Documentation/devicetree/bindings/clock/at91-clock.txt
Documentation/devicetree/bindings/clock/at91-clock.txt
+1
-1
drivers/clk/at91/clk-peripheral.c
drivers/clk/at91/clk-peripheral.c
+4
-4
drivers/clk/at91/clk-pll.c
drivers/clk/at91/clk-pll.c
+10
-2
drivers/clk/at91/pmc.h
drivers/clk/at91/pmc.h
+1
-1
未找到文件。
Documentation/devicetree/bindings/clock/at91-clock.txt
浏览文件 @
909aa10e
...
...
@@ -248,7 +248,7 @@ Required properties for peripheral clocks:
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the master clock phandle.
e.g. clocks = <&mck>;
- name: device tree node describing a specific
system
clock.
- name: device tree node describing a specific
peripheral
clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg: peripheral id. See Atmel's datasheets to get a full
list of peripheral ids.
...
...
drivers/clk/at91/clk-peripheral.c
浏览文件 @
909aa10e
...
...
@@ -29,7 +29,7 @@
#define PERIPHERAL_RSHIFT_MASK 0x3
#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
#define PERIPHERAL_MAX_SHIFT
4
#define PERIPHERAL_MAX_SHIFT
3
struct
clk_peripheral
{
struct
clk_hw
hw
;
...
...
@@ -242,7 +242,7 @@ static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
return
*
parent_rate
;
if
(
periph
->
range
.
max
)
{
for
(;
shift
<
PERIPHERAL_MAX_SHIFT
;
shift
++
)
{
for
(;
shift
<
=
PERIPHERAL_MAX_SHIFT
;
shift
++
)
{
cur_rate
=
*
parent_rate
>>
shift
;
if
(
cur_rate
<=
periph
->
range
.
max
)
break
;
...
...
@@ -254,7 +254,7 @@ static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
best_diff
=
cur_rate
-
rate
;
best_rate
=
cur_rate
;
for
(;
shift
<
PERIPHERAL_MAX_SHIFT
;
shift
++
)
{
for
(;
shift
<
=
PERIPHERAL_MAX_SHIFT
;
shift
++
)
{
cur_rate
=
*
parent_rate
>>
shift
;
if
(
cur_rate
<
rate
)
cur_diff
=
rate
-
cur_rate
;
...
...
@@ -289,7 +289,7 @@ static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
if
(
periph
->
range
.
max
&&
rate
>
periph
->
range
.
max
)
return
-
EINVAL
;
for
(
shift
=
0
;
shift
<
PERIPHERAL_MAX_SHIFT
;
shift
++
)
{
for
(
shift
=
0
;
shift
<
=
PERIPHERAL_MAX_SHIFT
;
shift
++
)
{
if
(
parent_rate
>>
shift
==
rate
)
{
periph
->
auto_div
=
false
;
periph
->
div
=
shift
;
...
...
drivers/clk/at91/clk-pll.c
浏览文件 @
909aa10e
...
...
@@ -173,8 +173,7 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
int
i
=
0
;
/* Check if parent_rate is a valid input rate */
if
(
parent_rate
<
characteristics
->
input
.
min
||
parent_rate
>
characteristics
->
input
.
max
)
if
(
parent_rate
<
characteristics
->
input
.
min
)
return
-
ERANGE
;
/*
...
...
@@ -187,6 +186,15 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
if
(
!
mindiv
)
mindiv
=
1
;
if
(
parent_rate
>
characteristics
->
input
.
max
)
{
tmpdiv
=
DIV_ROUND_UP
(
parent_rate
,
characteristics
->
input
.
max
);
if
(
tmpdiv
>
PLL_DIV_MAX
)
return
-
ERANGE
;
if
(
tmpdiv
>
mindiv
)
mindiv
=
tmpdiv
;
}
/*
* Calculate the maximum divider which is limited by PLL register
* layout (limited by the MUL or DIV field size).
...
...
drivers/clk/at91/pmc.h
浏览文件 @
909aa10e
...
...
@@ -121,7 +121,7 @@ extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
struct
at91_pmc
*
pmc
);
#endif
#if defined(CONFIG_HAVE_AT91_
SMD
)
#if defined(CONFIG_HAVE_AT91_
H32MX
)
extern
void
__init
of_sama5d4_clk_h32mx_setup
(
struct
device_node
*
np
,
struct
at91_pmc
*
pmc
);
#endif
...
...
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