LoongArch: kvm: add initial kvm support

LoongArch inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6BWFP

--------------------------------

add initial kvm support.
Signed-off-by: Nqemudev <qemudev@loongson.cn>
Change-Id: I1f6d361dd54299d97748a360686171e2c34a203c

arch/loongarch/Kbuild

 obj-y += kernel/
 obj-y += mm/
 obj-y += vdso/
+obj-$(CONFIG_KVM)	+= kvm/
 
 # for cleaning
 subdir- += boot

arch/loongarch/Kconfig

@@ -106,6 +106,7 @@ config LOONGARCH
 	select HAVE_SETUP_PER_CPU_AREA if NUMA
 	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_TIF_NOHZ
+	select HAVE_KVM
 	select HAVE_VIRT_CPU_ACCOUNTING_GEN if !SMP
 	select IRQ_FORCED_THREADING
 	select IRQ_LOONGARCH_CPU
@@ -539,3 +540,4 @@ source "drivers/cpufreq/Kconfig"
 endmenu
 
 source "drivers/firmware/Kconfig"
+source "arch/loongarch/kvm/Kconfig"

arch/loongarch/include/asm/kvm_host.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef __LOONGARCH_KVM_HOST_H__
+#define __LOONGARCH_KVM_HOST_H__
+
+#include <linux/cpumask.h>
+#include <linux/mutex.h>
+#include <linux/hrtimer.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/kvm.h>
+#include <linux/kvm_types.h>
+#include <linux/threads.h>
+#include <linux/spinlock.h>
+#include <asm/inst.h>
+
+/* Loongarch KVM register ids */
+#define LOONGARCH_CSR_32(_R, _S)					\
+	(KVM_REG_LOONGARCH_CSR | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
+
+#define LOONGARCH_CSR_64(_R, _S)					\
+	(KVM_REG_LOONGARCH_CSR | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
+
+#define KVM_IOC_CSRID(id)	LOONGARCH_CSR_64(id, 0)
+#define KVM_GET_IOC_CSRIDX(id)	((id & KVM_CSR_IDX_MASK) >> 3)
+
+#define LOONGSON_VIRT_REG_BASE	0x1f000000
+#define KVM_MAX_VCPUS		256
+#define KVM_USER_MEM_SLOTS	256
+/* memory slots that does not exposed to userspace */
+#define KVM_PRIVATE_MEM_SLOTS	0
+
+#define KVM_HALT_POLL_NS_DEFAULT 500000
+
+#define KVM_REQ_RECORD_STEAL	KVM_ARCH_REQ(1)
+#define KVM_INVALID_ADDR		0xdeadbeef
+#define KVM_HVA_ERR_BAD			(-1UL)
+#define KVM_HVA_ERR_RO_BAD		(-2UL)
+static inline bool kvm_is_error_hva(unsigned long addr)
+{
+	return IS_ERR_VALUE(addr);
+}
+
+struct kvm_vm_stat {
+	ulong remote_tlb_flush;
+	u64 vm_ioctl_irq_line;
+	u64 ls7a_ioapic_update;
+	u64 ls7a_ioapic_set_irq;
+	u64 ioapic_reg_write;
+	u64 ioapic_reg_read;
+	u64 set_ls7a_ioapic;
+	u64 get_ls7a_ioapic;
+	u64 set_ls3a_ext_irq;
+	u64 get_ls3a_ext_irq;
+	u64 trigger_ls3a_ext_irq;
+	u64 pip_read_exits;
+	u64 pip_write_exits;
+	u64 ls7a_msi_irq;
+};
+struct kvm_vcpu_stat {
+	u64 excep_exits[EXCCODE_INT_START];
+	u64 idle_exits;
+	u64 signal_exits;
+	u64 int_exits;
+	u64 rdcsr_cpu_feature_exits;
+	u64 rdcsr_misc_func_exits;
+	u64 rdcsr_ipi_access_exits;
+	u64 cpucfg_exits;
+	u64 huge_dec_exits;
+	u64 huge_thp_exits;
+	u64 huge_adjust_exits;
+	u64 huge_set_exits;
+	u64 huge_merge_exits;
+	u64 halt_successful_poll;
+	u64 halt_attempted_poll;
+	u64 halt_poll_invalid;
+	u64 halt_wakeup;
+};
+
+#define KVM_MEMSLOT_DISABLE_THP		(1UL << 17)
+struct kvm_arch_memory_slot {
+	unsigned int flags;
+};
+
+enum {
+	IOCSR_FEATURES,
+	IOCSR_VENDOR,
+	IOCSR_CPUNAME,
+	IOCSR_NODECNT,
+	IOCSR_MISC_FUNC,
+	IOCSR_MAX
+};
+
+struct kvm_context {
+	unsigned long gid_mask;
+	unsigned long gid_ver_mask;
+	unsigned long gid_fisrt_ver;
+	unsigned long vpid_cache;
+	struct kvm_vcpu *last_vcpu;
+};
+
+struct kvm_arch {
+	/* Guest physical mm */
+	struct mm_struct gpa_mm;
+	/* Mask of CPUs needing GPA ASID flush */
+	cpumask_t asid_flush_mask;
+
+	unsigned char online_vcpus;
+	unsigned char is_migrate;
+	s64 stablecounter_gftoffset;
+	u32 cpucfg_lasx;
+	struct ls7a_kvm_ioapic *v_ioapic;
+	struct ls3a_kvm_ipi *v_gipi;
+	struct ls3a_kvm_routerirq *v_routerirq;
+	struct ls3a_kvm_extirq *v_extirq;
+	spinlock_t iocsr_lock;
+	struct kvm_iocsr_entry iocsr[IOCSR_MAX];
+	struct kvm_cpucfg cpucfgs;
+	struct kvm_context __percpu *vmcs;
+};
+
+
+#define LOONGARCH_CSRS	0x100
+#define CSR_UCWIN_BASE	0x100
+#define CSR_UCWIN_SIZE	0x10
+#define CSR_DMWIN_BASE	0x180
+#define CSR_DMWIN_SIZE	0x4
+#define CSR_PERF_BASE	0x200
+#define CSR_PERF_SIZE	0x8
+#define CSR_DEBUG_BASE	0x500
+#define CSR_DEBUG_SIZE	0x3
+#define CSR_ALL_SIZE	0x800
+
+struct loongarch_csrs {
+	unsigned long csrs[CSR_ALL_SIZE];
+};
+
+/* Resume Flags */
+#define RESUME_FLAG_DR		(1<<0)	/* Reload guest nonvolatile state? */
+#define RESUME_FLAG_HOST	(1<<1)	/* Resume host? */
+
+#define RESUME_GUEST		0
+#define RESUME_GUEST_DR		RESUME_FLAG_DR
+#define RESUME_HOST		RESUME_FLAG_HOST
+
+enum emulation_result {
+	EMULATE_DONE,		/* no further processing */
+	EMULATE_DO_MMIO,	/* kvm_run filled with MMIO request */
+	EMULATE_FAIL,		/* can't emulate this instruction */
+	EMULATE_WAIT,		/* WAIT instruction */
+	EMULATE_PRIV_FAIL,
+	EMULATE_EXCEPT,		/* A guest exception has been generated */
+	EMULATE_PV_HYPERCALL,	/* HYPCALL instruction */
+	EMULATE_DEBUG,		/* Emulate guest kernel debug */
+	EMULATE_DO_IOCSR,	/* handle IOCSR request */
+};
+
+#define KVM_NR_MEM_OBJS     4
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+	int nobjs;
+	void *objects[KVM_NR_MEM_OBJS];
+};
+
+#if defined(CONFIG_CPU_HAS_LASX)
+#define FPU_ALIGN		__aligned(32)
+#elif defined(CONFIG_CPU_HAS_LSX)
+#define FPU_ALIGN		__aligned(16)
+#else
+#define FPU_ALIGN
+#endif
+#define KVM_LARCH_FPU		(0x1 << 0)
+#define KVM_LARCH_LSX		(0x1 << 1)
+#define KVM_LARCH_LASX		(0x1 << 2)
+#define KVM_LARCH_DATA_HWBP	(0x1 << 3)
+#define KVM_LARCH_INST_HWBP	(0x1 << 4)
+#define KVM_LARCH_HWBP		(KVM_LARCH_DATA_HWBP | KVM_LARCH_INST_HWBP)
+#define KVM_LARCH_RESET		(0x1 << 5)
+#define KVM_LARCH_PERF		(0x1 << 6)
+
+struct kvm_vcpu_arch {
+	unsigned long guest_eentry;
+	unsigned long host_eentry;
+	int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
+	int (*handle_exit)(struct kvm_run *run, struct kvm_vcpu *vcpu);
+
+	/* Host registers preserved across guest mode execution */
+	unsigned long host_stack;
+	unsigned long host_gp;
+	unsigned long host_pgd;
+	unsigned long host_pgdhi;
+	unsigned long host_entryhi;
+
+	/* Host CSR registers used when handling exits from guest */
+	unsigned long badv;
+	unsigned long host_estat;
+	unsigned long badi;
+	unsigned long host_ecfg;
+	unsigned long host_percpu;
+
+	u32 is_hypcall;
+	/* GPRS */
+	unsigned long gprs[32];
+	unsigned long pc;
+
+	/* FPU State */
+	struct loongarch_fpu fpu FPU_ALIGN;
+	/* Which auxiliary state is loaded (KVM_LOONGARCH_AUX_*) */
+	unsigned int aux_inuse;
+
+	/* CSR State */
+	struct loongarch_csrs *csr;
+
+	/* GPR used as IO source/target */
+	u32 io_gpr;
+
+	struct hrtimer swtimer;
+	/* Count timer control KVM register */
+	u32 count_ctl;
+
+	/* Bitmask of exceptions that are pending */
+	unsigned long irq_pending;
+	/* Bitmask of pending exceptions to be cleared */
+	unsigned long irq_clear;
+
+	/* Cache some mmu pages needed inside spinlock regions */
+	struct kvm_mmu_memory_cache mmu_page_cache;
+
+	/* vcpu's vpid is different on each host cpu in an smp system */
+	u64 vpid[NR_CPUS];
+
+	/* Period of stable timer tick in ns */
+	u64 timer_period;
+	/* Frequency of stable timer in Hz */
+	u64 timer_mhz;
+	/* Stable bias from the raw time */
+	u64 timer_bias;
+	/* Dynamic nanosecond bias (multiple of timer_period) to avoid overflow */
+	s64 timer_dyn_bias;
+	/* Save ktime */
+	ktime_t stable_ktime_saved;
+
+	u64 core_ext_ioisr[4];
+
+	/* Last CPU the VCPU state was loaded on */
+	int last_sched_cpu;
+	/* Last CPU the VCPU actually executed guest code on */
+	int last_exec_cpu;
+
+	u8 fpu_enabled;
+	u8 lsx_enabled;
+	/* paravirt steal time */
+	struct {
+		u64 guest_addr;
+		u64 last_steal;
+		struct gfn_to_pfn_cache cache;
+	} st;
+	struct kvm_guest_debug_arch guest_debug;
+	/* save host pmu csr */
+	u64 perf_ctrl[4];
+	u64 perf_cntr[4];
+
+};
+
+static inline unsigned long readl_sw_gcsr(struct loongarch_csrs *csr, int reg)
+{
+	return csr->csrs[reg];
+}
+
+static inline void writel_sw_gcsr(struct loongarch_csrs *csr, int reg, \
+		unsigned long val)
+{
+	csr->csrs[reg] = val;
+}
+
+/* Helpers */
+static inline bool _kvm_guest_has_fpu(struct kvm_vcpu_arch *arch)
+{
+	return cpu_has_fpu && arch->fpu_enabled;
+}
+
+
+static inline bool _kvm_guest_has_lsx(struct kvm_vcpu_arch *arch)
+{
+	return cpu_has_lsx && arch->lsx_enabled;
+}
+
+bool _kvm_guest_has_lasx(struct kvm_vcpu *vcpu);
+void _kvm_init_fault(void);
+
+/* Debug: dump vcpu state */
+int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
+
+/* MMU handling */
+int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long badv, bool write);
+void kvm_flush_tlb_all(void);
+void _kvm_destroy_mm(struct kvm *kvm);
+pgd_t *kvm_pgd_alloc(void);
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+
+enum _kvm_fault_result {
+	KVM_LOONGARCH_MAPPED = 0,
+	KVM_LOONGARCH_GVA,
+	KVM_LOONGARCH_GPA,
+	KVM_LOONGARCH_TLB,
+	KVM_LOONGARCH_TLBINV,
+	KVM_LOONGARCH_TLBMOD,
+};
+
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+int kvm_unmap_hva_range(struct kvm *kvm,
+			unsigned long start, unsigned long end, bool blockable);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
+int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
+
+static inline void update_pc(struct kvm_vcpu_arch *arch)
+{
+	arch->pc += 4;
+}
+
+/**
+ * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
+ * @vcpu:	Virtual CPU.
+ *
+ * Returns:	Whether the TLBL exception was likely due to an instruction
+ *		fetch fault rather than a data load fault.
+ */
+static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *arch)
+{
+	if (arch->pc == arch->badv)
+		return true;
+
+	return false;
+}
+
+/* Misc */
+static inline void kvm_arch_hardware_unsetup(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_free_memslot(struct kvm *kvm,
+		struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
+static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
+
+extern int kvm_enter_guest(struct kvm_run *run, struct kvm_vcpu *vcpu);
+extern void kvm_exception_entry(void);
+#endif /* __LOONGARCH_KVM_HOST_H__ */

arch/loongarch/include/asm/kvm_types.h

+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_LOONGARCH64_KVM_TYPES_H
+#define _ASM_LOONGARCH64_KVM_TYPES_H
+
+#define KVM_ARCH_NR_OBJS_PER_MEMORY_CACHE 4
+
+#endif /* _ASM_LOONGARCH64_KVM_TYPES_H */
+

arch/loongarch/include/uapi/asm/kvm.h

+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2020  Loongson Technologies, Inc.  All rights reserved.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ * Authors: Xing Li <lixing@loongson.cn>
+ */
+
+#ifndef __LINUX_KVM_LOONGARCH_H
+#define __LINUX_KVM_LOONGARCH_H
+
+#include <linux/types.h>
+#ifndef __KERNEL__
+#include <stdint.h>
+#endif
+
+#define __KVM_HAVE_GUEST_DEBUG
+#define KVM_GUESTDBG_USE_SW_BP 0x00010000
+#define KVM_GUESTDBG_USE_HW_BP 0x00020000
+#define KVM_DATA_HW_BREAKPOINT_NUM 8
+#define KVM_INST_HW_BREAKPOINT_NUM 8
+
+/*
+ * KVM Loongarch specific structures and definitions.
+ *
+ * Some parts derived from the x86 version of this file.
+ */
+
+#define __KVM_HAVE_READONLY_MEM
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+/*
+ * for KVM_GET_REGS and KVM_SET_REGS
+ */
+struct kvm_regs {
+	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
+	__u64 gpr[32];
+	__u64 pc;
+};
+
+/*
+ * for KVM_GET_CPUCFG
+ */
+struct kvm_cpucfg {
+	/* out (KVM_GET_CPUCFG) */
+	__u32 cpucfg[64];
+};
+
+/*
+ * for KVM_GET_FPU and KVM_SET_FPU
+ */
+struct kvm_fpu {
+	__u32 fcsr;
+	__u32 none;
+	__u64 fcc;    /* 8x8 */
+	struct kvm_fpureg {
+		__u64 val64[4];	//support max 256 bits
+	} fpr[32];
+};
+
+/*
+ * For LOONGARCH, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
+ * registers.  The id field is broken down as follows:
+ *
+ *  bits[63..52] - As per linux/kvm.h
+ *  bits[51..32] - Must be zero.
+ *  bits[31..16] - Register set.
+ *
+ * Register set = 0: GP registers from kvm_regs (see definitions below).
+ *
+ * Register set = 1: CSR registers.
+ *
+ * Register set = 2: KVM specific registers (see definitions below).
+ *
+ * Register set = 3: FPU / SIMD registers (see definitions below).
+ *
+ * Other sets registers may be added in the future.  Each set would
+ * have its own identifier in bits[31..16].
+ */
+
+#define KVM_REG_LOONGARCH_GP		(KVM_REG_LOONGARCH | 0x00000ULL)
+#define KVM_REG_LOONGARCH_CSR		(KVM_REG_LOONGARCH | 0x10000ULL)
+#define KVM_REG_LOONGARCH_KVM		(KVM_REG_LOONGARCH | 0x20000ULL)
+#define KVM_REG_LOONGARCH_FPU		(KVM_REG_LOONGARCH | 0x30000ULL)
+#define KVM_REG_LOONGARCH_MASK		(KVM_REG_LOONGARCH | 0x30000ULL)
+#define KVM_CSR_IDX_MASK		(0x10000 - 1)
+
+/*
+ * KVM_REG_LOONGARCH_KVM - KVM specific control registers.
+ */
+
+#define KVM_REG_LOONGARCH_COUNTER	(KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 3)
+#define KVM_REG_LOONGARCH_VCPU_RESET	(KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 4)
+
+#define __KVM_HAVE_IRQ_LINE
+
+struct kvm_debug_exit_arch {
+	__u64 era;
+	__u32 fwps;
+	__u32 mwps;
+	__u32 exception;
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct hw_breakpoint {
+    __u64 addr;
+    __u64 mask;
+    __u32 asid;
+    __u32 ctrl;
+};
+
+struct kvm_guest_debug_arch {
+	struct hw_breakpoint data_breakpoint[KVM_DATA_HW_BREAKPOINT_NUM];
+	struct hw_breakpoint inst_breakpoint[KVM_INST_HW_BREAKPOINT_NUM];
+	int inst_bp_nums, data_bp_nums;
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* dummy definition */
+struct kvm_sregs {
+};
+
+struct kvm_iocsr_entry {
+	__u32 addr;
+	__u32 pad;
+	__u64 data;
+};
+
+struct kvm_csr_entry {
+	__u32 index;
+	__u32 reserved;
+	__u64 data;
+};
+
+/* for KVM_GET_MSRS and KVM_SET_MSRS */
+struct kvm_msrs {
+	__u32 ncsrs; /* number of msrs in entries */
+	__u32 pad;
+
+	struct kvm_csr_entry entries[0];
+};
+
+struct kvm_loongarch_interrupt {
+	/* in */
+	__u32 cpu;
+	__u32 irq;
+};
+
+#define KVM_IRQCHIP_LS7A_IOAPIC	0x0
+#define KVM_IRQCHIP_LS3A_GIPI	0x1
+#define KVM_IRQCHIP_LS3A_HT_IRQ	0x2
+#define KVM_IRQCHIP_LS3A_ROUTE	0x3
+#define KVM_IRQCHIP_LS3A_EXTIRQ	0x4
+#define KVM_IRQCHIP_LS3A_IPMASK	0x5
+#define KVM_NR_IRQCHIPS          1
+#define KVM_IRQCHIP_NUM_PINS    64
+
+#define KVM_MAX_CORES			256
+#define KVM_EXTIOI_IRQS			(256)
+#define KVM_EXTIOI_IRQS_BITMAP_SIZE	(KVM_EXTIOI_IRQS / 8)
+/* map to ipnum per 32 irqs */
+#define KVM_EXTIOI_IRQS_IPMAP_SIZE	(KVM_EXTIOI_IRQS / 32)
+#define KVM_EXTIOI_IRQS_PER_GROUP	32
+#define KVM_EXTIOI_IRQS_COREMAP_SIZE	(KVM_EXTIOI_IRQS)
+#define KVM_EXTIOI_IRQS_NODETYPE_SIZE	16
+
+struct ls7a_ioapic_state {
+	/* 0x000 interrupt id register */
+	__u64 int_id;
+	/* 0x020 interrupt mask register */
+	__u64 int_mask;
+	/* 0x040 1=msi */
+	__u64 htmsi_en;
+	/* 0x060 edge=1 level  =0 */
+	__u64 intedge;
+	/* 0x080 for clean edge int,set 1 clean,set 0 is noused */
+	__u64 intclr;
+	/* 0x0c0 */
+	__u64 auto_crtl0;
+	/* 0x0e0 */
+	__u64 auto_crtl1;
+	/* 0x100 - 0x140 */
+	__u8 route_entry[64];
+	/* 0x200 - 0x240 */
+	__u8 htmsi_vector[64];
+	/* 0x300 */
+	__u64 intisr_chip0;
+	/* 0x320 */
+	__u64 intisr_chip1;
+	/* edge detection */
+	__u64 last_intirr;
+	/* 0x380 interrupt request register */
+	__u64 intirr;
+	/* 0x3a0 interrupt service register */
+	__u64 intisr;
+	/* 0x3e0 interrupt level polarity selection register,
+	 * 0 for high level tirgger
+	 */
+	__u64 int_polarity;
+};
+
+struct loongarch_gipi_single {
+	__u32 status;
+	__u32 en;
+	__u32 set;
+	__u32 clear;
+	__u64 buf[4];
+};
+
+struct loongarch_gipiState {
+	struct loongarch_gipi_single core[KVM_MAX_CORES];
+};
+
+struct kvm_loongarch_ls3a_extirq_state {
+	union ext_en_r {
+		uint64_t reg_u64[KVM_EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[KVM_EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_EXTIOI_IRQS_BITMAP_SIZE];
+	} ext_en_r;
+	union bounce_r {
+		uint64_t reg_u64[KVM_EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[KVM_EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_EXTIOI_IRQS_BITMAP_SIZE];
+	} bounce_r;
+	union ext_isr_r {
+		uint64_t reg_u64[KVM_EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[KVM_EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_EXTIOI_IRQS_BITMAP_SIZE];
+	} ext_isr_r;
+	union ext_core_isr_r {
+		uint64_t reg_u64[KVM_MAX_CORES][KVM_EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[KVM_MAX_CORES][KVM_EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_MAX_CORES][KVM_EXTIOI_IRQS_BITMAP_SIZE];
+	} ext_core_isr_r;
+	union ip_map_r {
+		uint64_t reg_u64;
+		uint32_t reg_u32[KVM_EXTIOI_IRQS_IPMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_EXTIOI_IRQS_IPMAP_SIZE];
+	} ip_map_r;
+	union core_map_r {
+		uint64_t reg_u64[KVM_EXTIOI_IRQS_COREMAP_SIZE / 8];
+		uint32_t reg_u32[KVM_EXTIOI_IRQS_COREMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_EXTIOI_IRQS_COREMAP_SIZE];
+	} core_map_r;
+	union node_type_r {
+		uint64_t reg_u64[KVM_EXTIOI_IRQS_NODETYPE_SIZE / 4];
+		uint32_t reg_u32[KVM_EXTIOI_IRQS_NODETYPE_SIZE / 2];
+		uint16_t reg_u16[KVM_EXTIOI_IRQS_NODETYPE_SIZE];
+		uint8_t reg_u8[KVM_EXTIOI_IRQS_NODETYPE_SIZE * 2];
+	} node_type_r;
+};
+
+struct loongarch_kvm_irqchip {
+	__u16 chip_id;
+	__u16 len;
+	__u16 vcpu_id;
+	__u16 reserved;
+	char data[0];
+};
+
+#endif /* __LINUX_KVM_LOONGARCH_H */

arch/loongarch/kvm/Kconfig

+# SPDX-License-Identifier: GPL-2.0
+#
+# KVM configuration
+#
+source "virt/kvm/Kconfig"
+
+menuconfig VIRTUALIZATION
+	bool "Virtualization"
+	help
+	  Say Y here to get to see options for using your Linux host to run
+	  other operating systems inside virtual machines (guests).
+	  This option alone does not add any kernel code.
+
+	  If you say N, all options in this submenu will be skipped and disabled.
+
+if VIRTUALIZATION
+
+config KVM
+	tristate "Kernel-based Virtual Machine (KVM) support"
+	depends on HAVE_KVM
+	select EXPORT_UASM
+	select PREEMPT_NOTIFIERS
+	select ANON_INODES
+	select KVM_GENERIC_DIRTYLOG_READ_PROTECT
+	select HAVE_KVM_VCPU_ASYNC_IOCTL
+	select KVM_MMIO
+	select MMU_NOTIFIER
+	select HAVE_KVM_IRQCHIP
+	select HAVE_KVM_IRQFD
+	select HAVE_KVM_IRQ_ROUTING
+	select HAVE_KVM_EVENTFD
+	select HAVE_KVM_MSI
+	select SRCU
+	select KVM_VFIO
+	help
+	  Support for hosting Guest kernels.
+
+choice
+	prompt "Virtualization mode"
+	depends on KVM
+	default KVM_LOONGARCH_LVZ
+
+config KVM_LOONGARCH_LVZ
+	bool "LOONGARCH Virtualization (VZ) ASE"
+	help
+	  Use the LOONGARCH Virtualization (VZ) ASE to virtualize guests. This
+	  supports running unmodified guest kernels, but requires hardware
+	  support.
+
+endchoice
+
+source "drivers/vhost/Kconfig"
+
+endif # VIRTUALIZATION

arch/loongarch/kvm/Makefile

+# SPDX-License-Identifier: GPL-2.0
+# Makefile for KVM support for LoongArch
+#
+
+OBJECT_FILES_NON_STANDARD_entry.o	:= y
+
+common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
+				irqchip.o eventfd.o)
+
+KVM := ../../../virt/kvm
+common-objs-$(CONFIG_KVM_VFIO) += $(KVM)/vfio.o
+
+EXTRA_CFLAGS += -Ivirt/kvm -Iarch/loongarch/kvm
+
+kvm-objs := $(common-objs-y) loongarch.o emulate.o interrupt.o
+kvm-objs += hypcall.o
+kvm-objs += mmu.o
+kvm-objs += kvm_compat.o
+
+kvm-objs		+= exit.o intc/ls7a_irq.o intc/ls3a_ipi.o intc/irqchip-debug.o\
+				timer.o intc/ls3a_ext_irq.o irqfd.o csr.o
+obj-$(CONFIG_KVM)	+= kvm.o
+obj-y			+= entry.o fpu.o

arch/loongarch/kvm/csr.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/inst.h>
+#include <asm/numa.h>
+#include "kvmcpu.h"
+#include "intc/ls3a_ipi.h"
+#include "intc/ls3a_ext_irq.h"
+#include "ls_irq.h"
+#include "kvm_compat.h"
+#include "kvmcsr.h"
+
+#define CASE_READ_SW_GCSR(csr, regid, csrid) \
+	do {                                          \
+		if (regid == csrid) {                     \
+			return kvm_read_sw_gcsr(csr, csrid);  \
+		}                                         \
+	} while (0)
+
+unsigned long _kvm_emu_read_csr(struct kvm_vcpu *vcpu, int csrid)
+{
+	struct loongarch_csrs *csr = vcpu->arch.csr;
+	unsigned long val = 0;
+
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_ERRCTL);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_ERRINFO1);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_ERRINFO2);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRENTRY);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRERA);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_ERRSAVE);
+	/* read sw csr when not config pmu to guest */
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCTRL0);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCTRL1);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCTRL2);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCTRL3);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR0);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR1);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR2);
+	CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR3);
+
+	val = 0;
+	if (csrid < 4096)
+		val = kvm_read_sw_gcsr(csr, csrid);
+	else
+		pr_warn_once("Unsupport csrread 0x%x with pc %lx\n",
+			csrid, vcpu->arch.pc);
+	return val;
+}
+
+#define CASE_WRITE_SW_GCSR(csr, regid, csrid, val) \
+	do {                                                \
+		if (regid == csrid) {                           \
+			kvm_write_sw_gcsr(csr, csrid, val);         \
+			return ;                                    \
+		}                                               \
+	} while (0)
+
+void _kvm_emu_write_csr(struct kvm_vcpu *vcpu, int csrid,
+	unsigned long val)
+{
+	struct loongarch_csrs *csr = vcpu->arch.csr;
+
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_ERRCTL, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_ERRINFO1, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_ERRINFO2, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_MERRENTRY, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_MERRERA, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_ERRSAVE, val);
+
+	/* give pmu register to guest when config perfctrl */
+	CASE_WRITE_HW_PMU(vcpu, csr, csrid, KVM_CSR_PERFCTRL0, val);
+	CASE_WRITE_HW_PMU(vcpu, csr, csrid, KVM_CSR_PERFCTRL1, val);
+	CASE_WRITE_HW_PMU(vcpu, csr, csrid, KVM_CSR_PERFCTRL2, val);
+	CASE_WRITE_HW_PMU(vcpu, csr, csrid, KVM_CSR_PERFCTRL3, val);
+	/* write sw pmu csr if not config ctrl */
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR0, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR1, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR2, val);
+	CASE_WRITE_SW_GCSR(csr, csrid, KVM_CSR_PERFCNTR3, val);
+
+
+	if (csrid < 4096)
+		kvm_write_sw_gcsr(csr, csrid, val);
+	else
+		pr_warn_once("Unsupport csrwrite 0x%x with pc %lx\n",
+				csrid, vcpu->arch.pc);
+}
+
+#define CASE_CHANGE_SW_GCSR(csr, regid, csrid, mask, val) \
+	do {                                                       \
+		if (regid == csrid) {                                  \
+			kvm_change_sw_gcsr(csr, csrid, mask, val);         \
+			return ;                                           \
+		}                                                      \
+	} while (0)
+
+void _kvm_emu_xchg_csr(struct kvm_vcpu *vcpu, int csrid,
+	unsigned long csr_mask, unsigned long val)
+{
+	struct loongarch_csrs *csr = vcpu->arch.csr;
+
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_IMPCTL1, csr_mask, val);
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_ERRCTL, csr_mask, val);
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_ERRINFO1, csr_mask, val);
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_ERRINFO2, csr_mask, val);
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_MERRENTRY, csr_mask, val);
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_MERRERA, csr_mask, val);
+	CASE_CHANGE_SW_GCSR(csr, csrid, KVM_CSR_ERRSAVE, csr_mask, val);
+
+	if (csrid < 4096) {
+		unsigned long orig;
+
+		orig = kvm_read_sw_gcsr(csr, csrid);
+		orig &= ~csr_mask;
+		orig |= val & csr_mask;
+		kvm_write_sw_gcsr(csr, csrid, orig);
+	}
+	pr_warn_once("Unsupport csrxchg 0x%x with pc %lx\n",
+				csrid, vcpu->arch.pc);
+}
+
+int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *v, int force)
+{
+	struct loongarch_csrs *csr = vcpu->arch.csr;
+
+	GET_HW_GCSR(id, KVM_CSR_CRMD, v);
+	GET_HW_GCSR(id, KVM_CSR_PRMD, v);
+	GET_HW_GCSR(id, KVM_CSR_EUEN, v);
+	GET_HW_GCSR(id, KVM_CSR_MISC, v);
+	GET_HW_GCSR(id, KVM_CSR_ECFG, v);
+	GET_HW_GCSR(id, KVM_CSR_ESTAT, v);
+	GET_HW_GCSR(id, KVM_CSR_ERA, v);
+	GET_HW_GCSR(id, KVM_CSR_BADV, v);
+	GET_HW_GCSR(id, KVM_CSR_BADI, v);
+	GET_HW_GCSR(id, KVM_CSR_EENTRY, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBIDX, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBEHI, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBELO0, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBELO1, v);
+	GET_HW_GCSR(id, KVM_CSR_ASID, v);
+	GET_HW_GCSR(id, KVM_CSR_PGDL, v);
+	GET_HW_GCSR(id, KVM_CSR_PGDH, v);
+	GET_HW_GCSR(id, KVM_CSR_PWCTL0, v);
+	GET_HW_GCSR(id, KVM_CSR_PWCTL1, v);
+	GET_HW_GCSR(id, KVM_CSR_STLBPGSIZE, v);
+	GET_HW_GCSR(id, KVM_CSR_RVACFG, v);
+	GET_HW_GCSR(id, KVM_CSR_CPUID, v);
+	GET_HW_GCSR(id, KVM_CSR_PRCFG1, v);
+	GET_HW_GCSR(id, KVM_CSR_PRCFG2, v);
+	GET_HW_GCSR(id, KVM_CSR_PRCFG3, v);
+	GET_HW_GCSR(id, KVM_CSR_KS0, v);
+	GET_HW_GCSR(id, KVM_CSR_KS1, v);
+	GET_HW_GCSR(id, KVM_CSR_KS2, v);
+	GET_HW_GCSR(id, KVM_CSR_KS3, v);
+	GET_HW_GCSR(id, KVM_CSR_KS4, v);
+	GET_HW_GCSR(id, KVM_CSR_KS5, v);
+	GET_HW_GCSR(id, KVM_CSR_KS6, v);
+	GET_HW_GCSR(id, KVM_CSR_KS7, v);
+	GET_HW_GCSR(id, KVM_CSR_TMID, v);
+	GET_HW_GCSR(id, KVM_CSR_TCFG, v);
+	GET_HW_GCSR(id, KVM_CSR_TVAL, v);
+	GET_HW_GCSR(id, KVM_CSR_CNTC, v);
+	GET_HW_GCSR(id, KVM_CSR_LLBCTL, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRENTRY, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRBADV, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRERA, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRSAVE, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRELO0, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRELO1, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBREHI, v);
+	GET_HW_GCSR(id, KVM_CSR_TLBRPRMD, v);
+	GET_HW_GCSR(id, KVM_CSR_DMWIN0, v);
+	GET_HW_GCSR(id, KVM_CSR_DMWIN1, v);
+	GET_HW_GCSR(id, KVM_CSR_DMWIN2, v);
+	GET_HW_GCSR(id, KVM_CSR_DMWIN3, v);
+	GET_HW_GCSR(id, KVM_CSR_MWPS, v);
+	GET_HW_GCSR(id, KVM_CSR_FWPS, v);
+
+	GET_SW_GCSR(csr, id, KVM_CSR_IMPCTL1, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_IMPCTL2, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_ERRCTL, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_ERRINFO1, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_ERRINFO2, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_MERRENTRY, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_MERRERA, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_ERRSAVE, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_CTAG, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_DEBUG, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_DERA, v);
+	GET_SW_GCSR(csr, id, KVM_CSR_DESAVE, v);
+
+	GET_SW_GCSR(csr, id, KVM_CSR_TINTCLR, v);
+
+	if (force && (id < CSR_ALL_SIZE)) {
+		*v = kvm_read_sw_gcsr(csr, id);
+		return 0;
+	}
+
+	return -1;
+}
+
+int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *v, int force)
+{
+	struct loongarch_csrs *csr = vcpu->arch.csr;
+	int ret;
+
+	SET_HW_GCSR(csr, id, KVM_CSR_CRMD, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_PRMD, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_EUEN, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_MISC, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_ECFG, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_ERA, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_BADV, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_BADI, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_EENTRY, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBIDX, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBEHI, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBELO0, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBELO1, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_ASID, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_PGDL, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_PGDH, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_PWCTL0, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_PWCTL1, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_STLBPGSIZE, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_RVACFG, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_CPUID, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS0, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS1, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS2, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS3, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS4, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS5, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS6, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_KS7, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TMID, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TCFG, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TVAL, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_CNTC, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_LLBCTL, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRENTRY, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRBADV, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRERA, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRSAVE, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRELO0, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRELO1, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBREHI, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_TLBRPRMD, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_DMWIN0, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_DMWIN1, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_DMWIN2, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_DMWIN3, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_MWPS, v);
+	SET_HW_GCSR(csr, id, KVM_CSR_FWPS, v);
+
+	SET_SW_GCSR(csr, id, KVM_CSR_IMPCTL1, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_IMPCTL2, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_ERRCTL, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_ERRINFO1, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_ERRINFO2, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_MERRENTRY, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_MERRERA, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_ERRSAVE, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_CTAG, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_DEBUG, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_DERA, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_DESAVE, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_PRCFG1, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_PRCFG2, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_PRCFG3, v);
+
+	SET_SW_GCSR(csr, id, KVM_CSR_PGD, v);
+	SET_SW_GCSR(csr, id, KVM_CSR_TINTCLR, v);
+
+	ret = -1;
+	switch (id) {
+	case KVM_CSR_ESTAT:
+		kvm_write_gcsr_estat(*v);
+		/* estat IP0~IP7 inject through guestexcept */
+		kvm_write_csr_gintc(((*v) >> 2)  & 0xff);
+		ret = 0;
+		break;
+	default:
+		if (force && (id < CSR_ALL_SIZE)) {
+			kvm_set_sw_gcsr(csr, id, *v);
+			ret = 0;
+		}
+		break;
+	}
+
+	return ret;
+}
+
+struct kvm_iocsr {
+	u32 start, end;
+	int (*get) (struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr, u64 *res);
+	int (*set) (struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr, u64 val);
+};
+
+static struct kvm_iocsr_entry *_kvm_find_iocsr(struct kvm *kvm, u32 addr)
+{
+	int i = 0;
+
+	for (i = 0; i < IOCSR_MAX; i++) {
+		if (addr == kvm->arch.iocsr[i].addr)
+			return &kvm->arch.iocsr[i];
+	}
+
+	return NULL;
+}
+
+static int kvm_iocsr_common_get(struct kvm_run *run, struct kvm_vcpu *vcpu,
+		u32 addr, u64 *res)
+{
+	int r = EMULATE_FAIL;
+	struct kvm_iocsr_entry *entry;
+
+	spin_lock(&vcpu->kvm->arch.iocsr_lock);
+	entry = _kvm_find_iocsr(vcpu->kvm, addr);
+	if (entry) {
+		r = EMULATE_DONE;
+		*res = entry->data;
+	}
+	spin_unlock(&vcpu->kvm->arch.iocsr_lock);
+	return r;
+}
+
+static int kvm_iocsr_common_set(struct kvm_run *run, struct kvm_vcpu *vcpu,
+		u32 addr, u64 val)
+{
+	int r = EMULATE_FAIL;
+	struct kvm_iocsr_entry *entry;
+
+	spin_lock(&vcpu->kvm->arch.iocsr_lock);
+	entry = _kvm_find_iocsr(vcpu->kvm, addr);
+	if (entry) {
+		r = EMULATE_DONE;
+		entry->data = val;
+	}
+	spin_unlock(&vcpu->kvm->arch.iocsr_lock);
+	return r;
+}
+
+static int kvm_misc_set(struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr,
+		u64 val)
+{
+	if ((val & KVM_IOCSRF_MISC_FUNC_EXT_IOI_EN) && vcpu->vcpu_id == 0)
+		kvm_setup_ls3a_extirq(vcpu->kvm);
+	return kvm_iocsr_common_set(run, vcpu, addr, val);
+}
+
+static int kvm_ipi_get(struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr,
+		u64 *res)
+{
+	int ret;
+
+	++vcpu->stat.rdcsr_ipi_access_exits;
+	run->mmio.phys_addr = KVM_IPI_REG_ADDRESS(vcpu->vcpu_id, (addr & 0xff));
+	ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr,
+			run->mmio.len, res);
+	if (ret) {
+		run->mmio.is_write = 0;
+		vcpu->mmio_needed = 1;
+		vcpu->mmio_is_write = 0;
+		return EMULATE_DO_MMIO;
+	}
+	return EMULATE_DONE;
+}
+
+static int kvm_extioi_isr_get(struct kvm_run *run, struct kvm_vcpu *vcpu,
+		u32 addr, u64 *res)
+{
+	int ret;
+
+	run->mmio.phys_addr =  EXTIOI_PERCORE_ADDR(vcpu->vcpu_id, (addr & 0xff));
+	ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr,
+			run->mmio.len, res);
+	if (ret) {
+		run->mmio.is_write = 0;
+		vcpu->mmio_needed = 1;
+		vcpu->mmio_is_write = 0;
+		return EMULATE_FAIL;
+	}
+
+	return EMULATE_DONE;
+}
+
+static int kvm_ipi_set(struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr,
+		u64 val)
+{
+	int ret;
+
+	run->mmio.phys_addr = KVM_IPI_REG_ADDRESS(vcpu->vcpu_id, (addr & 0xff));
+	ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr,
+			run->mmio.len, &val);
+	if (ret < 0) {
+		run->mmio.is_write = 1;
+		vcpu->mmio_needed = 1;
+		vcpu->mmio_is_write = 1;
+		return EMULATE_DO_MMIO;
+	}
+
+	return EMULATE_DONE;
+}
+
+static int kvm_extioi_set(struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr,
+		u64 val)
+{
+	int ret;
+
+	if ((addr & 0x1f00) == KVM_IOCSR_EXTIOI_ISR_BASE) {
+		run->mmio.phys_addr =  EXTIOI_PERCORE_ADDR(vcpu->vcpu_id, (addr & 0xff));
+	} else {
+		run->mmio.phys_addr = EXTIOI_ADDR((addr & 0x1fff));
+	}
+
+	ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr,
+			run->mmio.len, &val);
+	if (ret < 0) {
+		memcpy(run->mmio.data, &val, run->mmio.len);
+		run->mmio.is_write = 1;
+		vcpu->mmio_needed = 1;
+		vcpu->mmio_is_write = 1;
+		return EMULATE_DO_MMIO;
+	}
+
+	return EMULATE_DONE;
+}
+
+static int kvm_nop_set(struct kvm_run *run, struct kvm_vcpu *vcpu, u32 addr,
+		u64 val)
+{
+	return EMULATE_DONE;
+}
+
+/* we put these iocsrs with access frequency, from high to low */
+static struct kvm_iocsr kvm_iocsrs[] = {
+	/* extioi iocsr */
+	{KVM_IOCSR_EXTIOI_EN_BASE, KVM_IOCSR_EXTIOI_EN_BASE + 0x100,
+		NULL, kvm_extioi_set},
+	{KVM_IOCSR_EXTIOI_NODEMAP_BASE, KVM_IOCSR_EXTIOI_NODEMAP_BASE+0x28,
+		NULL, kvm_extioi_set},
+	{KVM_IOCSR_EXTIOI_ROUTE_BASE, KVM_IOCSR_EXTIOI_ROUTE_BASE + 0x100,
+		NULL, kvm_extioi_set},
+	{KVM_IOCSR_EXTIOI_ISR_BASE, KVM_IOCSR_EXTIOI_ISR_BASE + 0x1c,
+		kvm_extioi_isr_get, kvm_extioi_set},
+
+	{KVM_IOCSR_IPI_STATUS, KVM_IOCSR_IPI_STATUS + 0x40,
+		kvm_ipi_get, kvm_ipi_set},
+	{KVM_IOCSR_IPI_SEND, KVM_IOCSR_IPI_SEND + 0x1,
+		NULL, kvm_ipi_set},
+	{KVM_IOCSR_MBUF_SEND, KVM_IOCSR_MBUF_SEND + 0x1,
+		NULL, kvm_ipi_set},
+
+	{KVM_IOCSR_FEATURES, KVM_IOCSR_FEATURES + 0x1,
+		kvm_iocsr_common_get, kvm_nop_set},
+	{KVM_IOCSR_VENDOR, KVM_IOCSR_VENDOR + 0x1,
+		kvm_iocsr_common_get, kvm_nop_set},
+	{KVM_IOCSR_CPUNAME, KVM_IOCSR_CPUNAME + 0x1,
+		kvm_iocsr_common_get, kvm_nop_set},
+	{KVM_IOCSR_NODECNT, KVM_IOCSR_NODECNT + 0x1,
+		kvm_iocsr_common_get, kvm_nop_set},
+	{KVM_IOCSR_MISC_FUNC, KVM_IOCSR_MISC_FUNC + 0x1,
+		kvm_iocsr_common_get, kvm_misc_set},
+};
+
+static int _kvm_emu_iocsr_read(struct kvm_run *run, struct kvm_vcpu *vcpu,
+		u32 addr, u64 *res)
+{
+	enum emulation_result er = EMULATE_FAIL;
+	int i = 0;
+	struct kvm_iocsr *iocsr = NULL;
+
+	if (!irqchip_in_kernel(vcpu->kvm)) {
+		run->iocsr_io.len = run->mmio.len;
+		run->iocsr_io.phys_addr = addr;
+		run->iocsr_io.is_write = 0;
+		return EMULATE_DO_IOCSR;
+	}
+	for (i = 0; i < sizeof(kvm_iocsrs) / sizeof(struct kvm_iocsr); i++) {
+		iocsr = &kvm_iocsrs[i];
+		if (addr >= iocsr->start && addr < iocsr->end) {
+			if (iocsr->get)
+				er = iocsr->get(run, vcpu, addr, res);
+		}
+	}
+
+	if (er != EMULATE_DONE)
+		kvm_debug("%s iocsr 0x%x not support in kvm\n", __func__, addr);
+
+	return er;
+}
+
+static int _kvm_emu_iocsr_write(struct kvm_run *run, struct kvm_vcpu *vcpu,
+		u32 addr, u64 val)
+{
+	enum emulation_result er = EMULATE_FAIL;
+	int i = 0;
+	struct kvm_iocsr *iocsr = NULL;
+
+	if (!irqchip_in_kernel(vcpu->kvm)) {
+		run->iocsr_io.len = run->mmio.len;
+		memcpy(run->iocsr_io.data, &val, run->iocsr_io.len);
+		run->iocsr_io.phys_addr = addr;
+		run->iocsr_io.is_write = 1;
+		return EMULATE_DO_IOCSR;
+	}
+	for (i = 0; i < sizeof(kvm_iocsrs) / sizeof(struct kvm_iocsr); i++) {
+		iocsr = &kvm_iocsrs[i];
+		if (addr >= iocsr->start && addr < iocsr->end) {
+			if (iocsr->set)
+				er = iocsr->set(run, vcpu, addr, val);
+		}
+	}
+	if (er != EMULATE_DONE)
+		kvm_debug("%s iocsr 0x%x not support in kvm\n", __func__, addr);
+
+	return er;
+}
+
+/* all iocsr operation should in kvm, no mmio */
+int _kvm_emu_iocsr(larch_inst inst,
+		struct kvm_run *run, struct kvm_vcpu *vcpu)
+{
+	u32 rd, rj, opcode;
+	u32 val;
+	u64 res = 0;
+	int ret;
+
+	/*
+	 * Each IOCSR with different opcode
+	 */
+	rd = inst.reg2_format.rd;
+	rj = inst.reg2_format.rj;
+	opcode = inst.reg2_format.opcode;
+	val = vcpu->arch.gprs[rj];
+	res = vcpu->arch.gprs[rd];
+	/* LoongArch is Little endian */
+	switch (opcode) {
+	case iocsrrdb_op:
+		run->mmio.len = 1;
+		ret = _kvm_emu_iocsr_read(run, vcpu, val, &res);
+		vcpu->arch.gprs[rd] = (u8) res;
+		break;
+	case iocsrrdh_op:
+		run->mmio.len = 2;
+		ret = _kvm_emu_iocsr_read(run, vcpu, val, &res);
+		vcpu->arch.gprs[rd] = (u16) res;
+		break;
+	case iocsrrdw_op:
+		run->mmio.len = 4;
+		ret = _kvm_emu_iocsr_read(run, vcpu, val, &res);
+		vcpu->arch.gprs[rd] = (u32) res;
+		break;
+	case iocsrrdd_op:
+		run->mmio.len = 8;
+		ret = _kvm_emu_iocsr_read(run, vcpu, val, &res);
+		vcpu->arch.gprs[rd] = res;
+		break;
+	case iocsrwrb_op:
+		run->mmio.len = 1;
+		ret = _kvm_emu_iocsr_write(run, vcpu, val, (u8)res);
+		break;
+	case iocsrwrh_op:
+		run->mmio.len = 2;
+		ret = _kvm_emu_iocsr_write(run, vcpu, val, (u16)res);
+		break;
+	case iocsrwrw_op:
+		run->mmio.len = 4;
+		ret = _kvm_emu_iocsr_write(run, vcpu, val, (u32)res);
+		break;
+	case iocsrwrd_op:
+		run->mmio.len = 8;
+		ret = _kvm_emu_iocsr_write(run, vcpu, val, res);
+		break;
+	default:
+		ret = EMULATE_FAIL;
+		break;
+	}
+
+	if (ret == EMULATE_DO_IOCSR) {
+		vcpu->arch.io_gpr = rd;
+	}
+
+	return ret;
+}
+
+int _kvm_complete_iocsr_read(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
+	enum emulation_result er = EMULATE_DONE;
+
+	switch (run->iocsr_io.len) {
+	case 8:
+		*gpr = *(s64 *)run->iocsr_io.data;
+		break;
+	case 4:
+		*gpr = *(int *)run->iocsr_io.data;
+		break;
+	case 2:
+		*gpr = *(short *)run->iocsr_io.data;
+		break;
+	case 1:
+		*gpr = *(char *) run->iocsr_io.data;
+		break;
+	default:
+		kvm_err("Bad IOCSR length: %d,addr is 0x%lx",
+				run->iocsr_io.len, vcpu->arch.badv);
+		er = EMULATE_FAIL;
+		break;
+	}
+
+	return er;
+}
+
+int _kvm_get_iocsr(struct kvm *kvm, struct kvm_iocsr_entry *__user argp)
+{
+	struct kvm_iocsr_entry *entry, tmp;
+	int r = -EFAULT;
+
+	if (copy_from_user(&tmp, argp, sizeof(tmp)))
+		goto out;
+
+	spin_lock(&kvm->arch.iocsr_lock);
+	entry = _kvm_find_iocsr(kvm, tmp.addr);
+	if (entry != NULL)
+		tmp.data = entry->data;
+	spin_unlock(&kvm->arch.iocsr_lock);
+
+	if (entry)
+		r = copy_to_user(argp, &tmp, sizeof(tmp));
+
+out:
+	return r;
+}
+
+int _kvm_set_iocsr(struct kvm *kvm, struct kvm_iocsr_entry *__user argp)
+{
+	struct kvm_iocsr_entry *entry, tmp;
+	int r = -EFAULT;
+
+	if (copy_from_user(&tmp, argp, sizeof(tmp)))
+		goto out;
+
+	spin_lock(&kvm->arch.iocsr_lock);
+	entry = _kvm_find_iocsr(kvm, tmp.addr);
+	if (entry != NULL) {
+		r = 0;
+		entry->data = tmp.data;
+	}
+	spin_unlock(&kvm->arch.iocsr_lock);
+
+	if (tmp.addr == KVM_IOCSR_MISC_FUNC)
+		kvm_enable_ls3a_extirq(kvm, tmp.data & KVM_IOCSRF_MISC_FUNC_EXT_IOI_EN);
+
+out:
+	return r;
+}
+
+static struct kvm_iocsr_entry iocsr_array[IOCSR_MAX] = {
+	{KVM_IOCSR_FEATURES, .data = KVM_IOCSRF_NODECNT|KVM_IOCSRF_MSI
+		|KVM_IOCSRF_EXTIOI|KVM_IOCSRF_CSRIPI|KVM_IOCSRF_VM},
+	{KVM_IOCSR_VENDOR, .data = 0x6e6f73676e6f6f4c}, /* Loongson */
+	{KVM_IOCSR_CPUNAME, .data = 0x303030354133},	/* 3A5000 */
+	{KVM_IOCSR_NODECNT, .data = 0x4},
+	{KVM_IOCSR_MISC_FUNC, .data = 0x0},
+};
+
+int _kvm_init_iocsr(struct kvm *kvm)
+{
+	int i = 0;
+
+	spin_lock_init(&kvm->arch.iocsr_lock);
+	for (i = 0; i < IOCSR_MAX; i++) {
+		kvm->arch.iocsr[i].addr = iocsr_array[i].addr;
+		kvm->arch.iocsr[i].data = iocsr_array[i].data;
+	}
+	return 0;
+}

arch/loongarch/kvm/emulate.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/ktime.h>
+#include <linux/kvm_host.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/random.h>
+#include <asm/page.h>
+#include <asm/cacheflush.h>
+#include <asm/cacheops.h>
+#include <asm/cpu-info.h>
+#include <asm/mmu_context.h>
+#include <asm/tlbflush.h>
+#include <asm/inst.h>
+#include "kvmcpu.h"
+#include "trace.h"
+
+int _kvm_emu_idle(struct kvm_vcpu *vcpu)
+{
+	++vcpu->stat.idle_exits;
+	trace_kvm_exit(vcpu, KVM_TRACE_EXIT_IDLE);
+	if (!vcpu->arch.irq_pending) {
+		kvm_save_timer(vcpu);
+		kvm_vcpu_block(vcpu);
+
+		/*
+		 * We we are runnable, then definitely go off to user space to
+		 * check if any I/O interrupts are pending.
+		 */
+		if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
+			kvm_clear_request(KVM_REQ_UNHALT, vcpu);
+			vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
+		}
+	}
+
+	return EMULATE_DONE;
+}
+
+int _kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst)
+{
+	struct kvm_run *run = vcpu->run;
+	unsigned int rd, op8, opcode;
+	unsigned long rd_val = 0;
+	void *data = run->mmio.data;
+	unsigned long curr_pc;
+	int ret = 0;
+
+	/*
+	 * Update PC and hold onto current PC in case there is
+	 * an error and we want to rollback the PC
+	 */
+	curr_pc = vcpu->arch.pc;
+	update_pc(&vcpu->arch);
+
+	op8 = (inst.word >> 24) & 0xff;
+	run->mmio.phys_addr = vcpu->arch.badv;
+	if (run->mmio.phys_addr == KVM_INVALID_ADDR)
+		goto out_fail;
+
+	if (op8 < 0x28) {
+		/* stptrw/d process */
+		rd = inst.reg2i14_format.rd;
+		opcode = inst.reg2i14_format.opcode;
+
+		switch (opcode) {
+		case stptrd_op:
+			run->mmio.len = 8;
+			*(unsigned long *)data = vcpu->arch.gprs[rd];
+			break;
+		case stptrw_op:
+			run->mmio.len = 4;
+			*(unsigned int *)data = vcpu->arch.gprs[rd];
+			break;
+		default:
+			break;
+		}
+	} else if (op8 < 0x30) {
+		/* st.b/h/w/d  process */
+		rd = inst.reg2i12_format.rd;
+		opcode = inst.reg2i12_format.opcode;
+		rd_val = vcpu->arch.gprs[rd];
+
+		switch (opcode) {
+		case std_op:
+			run->mmio.len = 8;
+			*(unsigned long *)data = rd_val;
+			break;
+		case stw_op:
+			run->mmio.len = 4;
+			*(unsigned int *)data = rd_val;
+			break;
+		case sth_op:
+			run->mmio.len = 2;
+			*(unsigned short *)data = rd_val;
+			break;
+		case stb_op:
+			run->mmio.len = 1;
+			*(unsigned char *)data = rd_val;
+			break;
+		default:
+			kvm_err("Store not yet supporded (inst=0x%08x)\n",
+				inst.word);
+			kvm_arch_vcpu_dump_regs(vcpu);
+			goto out_fail;
+		}
+	} else if (op8 == 0x38) {
+		/* stxb/h/w/d process */
+		rd = inst.reg3_format.rd;
+		opcode = inst.reg3_format.opcode;
+
+		switch (opcode) {
+		case stxb_op:
+			run->mmio.len = 1;
+			*(unsigned char *)data = vcpu->arch.gprs[rd];
+			break;
+		case stxh_op:
+			run->mmio.len = 2;
+			*(unsigned short *)data = vcpu->arch.gprs[rd];
+			break;
+		case stxw_op:
+			run->mmio.len = 4;
+			*(unsigned int *)data = vcpu->arch.gprs[rd];
+			break;
+		case stxd_op:
+			run->mmio.len = 8;
+			*(unsigned long *)data = vcpu->arch.gprs[rd];
+			break;
+		default:
+			kvm_err("Store not yet supporded (inst=0x%08x)\n",
+				inst.word);
+			kvm_arch_vcpu_dump_regs(vcpu);
+			goto out_fail;
+		}
+	} else {
+		kvm_err("Store not yet supporded (inst=0x%08x)\n",
+			inst.word);
+		kvm_arch_vcpu_dump_regs(vcpu);
+		goto out_fail;
+	}
+
+	/* All MMIO emulate in kernel go through the common interface */
+	ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr,
+				run->mmio.len, data);
+	if (!ret) {
+		vcpu->mmio_needed = 0;
+		return EMULATE_DONE;
+	}
+
+	run->mmio.is_write = 1;
+	vcpu->mmio_needed = 1;
+	vcpu->mmio_is_write = 1;
+
+	return EMULATE_DO_MMIO;
+
+out_fail:
+	/* Rollback PC if emulation was unsuccessful */
+	vcpu->arch.pc = curr_pc;
+	return EMULATE_FAIL;
+}
+
+
+int _kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst)
+{
+	unsigned int op8, opcode, rd;
+	int ret = 0;
+	struct kvm_run *run = vcpu->run;
+
+	run->mmio.phys_addr = vcpu->arch.badv;
+	if (run->mmio.phys_addr == KVM_INVALID_ADDR)
+		return EMULATE_FAIL;
+
+	vcpu->mmio_needed = 2;	/* signed */
+	op8 = (inst.word >> 24) & 0xff;
+
+	if (op8 < 0x28) {
+		/* ldptr.w/d process */
+		rd = inst.reg2i14_format.rd;
+		opcode = inst.reg2i14_format.opcode;
+
+		switch (opcode) {
+		case ldptrd_op:
+			run->mmio.len = 8;
+			break;
+		case ldptrw_op:
+			run->mmio.len = 4;
+			break;
+		default:
+			break;
+		}
+	} else if (op8 < 0x2f) {
+		/* ld.b/h/w/d, ld.bu/hu/wu process */
+		rd = inst.reg2i12_format.rd;
+		opcode = inst.reg2i12_format.opcode;
+
+		switch (opcode) {
+		case ldd_op:
+			run->mmio.len = 8;
+			break;
+		case ldwu_op:
+			vcpu->mmio_needed = 1;	/* unsigned */
+			run->mmio.len = 4;
+			break;
+		case ldw_op:
+			run->mmio.len = 4;
+			break;
+		case ldhu_op:
+			vcpu->mmio_needed = 1;	/* unsigned */
+			run->mmio.len = 2;
+			break;
+		case ldh_op:
+			run->mmio.len = 2;
+			break;
+		case ldbu_op:
+			vcpu->mmio_needed = 1;	/* unsigned */
+			run->mmio.len = 1;
+			break;
+		case ldb_op:
+			run->mmio.len = 1;
+			break;
+		default:
+			kvm_err("Load not yet supporded (inst=0x%08x)\n",
+				inst.word);
+			kvm_arch_vcpu_dump_regs(vcpu);
+			vcpu->mmio_needed = 0;
+			return EMULATE_FAIL;
+		}
+	} else if (op8 == 0x38) {
+		/* ldxb/h/w/d, ldxb/h/wu, ldgtb/h/w/d, ldleb/h/w/d process */
+		rd = inst.reg3_format.rd;
+		opcode = inst.reg3_format.opcode;
+
+		switch (opcode) {
+		case ldxb_op:
+			run->mmio.len = 1;
+			break;
+		case ldxbu_op:
+			run->mmio.len = 1;
+			vcpu->mmio_needed = 1;	/* unsigned */
+			break;
+		case ldxh_op:
+			run->mmio.len = 2;
+			break;
+		case ldxhu_op:
+			run->mmio.len = 2;
+			vcpu->mmio_needed = 1;	/* unsigned */
+			break;
+		case ldxw_op:
+			run->mmio.len = 4;
+			break;
+		case ldxwu_op:
+			run->mmio.len = 4;
+			vcpu->mmio_needed = 1;	/* unsigned */
+			break;
+		case ldxd_op:
+			run->mmio.len = 8;
+			break;
+		default:
+			kvm_err("Load not yet supporded (inst=0x%08x)\n",
+				inst.word);
+			kvm_arch_vcpu_dump_regs(vcpu);
+			vcpu->mmio_needed = 0;
+			return EMULATE_FAIL;
+		}
+	} else {
+		kvm_err("Load not yet supporded (inst=0x%08x) @ %lx\n",
+			inst.word, vcpu->arch.pc);
+		vcpu->mmio_needed = 0;
+		return EMULATE_FAIL;
+	}
+
+	/* Set for _kvm_complete_mmio_read use */
+	vcpu->arch.io_gpr = rd;
+	ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, run->mmio.phys_addr,
+						run->mmio.len, run->mmio.data);
+	run->mmio.is_write = 0;
+	vcpu->mmio_is_write = 0;
+
+	if (!ret) {
+		_kvm_complete_mmio_read(vcpu, run);
+		vcpu->mmio_needed = 0;
+		return EMULATE_DONE;
+	}
+	return EMULATE_DO_MMIO;
+}
+
+int _kvm_complete_mmio_read(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
+	enum emulation_result er = EMULATE_DONE;
+
+	/* update with new PC */
+	update_pc(&vcpu->arch);
+	switch (run->mmio.len) {
+	case 8:
+		*gpr = *(s64 *)run->mmio.data;
+		break;
+
+	case 4:
+		if (vcpu->mmio_needed == 2) {
+			*gpr = *(int *)run->mmio.data;
+		} else
+			*gpr = *(unsigned int *)run->mmio.data;
+		break;
+
+	case 2:
+		if (vcpu->mmio_needed == 2)
+			*gpr = *(short *) run->mmio.data;
+		else
+			*gpr = *(unsigned short *)run->mmio.data;
+
+		break;
+	case 1:
+		if (vcpu->mmio_needed == 2)
+			*gpr = *(char *) run->mmio.data;
+		else
+			*gpr = *(unsigned char *) run->mmio.data;
+		break;
+	default:
+		kvm_err("Bad MMIO length: %d,addr is 0x%lx",
+				run->mmio.len, vcpu->arch.badv);
+		er = EMULATE_FAIL;
+		break;
+	}
+
+	return er;
+}

arch/loongarch/kvm/entry.S

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/linkage.h>
+#include <asm/stackframe.h>
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/regdef.h>
+#include "kvm_compat.h"
+
+#define RESUME_HOST	(1 << 1)
+
+#define GGPR_OFFSET(x)	(KVM_ARCH_GGPR + 8*x)
+#define PT_GPR_OFFSET(x)	(PT_R0 + 8*x)
+
+	.text
+
+.macro kvm_save_guest_gprs base
+	.irp n,1,2,3,4,5,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+	KVM_LONG_S	$r\n, \base, GGPR_OFFSET(\n)
+	.endr
+.endm
+
+.macro kvm_restore_guest_gprs base
+	.irp n,1,2,3,4,5,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+	KVM_LONG_L	$r\n, \base, GGPR_OFFSET(\n)
+	.endr
+.endm
+
+.macro kvm_save_host_gpr base
+	.irp n,1,2,3,22,23,24,25,26,27,28,29,30,31
+	KVM_LONG_S	$r\n, \base, PT_GPR_OFFSET(\n)
+	.endr
+.endm
+
+.macro kvm_restore_host_gpr base
+	.irp n,1,2,3,22,23,24,25,26,27,28,29,30,31
+	KVM_LONG_L	$r\n, \base, PT_GPR_OFFSET(\n)
+	.endr
+.endm
+
+/*
+ * prepare switch to guest
+ * @param:
+ *  KVM_ARCH: kvm_vcpu_arch, don't touch it until 'ertn'
+ *  GPRNUM: KVM_ARCH gpr number
+ *  tmp, tmp1: temp register
+ */
+.macro kvm_switch_to_guest KVM_ARCH GPRNUM tmp tmp1
+	/* set host excfg.VS=0, all exceptions share one exception entry */
+	csrrd	\tmp, KVM_CSR_ECFG
+	bstrins.w	\tmp, zero, (KVM_ECFG_VS_SHIFT + KVM_ECFG_VS_WIDTH - 1), KVM_ECFG_VS_SHIFT
+	csrwr	\tmp, KVM_CSR_ECFG
+
+	/* Load up the new EENTRY */
+	KVM_LONG_L	\tmp, \KVM_ARCH, KVM_ARCH_GEENTRY
+	csrwr		\tmp, KVM_CSR_EENTRY
+
+	/* Set Guest ERA */
+	KVM_LONG_L	\tmp, \KVM_ARCH, KVM_ARCH_GPC
+	csrwr		\tmp, KVM_CSR_ERA
+
+	/* Save host PGDL */
+	csrrd	\tmp, KVM_CSR_PGDL
+	KVM_LONG_S	\tmp, \KVM_ARCH, KVM_ARCH_HPGD
+
+	/* Switch to kvm */
+	KVM_LONG_L	\tmp1, \KVM_ARCH, KVM_VCPU_KVM - KVM_VCPU_ARCH
+
+	/* Load guest PGDL */
+	lu12i.w \tmp, KVM_GPGD
+	srli.w \tmp, \tmp, 12
+	ldx.d  \tmp, \tmp1, \tmp
+	csrwr	\tmp, KVM_CSR_PGDL
+
+	/* Mix GID and RID */
+	csrrd	\tmp1, KVM_CSR_GSTAT
+	bstrpick.w	\tmp1, \tmp1, (KVM_GSTAT_GID_SHIFT + KVM_GSTAT_GID_WIDTH - 1), KVM_GSTAT_GID_SHIFT
+	csrrd	\tmp, KVM_CSR_GTLBC
+	bstrins.w	\tmp, \tmp1, (KVM_GTLBC_TGID_SHIFT + KVM_GTLBC_TGID_WIDTH - 1), KVM_GTLBC_TGID_SHIFT
+	csrwr	\tmp, KVM_CSR_GTLBC
+
+	/*
+	 * Switch to guest:
+	 *  GSTAT.PGM = 1, ERRCTL.ISERR = 0, TLBRPRMD.ISTLBR = 0
+	 *  ertn
+	 */
+
+	/* Prepare enable Intr before enter guest */
+	ori	\tmp, zero, KVM_PRMD_PIE
+	csrxchg	\tmp, \tmp, KVM_CSR_PRMD
+
+	/* Set PVM bit to setup ertn to guest context */
+	ori	\tmp, zero, KVM_GSTAT_PVM
+	csrxchg	\tmp, \tmp, KVM_CSR_GSTAT
+
+	/* Load Guest gprs */
+	kvm_restore_guest_gprs	\KVM_ARCH
+
+	/* Load KVM_ARCH register */
+	KVM_LONG_L	\KVM_ARCH, \KVM_ARCH, GGPR_OFFSET(\GPRNUM)
+
+	ertn
+.endm
+
+#ifndef	EXCPTION_ENTRY
+#define EXCPTION_ENTRY(name)	\
+	.globl name ASM_NL	\
+	.p2align	12;	\
+	name:			\
+		.cfi_startproc;
+#endif
+#ifndef	EXCPTION_ENDPROC
+#define EXCPTION_ENDPROC(name)	\
+	.cfi_endproc;			\
+	SYM_END(name, SYM_T_FUNC)
+#endif
+
+/* load kvm_vcpu to a2 and store a1 for free use */
+EXCPTION_ENTRY(kvm_exception_entry)
+	csrwr	a2, KVM_TEMP_KS
+	csrrd	a2, KVM_VCPU_KS
+	KVM_LONG_ADDI	a2, a2, KVM_VCPU_ARCH
+
+	/* After save gprs, free to use any gpr */
+	kvm_save_guest_gprs	a2
+	/* Save guest a2 */
+	csrrd	t0, KVM_TEMP_KS
+	KVM_LONG_S	t0, a2, GGPR_OFFSET(REG_A2)
+
+	b	kvm_exit_entry
+EXCPTION_ENDPROC(kvm_exception_entry)
+
+/* a2: kvm_vcpu_arch, a1 is free to use */
+SYM_FUNC_START(kvm_exit_entry)
+	csrrd	s1, KVM_VCPU_KS
+	KVM_LONG_L	s0, s1, KVM_VCPU_RUN
+
+	csrrd		t0, KVM_CSR_ESTAT
+	KVM_LONG_S	t0, a2, KVM_ARCH_HESTAT
+	csrrd		t0, KVM_CSR_ERA
+	KVM_LONG_S	t0, a2, KVM_ARCH_GPC
+	csrrd		t0, KVM_CSR_BADV
+	KVM_LONG_S	t0, a2, KVM_ARCH_HBADV
+	csrrd		t0, KVM_CSR_BADI
+	KVM_LONG_S	t0, a2, KVM_ARCH_HBADI
+
+	/* Restore host excfg.VS */
+	csrrd		t0, KVM_CSR_ECFG
+	KVM_LONG_L	t1, a2, KVM_ARCH_HECFG
+	or		t0, t0, t1
+	csrwr		t0, KVM_CSR_ECFG
+
+	/* Restore host eentry */
+	KVM_LONG_L	t0, a2, KVM_ARCH_HEENTRY
+	csrwr		t0, KVM_CSR_EENTRY
+
+#if defined(CONFIG_CPU_HAS_FPU)
+	/* Save FPU context */
+	csrrd	t0, KVM_CSR_EUEN
+	ori	t1, zero, KVM_EUEN_FPEN | KVM_EUEN_LSXEN | KVM_EUEN_LASXEN
+	and	t2, t0, t1
+	beqz	t2, 1f
+	movfcsr2gr	t3, fcsr0
+	INT_S	t3,	a2, VCPU_FCSR0
+
+	movcf2gr	t3, $fcc0
+	or		t2, t3, zero
+	movcf2gr	t3, $fcc1
+	bstrins.d	t2, t3, 0xf, 0x8
+	movcf2gr	t3, $fcc2
+	bstrins.d	t2, t3, 0x17, 0x10
+	movcf2gr	t3, $fcc3
+	bstrins.d	t2, t3, 0x1f, 0x18
+	movcf2gr	t3, $fcc4
+	bstrins.d	t2, t3, 0x27, 0x20
+	movcf2gr	t3, $fcc5
+	bstrins.d	t2, t3, 0x2f, 0x28
+	movcf2gr	t3, $fcc6
+	bstrins.d	t2, t3, 0x37, 0x30
+	movcf2gr	t3, $fcc7
+	bstrins.d	t2, t3, 0x3f, 0x38
+	KVM_LONG_S	t2, a2, VCPU_FCC
+	movgr2fcsr	fcsr0, zero
+1:
+#endif
+
+	KVM_LONG_L	t0, a2, KVM_ARCH_HPGD
+	csrwr	t0, KVM_CSR_PGDL
+
+	/* Disable PVM bit for keeping from into guest */
+	ori	t0, zero, KVM_GSTAT_PVM
+	csrxchg	zero, t0, KVM_CSR_GSTAT
+
+	/* Clear GTLBC.TGID field */
+	csrrd	t0, KVM_CSR_GTLBC
+	bstrins.w	t0, zero, KVM_GTLBC_TGID_SHIFT + KVM_GTLBC_TGID_WIDTH - 1, KVM_GTLBC_TGID_SHIFT
+	csrwr	t0, KVM_CSR_GTLBC
+
+	/* Enable Address Map mode */
+	ori	t0, zero, (1 << KVM_CRMD_DACM_SHIFT)|(1 << KVM_CRMD_DACF_SHIFT) | KVM_CRMD_PG |PLV_KERN
+	csrwr	t0, KVM_CSR_CRMD
+
+	KVM_LONG_L	tp, a2, KVM_ARCH_HGP
+	KVM_LONG_L	sp, a2, KVM_ARCH_HSTACK
+	/* restore per cpu register */
+	KVM_LONG_L	$r21, a2, KVM_ARCH_HPERCPU
+
+	KVM_LONG_ADDI	sp, sp, -PT_SIZE
+
+	/* Prepare handle exception */
+	or		a0, s0, zero
+	or		a1, s1, zero
+	KVM_LONG_L	t8, a2, KVM_ARCH_HANDLE_EXIT
+	jirl		ra,t8, 0
+
+	ori	t0, zero, KVM_CRMD_IE
+	csrxchg	zero, t0, KVM_CSR_CRMD
+	or	a2, s1, zero
+	KVM_LONG_ADDI	a2, a2, KVM_VCPU_ARCH
+
+	andi	t0, v0, RESUME_HOST
+	bnez	t0, ret_to_host
+	INT_S	zero, a2, KVM_ARCH_ISHYPCALL
+
+ret_to_guest:
+	/* Save per cpu register again, maybe switched to another cpu */
+	KVM_LONG_S	$r21, a2, KVM_ARCH_HPERCPU
+
+	/* Save kvm_vcpu to kscratch */
+	csrwr	s1, KVM_VCPU_KS
+	kvm_switch_to_guest a2 REG_A2 t0 t1
+
+ret_to_host:
+	KVM_LONG_L  a2, a2, KVM_ARCH_HSTACK
+	addi.d  a2, a2, -PT_SIZE
+	srai.w  a3, v0, 2
+	or      v0, a3, zero
+	kvm_restore_host_gpr    a2
+	jirl    zero, ra, 0
+SYM_FUNC_END(kvm_exit_entry)
+
+/*
+ * int kvm_enter_guest(struct kvm_run *run, struct kvm_vcpu *vcpu)
+ *
+ * @register_param:
+ *  a0: kvm_run* run
+ *  a1: kvm_vcpu* vcpu
+ */
+SYM_FUNC_START(kvm_enter_guest)
+	/* allocate space in stack bottom */
+	KVM_LONG_ADDI	a2, sp, -PT_SIZE
+
+	/* save host gprs */
+	kvm_save_host_gpr a2
+
+	/* save host crmd,prmd csr to stack */
+	csrrd		a3, KVM_CSR_CRMD
+	KVM_LONG_S	a3, a2, PT_CRMD
+	csrrd		a3, KVM_CSR_PRMD
+	KVM_LONG_S	a3, a2, PT_PRMD
+
+	KVM_LONG_ADDI	a2, a1, KVM_VCPU_ARCH
+	KVM_LONG_S	sp, a2, KVM_ARCH_HSTACK
+	KVM_LONG_S	tp, a2, KVM_ARCH_HGP
+	/* Save per cpu register */
+	KVM_LONG_S	$r21, a2, KVM_ARCH_HPERCPU
+
+	/* Save kvm_vcpu to kscratch */
+	csrwr	a1, KVM_VCPU_KS
+
+	kvm_switch_to_guest	a2 REG_A2 t0 t1
+
+SYM_FUNC_END(kvm_enter_guest)
+
+SYM_FUNC_START(__kvm_save_fpu)
+	fpu_save_double a0 t1
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_save_fpu)
+
+SYM_FUNC_START(__kvm_restore_fpu)
+	fpu_restore_double a0 t1
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_restore_fpu)
+
+SYM_FUNC_START(__kvm_restore_fcsr)
+	fpu_restore_csr a0 t1
+	fpu_restore_cc  a0 t1 t2
+
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_restore_fcsr)
+
+#ifdef CONFIG_CPU_HAS_LSX
+SYM_FUNC_START(__kvm_save_lsx)
+	lsx_save_data a0 t1
+
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_save_lsx)
+
+SYM_FUNC_START(__kvm_restore_lsx)
+	lsx_restore_data a0 t1
+
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_restore_lsx)
+
+SYM_FUNC_START(__kvm_restore_lsx_upper)
+	lsx_restore_all_upper a0 t0 t1
+
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_restore_lsx_upper)
+#endif
+
+#ifdef CONFIG_CPU_HAS_LASX
+SYM_FUNC_START(__kvm_save_lasx)
+	lasx_save_data a0 t7
+
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_save_lasx)
+
+SYM_FUNC_START(__kvm_restore_lasx)
+	lasx_restore_data a0 t7
+
+	jirl    zero, ra, 0
+SYM_FUNC_END(__kvm_restore_lasx)
+#endif
+

arch/loongarch/kvm/exit.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/preempt.h>
+#include <linux/vmalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/cacheops.h>
+#include <asm/cmpxchg.h>
+#include <asm/fpu.h>
+#include <asm/inst.h>
+#include <asm/mmu_context.h>
+#include <asm/cacheflush.h>
+#include <asm/time.h>
+#include <asm/tlb.h>
+#include <asm/numa.h>
+#include <asm/watch.h>
+#include "kvmcpu.h"
+#include <linux/kvm_host.h>
+#include <mmzone.h>
+
+#include "trace.h"
+#include "kvm_compat.h"
+#include "kvmcsr.h"
+#include "intc/ls3a_ext_irq.h"
+
+/*
+ * Loongarch KVM callback handling for not implemented guest exiting
+ */
+static int _kvm_fault_ni(struct kvm_vcpu *vcpu)
+{
+	unsigned long estat, badv;
+	unsigned int exccode, inst;
+
+	/*
+	 *  Fetch the instruction.
+	 */
+	badv = vcpu->arch.badv;
+	estat = vcpu->arch.host_estat;
+	exccode = (estat & KVM_ESTAT_EXC) >> KVM_ESTAT_EXC_SHIFT;
+	inst = vcpu->arch.badi;
+	kvm_err("Exccode: %d PC=%#lx inst=0x%08x BadVaddr=%#lx estat=%#llx\n",
+		exccode, vcpu->arch.pc, inst, badv, kvm_read_gcsr_estat());
+	kvm_arch_vcpu_dump_regs(vcpu);
+	vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+	return RESUME_HOST;
+}
+
+static int _kvm_handle_csr(struct kvm_vcpu *vcpu, larch_inst inst)
+{
+	enum emulation_result er = EMULATE_DONE;
+	unsigned int rd, rj, csrid;
+	unsigned long csr_mask;
+	unsigned long val = 0;
+
+	/*
+	 * CSR value mask imm
+	 * rj = 0 means csrrd
+	 * rj = 1 means csrwr
+	 * rj != 0,1 means csrxchg
+	 */
+	rd = inst.reg2csr_format.rd;
+	rj = inst.reg2csr_format.rj;
+	csrid = inst.reg2csr_format.csr;
+
+	/* Process CSR ops */
+	if (rj == 0) {
+		/* process csrrd */
+		val = _kvm_emu_read_csr(vcpu, csrid);
+		if (er != EMULATE_FAIL)
+			vcpu->arch.gprs[rd] = val;
+	} else if (rj == 1) {
+		/* process csrwr */
+		val = vcpu->arch.gprs[rd];
+		_kvm_emu_write_csr(vcpu, csrid, val);
+	} else {
+		/* process csrxchg */
+		val = vcpu->arch.gprs[rd];
+		csr_mask = vcpu->arch.gprs[rj];
+		_kvm_emu_xchg_csr(vcpu, csrid, csr_mask, val);
+	}
+
+	return er;
+}
+
+static int _kvm_emu_cache(struct kvm_vcpu *vcpu, larch_inst inst)
+{
+	return EMULATE_DONE;
+}
+
+static int _kvm_trap_handle_gspr(struct kvm_vcpu *vcpu)
+{
+	enum emulation_result er = EMULATE_DONE;
+	struct kvm_run *run = vcpu->run;
+	larch_inst inst;
+	unsigned long curr_pc;
+	int rd, rj;
+	unsigned int index;
+
+	/*
+	 *  Fetch the instruction.
+	 */
+	inst.word = vcpu->arch.badi;
+	curr_pc = vcpu->arch.pc;
+	update_pc(&vcpu->arch);
+
+	er = EMULATE_FAIL;
+	switch (((inst.word >> 24) & 0xff)) {
+	case 0x0:
+		/* cpucfg GSPR */
+		if (inst.reg2_format.opcode == 0x1B) {
+			rd = inst.reg2_format.rd;
+			rj = inst.reg2_format.rj;
+			++vcpu->stat.cpucfg_exits;
+			index = vcpu->arch.gprs[rj];
+			vcpu->arch.gprs[rd] = vcpu->kvm->arch.cpucfgs.cpucfg[index];
+			if (vcpu->arch.gprs[rd] == 0) {
+				/*
+				 * Fallback to get host cpucfg info, this is just for
+				 * compatible with older qemu.
+				 */
+				vcpu->arch.gprs[rd] = read_cpucfg(index);
+				/* Nested KVM is not supported */
+				if (index == 2)
+					vcpu->arch.gprs[rd] &= ~CPUCFG2_LVZP;
+			}
+			er = EMULATE_DONE;
+		}
+		break;
+	case 0x4:
+		/* csr GSPR */
+		er = _kvm_handle_csr(vcpu, inst);
+		break;
+	case 0x6:
+		/* iocsr,cache,idle GSPR */
+		switch (((inst.word >> 22) & 0x3ff)) {
+		case 0x18:
+			/* cache GSPR */
+			er = _kvm_emu_cache(vcpu, inst);
+			trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
+			break;
+		case 0x19:
+			/* iocsr/idle GSPR */
+			switch (((inst.word >> 15) & 0x1ffff)) {
+			case 0xc90:
+				/* iocsr GSPR */
+				er = _kvm_emu_iocsr(inst, run, vcpu);
+				break;
+			case 0xc91:
+				/* idle GSPR */
+				er = _kvm_emu_idle(vcpu);
+				break;
+			default:
+				er = EMULATE_FAIL;
+				break;
+			}
+			break;
+		default:
+			er = EMULATE_FAIL;
+			break;
+		}
+		break;
+	default:
+		er = EMULATE_FAIL;
+		break;
+	}
+
+	/* Rollback PC only if emulation was unsuccessful */
+	if (er == EMULATE_FAIL) {
+		kvm_err("[%#lx]%s: unsupported gspr instruction 0x%08x\n",
+			curr_pc, __func__, inst.word);
+
+		kvm_arch_vcpu_dump_regs(vcpu);
+		vcpu->arch.pc = curr_pc;
+	}
+	return er;
+}
+
+static int _kvm_check_hypcall(struct kvm_vcpu *vcpu)
+{
+	enum emulation_result ret;
+	larch_inst inst;
+	unsigned long curr_pc;
+	unsigned int code;
+
+	/*
+	 * Update PC and hold onto current PC in case there is
+	 * an error and we want to rollback the PC
+	 */
+	inst.word = vcpu->arch.badi;
+	code = inst.reg0i15_format.simmediate;
+	curr_pc = vcpu->arch.pc;
+	update_pc(&vcpu->arch);
+
+	ret = EMULATE_DONE;
+	switch (code) {
+	case KVM_HC_CODE_SERIVCE:
+		ret = EMULATE_PV_HYPERCALL;
+		break;
+	case KVM_HC_CODE_SWDBG:
+		/*
+		 * Only SWDBG(SoftWare DeBug) could stop vm
+		 * code other than 0 is ignored.
+		 */
+		ret = EMULATE_DEBUG;
+		break;
+	default:
+		kvm_info("[%#lx] HYPCALL %#03x unsupported\n", vcpu->arch.pc, code);
+		break;
+	}
+
+	if (ret == EMULATE_DEBUG)
+		vcpu->arch.pc = curr_pc;
+
+	return ret;
+}
+
+/* Execute cpucfg instruction will tirggerGSPR,
+ * Also the access to unimplemented csrs 0x15
+ * 0x16, 0x50~0x53, 0x80, 0x81, 0x90~0x95, 0x98
+ * 0xc0~0xff, 0x100~0x109, 0x500~0x502,
+ * cache_op, idle_op iocsr ops the same */
+static int _kvm_handle_gspr(struct kvm_vcpu *vcpu)
+{
+	enum emulation_result er = EMULATE_DONE;
+	int ret = RESUME_GUEST;
+
+	vcpu->arch.is_hypcall = 0;
+
+	er = _kvm_trap_handle_gspr(vcpu);
+
+	if (er == EMULATE_DONE) {
+		ret = RESUME_GUEST;
+	} else if (er == EMULATE_DO_MMIO) {
+		vcpu->run->exit_reason = KVM_EXIT_MMIO;
+		ret = RESUME_HOST;
+	} else if (er == EMULATE_DO_IOCSR) {
+		vcpu->run->exit_reason = KVM_EXIT_LOONGARCH_IOCSR;
+		ret = RESUME_HOST;
+	} else {
+		kvm_err("%s internal error\n", __func__);
+		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		ret = RESUME_HOST;
+	}
+	return ret;
+}
+
+static int _kvm_handle_hypcall(struct kvm_vcpu *vcpu)
+{
+	enum emulation_result er = EMULATE_DONE;
+	int ret = RESUME_GUEST;
+
+	vcpu->arch.is_hypcall = 0;
+	er = _kvm_check_hypcall(vcpu);
+
+	if (er == EMULATE_PV_HYPERCALL)
+		ret = _kvm_handle_pv_hcall(vcpu);
+	else if (er == EMULATE_DEBUG) {
+		vcpu->run->exit_reason = KVM_EXIT_DEBUG;
+		ret = RESUME_HOST;
+	} else
+		ret = RESUME_GUEST;
+
+	return ret;
+}
+
+static int _kvm_handle_gcm(struct kvm_vcpu *vcpu)
+{
+	int ret, subcode;
+
+	vcpu->arch.is_hypcall = 0;
+	ret = RESUME_GUEST;
+	subcode = (vcpu->arch.host_estat & KVM_ESTAT_ESUBCODE) >> KVM_ESTAT_ESUBCODE_SHIFT;
+	if ((subcode != EXCSUBCODE_GCSC) && (subcode != EXCSUBCODE_GCHC)) {
+		kvm_err("%s internal error\n", __func__);
+		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		ret = RESUME_HOST;
+	}
+
+	return ret;
+}
+
+/**
+ * _kvm_handle_fpu_disabled() - Guest used fpu however it is disabled at host
+ * @vcpu:	Virtual CPU context.
+ *
+ * Handle when the guest attempts to use fpu which hasn't been allowed
+ * by the root context.
+ */
+static int _kvm_handle_fpu_disabled(struct kvm_vcpu *vcpu)
+{
+	struct kvm_run *run = vcpu->run;
+
+	/*
+	 * If guest FPU not present, the FPU operation should have been
+	 * treated as a reserved instruction!
+	 * If FPU already in use, we shouldn't get this at all.
+	 */
+	if (WARN_ON(!_kvm_guest_has_fpu(&vcpu->arch) ||
+				vcpu->arch.aux_inuse & KVM_LARCH_FPU)) {
+		kvm_err("%s internal error\n", __func__);
+		run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		return RESUME_HOST;
+	}
+
+	kvm_own_fpu(vcpu);
+	return RESUME_GUEST;
+}
+
+/**
+ * _kvm_handle_lsx_disabled() - Guest used LSX while disabled in root.
+ * @vcpu:	Virtual CPU context.
+ *
+ * Handle when the guest attempts to use LSX when it is disabled in the root
+ * context.
+ */
+static int _kvm_handle_lsx_disabled(struct kvm_vcpu *vcpu)
+{
+	struct kvm_run *run = vcpu->run;
+
+	/*
+	 * If LSX not present or not exposed to guest, the LSX operation
+	 * should have been treated as a reserved instruction!
+	 * If LSX already in use, we shouldn't get this at all.
+	 */
+	if (!_kvm_guest_has_lsx(&vcpu->arch) ||
+	    !(kvm_read_gcsr_euen() & KVM_EUEN_LSXEN) ||
+	    vcpu->arch.aux_inuse & KVM_LARCH_LSX) {
+		kvm_err("%s internal error, lsx %d guest euen %llx aux %x",
+			__func__, _kvm_guest_has_lsx(&vcpu->arch),
+			kvm_read_gcsr_euen(), vcpu->arch.aux_inuse);
+		run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		return RESUME_HOST;
+	}
+
+	kvm_own_lsx(vcpu);
+	return RESUME_GUEST;
+}
+
+bool _kvm_guest_has_lasx(struct kvm_vcpu *vcpu)
+{
+      return cpu_has_lasx && vcpu->arch.lsx_enabled && vcpu->kvm->arch.cpucfg_lasx;
+}
+
+/**
+ * _kvm_handle_lasx_disabled() - Guest used LASX while disabled in root.
+ * @vcpu:	Virtual CPU context.
+ *
+ * Handle when the guest attempts to use LASX when it is disabled in the root
+ * context.
+ */
+static int _kvm_handle_lasx_disabled(struct kvm_vcpu *vcpu)
+{
+	struct kvm_run *run = vcpu->run;
+
+	/*
+	 * If LASX not present or not exposed to guest, the LASX operation
+	 * should have been treated as a reserved instruction!
+	 * If LASX already in use, we shouldn't get this at all.
+	 */
+	if (!_kvm_guest_has_lasx(vcpu) ||
+	    !(kvm_read_gcsr_euen() & KVM_EUEN_LSXEN) ||
+	    !(kvm_read_gcsr_euen() & KVM_EUEN_LASXEN) ||
+	    vcpu->arch.aux_inuse & KVM_LARCH_LASX) {
+		kvm_err("%s internal error, lasx %d guest euen %llx aux %x",
+			__func__, _kvm_guest_has_lasx(vcpu),
+			kvm_read_gcsr_euen(), vcpu->arch.aux_inuse);
+		run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		return RESUME_HOST;
+	}
+
+	kvm_own_lasx(vcpu);
+
+	return RESUME_GUEST;
+}
+
+
+static int _kvm_handle_read_fault(struct kvm_vcpu *vcpu)
+{
+	struct kvm_run *run = vcpu->run;
+	ulong badv = vcpu->arch.badv;
+	larch_inst inst;
+	enum emulation_result er = EMULATE_DONE;
+	int ret = RESUME_GUEST;
+
+	if (kvm_handle_mm_fault(vcpu, badv, false)) {
+		/* A code fetch fault doesn't count as an MMIO */
+		if (kvm_is_ifetch_fault(&vcpu->arch)) {
+			kvm_err("%s ifetch error addr:%lx\n", __func__, badv);
+			run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+			return RESUME_HOST;
+		}
+
+		/* Treat as MMIO */
+		inst.word =  vcpu->arch.badi;
+		er = _kvm_emu_mmio_read(vcpu, inst);
+		if (er == EMULATE_FAIL) {
+			kvm_err("Guest Emulate Load failed: PC: %#lx, BadVaddr: %#lx\n",
+				vcpu->arch.pc, badv);
+			run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		}
+	}
+
+	if (er == EMULATE_DONE) {
+		ret = RESUME_GUEST;
+	} else if (er == EMULATE_DO_MMIO) {
+		run->exit_reason = KVM_EXIT_MMIO;
+		ret = RESUME_HOST;
+	} else {
+		run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		ret = RESUME_HOST;
+	}
+	return ret;
+}
+
+static int _kvm_handle_write_fault(struct kvm_vcpu *vcpu)
+{
+	struct kvm_run *run = vcpu->run;
+	ulong badv = vcpu->arch.badv;
+	larch_inst inst;
+	enum emulation_result er = EMULATE_DONE;
+	int ret = RESUME_GUEST;
+
+	if (kvm_handle_mm_fault(vcpu, badv, true)) {
+
+		/* Treat as MMIO */
+		inst.word =  vcpu->arch.badi;
+		er = _kvm_emu_mmio_write(vcpu, inst);
+		if (er == EMULATE_FAIL) {
+			kvm_err("Guest Emulate Store failed: PC:  %#lx, BadVaddr: %#lx\n",
+				vcpu->arch.pc, badv);
+			run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		}
+	}
+
+	if (er == EMULATE_DONE) {
+		ret = RESUME_GUEST;
+	} else if (er == EMULATE_DO_MMIO) {
+		run->exit_reason = KVM_EXIT_MMIO;
+		ret = RESUME_HOST;
+	} else {
+		run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+		ret = RESUME_HOST;
+	}
+	return ret;
+}
+
+static int _kvm_handle_debug(struct kvm_vcpu *vcpu)
+{
+	uint32_t fwps, mwps;
+
+	fwps = kvm_csr_readq(KVM_CSR_FWPS);
+	mwps = kvm_csr_readq(KVM_CSR_MWPS);
+	if (fwps & 0xff)
+		kvm_csr_writeq(fwps, KVM_CSR_FWPS);
+	if (mwps & 0xff)
+		kvm_csr_writeq(mwps, KVM_CSR_MWPS);
+	vcpu->run->debug.arch.exception = EXCCODE_WATCH;
+	vcpu->run->debug.arch.fwps = fwps;
+	vcpu->run->debug.arch.mwps = mwps;
+	vcpu->run->exit_reason = KVM_EXIT_DEBUG;
+	return RESUME_HOST;
+}
+
+static exit_handle_fn _kvm_fault_tables[EXCCODE_INT_START] = {
+	[EXCCODE_TLBL]		= _kvm_handle_read_fault,
+	[EXCCODE_TLBS]		= _kvm_handle_write_fault,
+	[EXCCODE_TLBI]		= _kvm_handle_read_fault,
+	[EXCCODE_TLBM]		= _kvm_handle_write_fault,
+	[EXCCODE_TLBRI]		= _kvm_handle_read_fault,
+	[EXCCODE_TLBXI]		= _kvm_handle_read_fault,
+	[EXCCODE_FPDIS]		= _kvm_handle_fpu_disabled,
+	[EXCCODE_LSXDIS]	= _kvm_handle_lsx_disabled,
+	[EXCCODE_LASXDIS]	= _kvm_handle_lasx_disabled,
+	[EXCCODE_WATCH]		= _kvm_handle_debug,
+	[EXCCODE_GSPR]		= _kvm_handle_gspr,
+	[EXCCODE_HYP]		= _kvm_handle_hypcall,
+	[EXCCODE_GCM]		= _kvm_handle_gcm,
+};
+
+int _kvm_handle_fault(struct kvm_vcpu *vcpu, int fault)
+{
+	return _kvm_fault_tables[fault](vcpu);
+}
+
+void _kvm_init_fault(void)
+{
+	int i;
+
+	for (i = 0; i < EXCCODE_INT_START; i++)
+		if (!_kvm_fault_tables[i])
+			_kvm_fault_tables[i] = _kvm_fault_ni;
+}

arch/loongarch/kvm/fpu.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/kernel.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm_para.h>
+#include <asm/fpu.h>
+
+/* FPU/LSX context management */
+void __kvm_save_fpu(struct loongarch_fpu *fpu);
+void __kvm_restore_fpu(struct loongarch_fpu *fpu);
+void __kvm_restore_fcsr(struct loongarch_fpu *fpu);
+
+void kvm_save_fpu(struct kvm_vcpu *cpu)
+{
+	return __kvm_save_fpu(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_save_fpu);
+
+void kvm_restore_fpu(struct kvm_vcpu *cpu)
+{
+	return __kvm_restore_fpu(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_restore_fpu);
+
+void kvm_restore_fcsr(struct kvm_vcpu *cpu)
+{
+	return __kvm_restore_fcsr(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_restore_fcsr);
+
+#ifdef CONFIG_CPU_HAS_LSX
+void __kvm_save_lsx(struct loongarch_fpu *fpu);
+void __kvm_restore_lsx(struct loongarch_fpu *fpu);
+void __kvm_restore_lsx_upper(struct loongarch_fpu *fpu);
+
+void kvm_save_lsx(struct kvm_vcpu *cpu)
+{
+	return __kvm_save_lsx(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_save_lsx);
+
+void kvm_restore_lsx(struct kvm_vcpu *cpu)
+{
+	return __kvm_restore_lsx(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_restore_lsx);
+
+void kvm_restore_lsx_upper(struct kvm_vcpu *cpu)
+{
+	return __kvm_restore_lsx_upper(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_restore_lsx_upper);
+
+#endif
+
+#ifdef CONFIG_CPU_HAS_LSX
+void __kvm_save_lasx(struct loongarch_fpu *fpu);
+void __kvm_restore_lasx(struct loongarch_fpu *fpu);
+void __kvm_restore_lasx_upper(struct loongarch_fpu *fpu);
+
+void kvm_save_lasx(struct kvm_vcpu *cpu)
+{
+	return __kvm_save_lasx(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_save_lasx);
+
+void kvm_restore_lasx(struct kvm_vcpu *cpu)
+{
+	return __kvm_restore_lasx(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_restore_lasx);
+
+void kvm_restore_lasx_upper(struct kvm_vcpu *cpu)
+{
+	return _restore_lasx_upper(&cpu->arch.fpu);
+}
+EXPORT_SYMBOL_GPL(kvm_restore_lasx_upper);
+#endif
+
+EXPORT_SYMBOL_GPL(kvm_enter_guest);
+EXPORT_SYMBOL_GPL(kvm_exception_entry);
+

arch/loongarch/kvm/hypcall.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/kernel.h>
+#include <linux/kvm_host.h>
+#include <linux/sched/stat.h>
+#include <asm/kvm_para.h>
+#include <asm/paravirt.h>
+#include "intc/ls3a_ipi.h"
+
+int kvm_virt_ipi(struct kvm_vcpu *vcpu)
+{
+	int ret = 0;
+	u64 ipi_bitmap;
+	unsigned int min, action, cpu;
+
+	ipi_bitmap = vcpu->arch.gprs[REG_A1];
+	min = vcpu->arch.gprs[REG_A2];
+	action = vcpu->arch.gprs[REG_A3];
+
+	if (ipi_bitmap) {
+		cpu = find_first_bit((void *)&ipi_bitmap, BITS_PER_LONG);
+		while (cpu < BITS_PER_LONG) {
+			kvm_helper_send_ipi(vcpu, cpu + min, action);
+			cpu = find_next_bit((void *)&ipi_bitmap, BITS_PER_LONG, cpu + 1);
+		}
+	}
+
+	return ret;
+}
+
+int kvm_save_notify(struct kvm_vcpu *vcpu)
+{
+	unsigned long num, id, data;
+
+	int ret = 0;
+
+	num = vcpu->arch.gprs[REG_A0];
+	id = vcpu->arch.gprs[REG_A1];
+	data = vcpu->arch.gprs[REG_A2];
+
+	switch (id) {
+	case KVM_FEATURE_STEAL_TIME:
+		if (!sched_info_on())
+			break;
+		vcpu->arch.st.guest_addr = data;
+		kvm_debug("cpu :%d addr:%lx\n", vcpu->vcpu_id, data);
+		vcpu->arch.st.last_steal = current->sched_info.run_delay;
+		kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu);
+		break;
+	default:
+		break;
+	};
+
+	return ret;
+};
+
+static int _kvm_pv_feature(struct kvm_vcpu *vcpu)
+{
+	int feature = vcpu->arch.gprs[REG_A1];
+	int ret = KVM_RET_NOT_SUPPORTED;
+	switch (feature) {
+	case KVM_FEATURE_STEAL_TIME:
+		if (sched_info_on())
+			ret = KVM_RET_SUC;
+		break;
+	case KVM_FEATURE_MULTI_IPI:
+		ret = KVM_RET_SUC;
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+/*
+ * hypcall emulation always return to guest, Caller should check retval.
+ */
+int _kvm_handle_pv_hcall(struct kvm_vcpu *vcpu)
+{
+	unsigned long func = vcpu->arch.gprs[REG_A0];
+	int hyp_ret = KVM_RET_NOT_SUPPORTED;
+
+	switch (func) {
+	case KVM_HC_FUNC_FEATURE:
+		hyp_ret = _kvm_pv_feature(vcpu);
+		break;
+	case KVM_HC_FUNC_NOTIFY:
+		hyp_ret = kvm_save_notify(vcpu);
+		break;
+	case KVM_HC_FUNC_IPI:
+		hyp_ret = kvm_virt_ipi(vcpu);
+		break;
+	default:
+		kvm_info("[%#lx] hvc func:%#lx unsupported\n", vcpu->arch.pc, func);
+		break;
+	};
+
+	vcpu->arch.gprs[REG_V0] = hyp_ret;
+
+	return RESUME_GUEST;
+}

arch/loongarch/kvm/intc/irqchip-debug.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/debugfs.h>
+#include <linux/kvm_host.h>
+#include <linux/seq_file.h>
+#include "kvmcpu.h"
+#include "ls3a_ext_irq.h"
+#include "ls7a_irq.h"
+
+#ifdef CONFIG_DEBUG_FS
+static int irqchip_state_show(struct seq_file *m, void *v)
+{
+	struct kvm *kvm = m->private;
+
+	kvm_get_kvm(kvm);
+	kvm_dump_ls3a_extirq_state(m, kvm->arch.v_extirq);
+	kvm_dump_ls7a_ioapic_state(m, kvm->arch.v_ioapic);
+	kvm_put_kvm(kvm);
+
+	return 0;
+}
+
+static int irqchip_debug_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, irqchip_state_show, inode->i_private);
+}
+
+static const struct file_operations irqchip_debug_fops = {
+	.open       = irqchip_debug_open,
+	.read       = seq_read,
+	.llseek     = seq_lseek,
+	.release    = single_release,
+};
+
+void irqchip_debug_init(struct kvm *kvm)
+{
+	debugfs_create_file("irqchip-state", 0444, kvm->debugfs_dentry, kvm,
+			    &irqchip_debug_fops);
+}
+#else
+
+void irqchip_debug_init(struct kvm *kvm) {}
+#endif
+void irqchip_debug_destroy(struct kvm *kvm)
+{
+}

arch/loongarch/kvm/intc/ls3a_ext_irq.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef __LS3A_KVM_EXT_IRQ_H
+#define __LS3A_KVM_EXT_IRQ_H
+
+#include <linux/mm_types.h>
+#include <linux/hrtimer.h>
+#include <linux/kvm_host.h>
+#include <linux/spinlock.h>
+#include <linux/seq_file.h>
+
+#include <kvm/iodev.h>
+
+#define IOCSR_EXTIOI_ADDR		KVM_IOCSR_EXTIOI_NODEMAP_BASE
+
+#define EXTIOI_ADDR_OFF			0x10000
+#define EXTIOI_REG_BASE			(LOONGSON_VIRT_REG_BASE + EXTIOI_ADDR_OFF)
+#define EXTIOI_REG_END			(EXTIOI_REG_BASE + 0x20000)
+#define EXTIOI_ADDR_SIZE		(EXTIOI_REG_END - EXTIOI_REG_BASE)
+#define EXTIOI_PERCORE_REG_OFF		0x10000
+#define EXTIOI_PERCORE_REG_END		(EXTIOI_PERCORE_REG_OFF + 0x10000)
+
+#define EXTIOI_ADDR(off)		(EXTIOI_REG_BASE + (off) - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_PERCORE_ADDR(id, off) \
+	(EXTIOI_REG_BASE + EXTIOI_PERCORE_REG_OFF + ((id) << 8) + (off))
+
+#define EXTIOI_NODETYPE_START		(KVM_IOCSR_EXTIOI_NODEMAP_BASE - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_NODETYPE_END		(EXTIOI_NODETYPE_START + 0x20)
+#define EXTIOI_IPMAP_START		(KVM_IOCSR_EXTIOI_IPMAP_BASE - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_IPMAP_END		(EXTIOI_IPMAP_START + 0x8)
+#define EXTIOI_ENABLE_START		(KVM_IOCSR_EXTIOI_EN_BASE - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_ENABLE_END		(EXTIOI_ENABLE_START + 0x20)
+#define EXTIOI_BOUNCE_START		(KVM_IOCSR_EXTIOI_BOUNCE_BASE - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_BOUNCE_END		(EXTIOI_BOUNCE_START + 0x20)
+#define EXTIOI_ISR_START		(0x1700 - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_ISR_END			(EXTIOI_ISR_START + 0x20)
+#define EXTIOI_COREMAP_START		(KVM_IOCSR_EXTIOI_ROUTE_BASE - IOCSR_EXTIOI_ADDR)
+#define EXTIOI_COREMAP_END		(EXTIOI_COREMAP_START + 0x100)
+#define EXTIOI_COREISR_START		(EXTIOI_PERCORE_REG_OFF)
+#define EXTIOI_COREISR_END		(EXTIOI_PERCORE_REG_END)
+
+#define LS3A_INTC_IP			8
+#define EXTIOI_IRQS			KVM_EXTIOI_IRQS
+#define EXTIOI_IRQS_BITMAP_SIZE		(EXTIOI_IRQS / 8)
+/* map to ipnum per 32 irqs */
+#define EXTIOI_IRQS_IPMAP_SIZE		(EXTIOI_IRQS / 32)
+#define EXTIOI_IRQS_PER_GROUP		KVM_EXTIOI_IRQS_PER_GROUP
+#define EXTIOI_IRQS_COREMAP_SIZE	(EXTIOI_IRQS)
+#define EXTIOI_IRQS_NODETYPE_SIZE	KVM_EXTIOI_IRQS_NODETYPE_SIZE
+
+typedef struct kvm_ls3a_extirq_state {
+	union ext_en {
+		uint64_t reg_u64[EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[EXTIOI_IRQS_BITMAP_SIZE];
+	} ext_en;
+	union bounce {
+		uint64_t reg_u64[EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[EXTIOI_IRQS_BITMAP_SIZE];
+	} bounce;
+	union ext_isr {
+		uint64_t reg_u64[EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[EXTIOI_IRQS_BITMAP_SIZE];
+	} ext_isr;
+	union ext_core_isr {
+		uint64_t reg_u64[KVM_MAX_VCPUS][EXTIOI_IRQS_BITMAP_SIZE / 8];
+		uint32_t reg_u32[KVM_MAX_VCPUS][EXTIOI_IRQS_BITMAP_SIZE / 4];
+		uint8_t reg_u8[KVM_MAX_VCPUS][EXTIOI_IRQS_BITMAP_SIZE];
+	} ext_core_isr;
+	union ip_map {
+		uint64_t reg_u64;
+		uint32_t reg_u32[EXTIOI_IRQS_IPMAP_SIZE / 4];
+		uint8_t reg_u8[EXTIOI_IRQS_IPMAP_SIZE];
+	} ip_map;
+	union core_map {
+		uint64_t reg_u64[EXTIOI_IRQS_COREMAP_SIZE / 8];
+		uint32_t reg_u32[EXTIOI_IRQS_COREMAP_SIZE / 4];
+		uint8_t reg_u8[EXTIOI_IRQS_COREMAP_SIZE];
+	} core_map;
+	union {
+		uint64_t reg_u64[EXTIOI_IRQS_NODETYPE_SIZE / 4];
+		uint32_t reg_u32[EXTIOI_IRQS_NODETYPE_SIZE / 2];
+		uint16_t reg_u16[EXTIOI_IRQS_NODETYPE_SIZE];
+		uint8_t reg_u8[EXTIOI_IRQS_NODETYPE_SIZE * 2];
+	} node_type;
+
+	/*software state */
+	uint8_t ext_sw_ipmap[EXTIOI_IRQS];
+	uint8_t ext_sw_coremap[EXTIOI_IRQS];
+	uint8_t ext_sw_ipisr[KVM_MAX_VCPUS][LS3A_INTC_IP][EXTIOI_IRQS_BITMAP_SIZE];
+} LS3AExtirqState;
+
+struct ls3a_kvm_extirq {
+	spinlock_t lock;
+	struct kvm *kvm;
+	atomic64_t enabled;
+	struct kvm_io_device device;
+	struct kvm_ls3a_extirq_state ls3a_ext_irq;
+};
+
+static inline struct ls3a_kvm_extirq *ls3a_ext_irqchip(struct kvm *kvm)
+{
+	return kvm->arch.v_extirq;
+}
+
+static inline int ls3a_extirq_in_kernel(struct kvm *kvm)
+{
+	int ret;
+
+	ret = (ls3a_ext_irqchip(kvm) != NULL);
+	return ret;
+}
+
+
+void ext_irq_handler(struct kvm *kvm, int irq, int level);
+int kvm_create_ls3a_ext_irq(struct kvm *kvm);
+int kvm_get_ls3a_extirq(struct kvm *kvm,
+			struct kvm_loongarch_ls3a_extirq_state *state);
+int kvm_set_ls3a_extirq(struct kvm *kvm,
+			struct kvm_loongarch_ls3a_extirq_state *state);
+void kvm_destroy_ls3a_ext_irq(struct kvm *kvm);
+void msi_irq_handler(struct kvm *kvm, int irq, int level);
+int kvm_setup_ls3a_extirq(struct kvm *kvm);
+int kvm_enable_ls3a_extirq(struct kvm *kvm, bool enable);
+void kvm_dump_ls3a_extirq_state(struct seq_file *m, struct ls3a_kvm_extirq *irqchip);
+#endif

arch/loongarch/kvm/intc/ls3a_ipi.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include "kvmcpu.h"
+#include "ls3a_ipi.h"
+#include "ls7a_irq.h"
+#include "ls3a_ext_irq.h"
+
+#define ls3a_gipi_lock(s, flags)	spin_lock_irqsave(&s->lock, flags)
+#define ls3a_gipi_unlock(s, flags)	spin_unlock_irqrestore(&s->lock, flags)
+
+extern int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
+			     struct kvm_loongarch_interrupt *irq);
+int kvm_helper_send_ipi(struct kvm_vcpu *vcpu, unsigned int cpu, unsigned int action)
+{
+	struct kvm *kvm = vcpu->kvm;
+	struct ls3a_kvm_ipi *ipi = ls3a_ipi_irqchip(kvm);
+	gipiState *s = &(ipi->ls3a_gipistate);
+	unsigned long flags;
+	struct kvm_loongarch_interrupt irq;
+
+	kvm->stat.pip_write_exits++;
+
+	ls3a_gipi_lock(ipi, flags);
+	if (s->core[cpu].status == 0) {
+		irq.cpu = cpu;
+		irq.irq = LARCH_INT_IPI;
+		kvm_vcpu_ioctl_interrupt(kvm->vcpus[cpu], &irq);
+	}
+
+	s->core[cpu].status |= action;
+	ls3a_gipi_unlock(ipi, flags);
+
+	return 0;
+}
+
+static int ls3a_gipi_writel(struct ls3a_kvm_ipi *ipi, gpa_t addr,
+						int len, const void *val)
+{
+	uint64_t data, offset;
+	struct kvm_loongarch_interrupt irq;
+	gipiState *s = &(ipi->ls3a_gipistate);
+	uint32_t cpu, action_data;
+	struct kvm *kvm;
+	void *pbuf;
+	int mailbox, action;
+
+	kvm = ipi->kvm;
+	cpu = (addr >> 8) & 0xff;
+
+	data = *(uint64_t *)val;
+	offset = addr & 0xFF;
+
+	BUG_ON(offset & (len - 1));
+
+	switch (offset) {
+	case CORE0_STATUS_OFF:
+		printk("CORE0_SET_OFF Can't be write\n");
+
+		break;
+	case CORE0_EN_OFF:
+		s->core[cpu].en = data;
+
+		break;
+	case CORE0_IPI_SEND:
+		cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
+		action = (data & 0x1f);
+		action_data = (1 << action);
+
+		if (s->core[cpu].status == 0) {
+			irq.cpu = cpu;
+			irq.irq = LARCH_INT_IPI;
+
+			if (likely(kvm->vcpus[cpu])) {
+				kvm_vcpu_ioctl_interrupt(kvm->vcpus[cpu], &irq);
+			}
+		}
+		s->core[cpu].status |= action_data;
+		break;
+	case CORE0_SET_OFF:
+		pr_info("CORE0_SET_OFF simulation is required\n");
+		break;
+	case CORE0_CLEAR_OFF:
+		s->core[cpu].status &= ~data;
+		if (!s->core[cpu].status) {
+			irq.cpu = cpu;
+			irq.irq = -LARCH_INT_IPI;
+			if (likely(kvm->vcpus[cpu]))
+				kvm_vcpu_ioctl_interrupt(kvm->vcpus[cpu], &irq);
+			else
+				kvm_err("Failed lower ipi irq target cpu:%d\n", cpu);
+		}
+
+		break;
+	case CORE0_MAIL_SEND:
+		cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
+		mailbox = ((data & 0xffffffff) >> 2) & 0x7;
+		pbuf =  (void *)s->core[cpu].buf + mailbox * 4;
+
+		*(unsigned int *)pbuf = (unsigned int)(data >> 32);
+		break;
+	case 0x20 ... 0x3c:
+		pbuf =  (void *)s->core[cpu].buf + (offset - 0x20);
+		if (len == 1)
+			*(unsigned char *)pbuf = (unsigned char)data;
+		else if (len == 2)
+			*(unsigned short *)pbuf = (unsigned short)data;
+		else if (len == 4)
+			*(unsigned int *)pbuf = (unsigned int)data;
+		else if (len == 8)
+			*(unsigned long *)pbuf = (unsigned long)data;
+
+		break;
+	default:
+		printk("ls3a_gipi_writel with unknown addr %llx \n", addr);
+		break;
+	}
+	return 0;
+}
+
+static uint64_t ls3a_gipi_readl(struct ls3a_kvm_ipi *ipi,
+				gpa_t addr, int len, void *val)
+{
+	uint64_t offset;
+	uint64_t ret = 0;
+
+	gipiState *s = &(ipi->ls3a_gipistate);
+	uint32_t cpu;
+	void *pbuf;
+
+	cpu = (addr >> 8) & 0xff;
+
+	offset = addr & 0xFF;
+
+	BUG_ON(offset & (len - 1));
+	switch (offset) {
+	case CORE0_STATUS_OFF:
+		ret = s->core[cpu].status;
+		break;
+	case CORE0_EN_OFF:
+		ret = s->core[cpu].en;
+		break;
+	case CORE0_SET_OFF:
+		ret = 0;
+		break;
+	case CORE0_CLEAR_OFF:
+		ret = 0;
+		break;
+	case 0x20 ... 0x3c:
+		pbuf =  (void *)s->core[cpu].buf + (offset - 0x20);
+		if (len == 1)
+			ret  = *(unsigned char *)pbuf;
+		else if (len == 2)
+			ret = *(unsigned short *)pbuf;
+		else if (len == 4)
+			ret = *(unsigned int *)pbuf;
+		else if (len == 8)
+			ret = *(unsigned long *)pbuf;
+		break;
+	default:
+		printk("ls3a_gipi_readl with unknown addr %llx \n", addr);
+		break;
+	}
+
+	*(uint64_t *)val = ret;
+
+	return ret;
+}
+
+static int kvm_ls3a_ipi_write(struct kvm_vcpu *vcpu,
+			      struct kvm_io_device *dev,
+			      gpa_t addr, int len, const void *val)
+{
+	struct ls3a_kvm_ipi *ipi;
+	ipi_io_device *ipi_device;
+	unsigned long flags;
+
+	ipi_device = container_of(dev, ipi_io_device, device);
+	ipi = ipi_device->ipi;
+	ipi->kvm->stat.pip_write_exits++;
+
+	ls3a_gipi_lock(ipi, flags);
+	ls3a_gipi_writel(ipi, addr, len, val);
+	ls3a_gipi_unlock(ipi, flags);
+	return 0;
+}
+
+
+static int kvm_ls3a_ipi_read(struct kvm_vcpu *vcpu,
+			     struct kvm_io_device *dev,
+			     gpa_t addr, int len, void *val)
+{
+	struct ls3a_kvm_ipi *ipi;
+	ipi_io_device *ipi_device;
+	unsigned long flags;
+
+	ipi_device = container_of(dev, ipi_io_device, device);
+	ipi = ipi_device->ipi;
+	ipi->kvm->stat.pip_read_exits++;
+
+	ls3a_gipi_lock(ipi, flags);
+	ls3a_gipi_readl(ipi, addr, len, val);
+	ls3a_gipi_unlock(ipi, flags);
+	return 0;
+}
+
+
+static const struct kvm_io_device_ops kvm_ls3a_ipi_ops = {
+	.read	= kvm_ls3a_ipi_read,
+	.write	= kvm_ls3a_ipi_write,
+};
+
+void kvm_destroy_ls3a_ipi(struct kvm *kvm)
+{
+	struct kvm_io_device *device;
+	struct ls3a_kvm_ipi *vipi = kvm->arch.v_gipi;
+
+	if (!vipi)
+		return;
+	device = &vipi->dev_ls3a_ipi.device;
+	kvm_io_bus_unregister_dev(vipi->kvm, KVM_MMIO_BUS, device);
+	kfree(vipi);
+}
+
+int kvm_create_ls3a_ipi(struct kvm *kvm)
+{
+	struct ls3a_kvm_ipi *s;
+	unsigned long addr;
+	struct kvm_io_device *device;
+	int ret;
+
+	s = kzalloc(sizeof(struct ls3a_kvm_ipi), GFP_KERNEL);
+	if (!s)
+		return -ENOMEM;
+	spin_lock_init(&s->lock);
+	s->kvm = kvm;
+
+	/*
+	 * Initialize MMIO device
+	 */
+	device = &s->dev_ls3a_ipi.device;
+	kvm_iodevice_init(device, &kvm_ls3a_ipi_ops);
+	addr = SMP_MAILBOX;
+	mutex_lock(&kvm->slots_lock);
+	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS,
+			addr, KVM_IOCSR_IPI_ADDR_SIZE, device);
+	mutex_unlock(&kvm->slots_lock);
+	if (ret < 0) {
+		kvm_err("%s Initialize MMIO dev err ret:%d\n", __func__, ret);
+		goto err;
+	} else {
+		s->dev_ls3a_ipi.ipi = s;
+	}
+
+	kvm->arch.v_gipi = s;
+	return 0;
+
+err:
+	kfree(s);
+	return -EFAULT;
+}
+
+int kvm_get_ls3a_ipi(struct kvm *kvm, struct loongarch_gipiState *state)
+{
+	struct ls3a_kvm_ipi *ipi = ls3a_ipi_irqchip(kvm);
+	gipiState *ipi_state =  &(ipi->ls3a_gipistate);
+	unsigned long flags;
+
+	ls3a_gipi_lock(ipi, flags);
+	memcpy(state, ipi_state, sizeof(gipiState));
+	ls3a_gipi_unlock(ipi, flags);
+	return 0;
+}
+
+int kvm_set_ls3a_ipi(struct kvm *kvm, struct loongarch_gipiState *state)
+{
+	struct ls3a_kvm_ipi *ipi = ls3a_ipi_irqchip(kvm);
+	gipiState *ipi_state =  &(ipi->ls3a_gipistate);
+	unsigned long flags;
+
+	if (!ipi)
+		return -EINVAL;
+
+	ls3a_gipi_lock(ipi, flags);
+	memcpy(ipi_state, state, sizeof(gipiState));
+	ls3a_gipi_unlock(ipi, flags);
+	return 0;
+}

arch/loongarch/kvm/intc/ls3a_ipi.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef __LS3A_KVM_IPI_H
+#define __LS3A_KVM_IPI_H
+
+#include <linux/mm_types.h>
+#include <linux/hrtimer.h>
+#include <linux/kvm_host.h>
+#include <linux/spinlock.h>
+#include <kvm/iodev.h>
+
+typedef struct gipi_single {
+	uint32_t status;
+	uint32_t en;
+	uint32_t set;
+	uint32_t clear;
+	uint64_t buf[4];
+} gipi_single;
+
+typedef struct gipiState {
+	gipi_single core[KVM_MAX_VCPUS];
+} gipiState;
+
+struct ls3a_kvm_ipi;
+
+typedef struct ipi_io_device {
+	struct ls3a_kvm_ipi *ipi;
+	struct kvm_io_device device;
+	int nodeNum;
+} ipi_io_device;
+
+struct ls3a_kvm_ipi {
+	spinlock_t lock;
+	struct kvm *kvm;
+	gipiState ls3a_gipistate;
+	int nodeNum;
+	ipi_io_device dev_ls3a_ipi;
+};
+
+#define SMP_MAILBOX			(LOONGSON_VIRT_REG_BASE + 0x0000)
+#define KVM_IPI_REG_ADDRESS(id, off)	(SMP_MAILBOX | (id << 8) | off)
+#define KVM_IOCSR_IPI_ADDR_SIZE		0x10000
+
+#define CORE0_STATUS_OFF	0x000
+#define CORE0_EN_OFF		0x004
+#define CORE0_SET_OFF		0x008
+#define CORE0_CLEAR_OFF		0x00c
+#define CORE0_BUF_20		0x020
+#define CORE0_BUF_28		0x028
+#define CORE0_BUF_30		0x030
+#define CORE0_BUF_38		0x038
+#define CORE0_IPI_SEND		0x040
+#define CORE0_MAIL_SEND		0x048
+
+static inline struct ls3a_kvm_ipi *ls3a_ipi_irqchip(struct kvm *kvm)
+{
+	return kvm->arch.v_gipi;
+}
+
+static inline int ls3a_ipi_in_kernel(struct kvm *kvm)
+{
+	int ret;
+
+	ret = (ls3a_ipi_irqchip(kvm) != NULL);
+	return ret;
+}
+
+int kvm_create_ls3a_ipi(struct kvm *kvm);
+void kvm_destroy_ls3a_ipi(struct kvm *kvm);
+int kvm_set_ls3a_ipi(struct kvm *kvm, struct loongarch_gipiState *state);
+int kvm_get_ls3a_ipi(struct kvm *kvm, struct loongarch_gipiState *state);
+int kvm_helper_send_ipi(struct kvm_vcpu *vcpu, unsigned int cpu, unsigned int action);
+#endif

arch/loongarch/kvm/intc/ls7a_irq.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/highmem.h>
+#include <linux/mm.h>
+#include "ls3a_ipi.h"
+#include "ls7a_irq.h"
+#include "ls3a_ext_irq.h"
+
+void ls7a_ioapic_lock(struct ls7a_kvm_ioapic *s, unsigned long *flags)
+{
+	unsigned long tmp;
+	spin_lock_irqsave(&s->lock, tmp);
+	*flags = tmp;
+}
+
+void ls7a_ioapic_unlock(struct ls7a_kvm_ioapic *s, unsigned long *flags)
+{
+	unsigned long tmp;
+	tmp = *flags;
+	spin_unlock_irqrestore(&s->lock, tmp);
+}
+
+static void kvm_ls7a_ioapic_raise(struct kvm *kvm, unsigned long mask)
+{
+	unsigned long irqnum, val;
+	struct ls7a_kvm_ioapic *s = ls7a_ioapic_irqchip(kvm);
+	struct kvm_ls7a_ioapic_state *state;
+	struct kvm_loongarch_interrupt irq;
+	int i;
+
+	state = &s->ls7a_ioapic;
+	irq.cpu = -1;
+	val = mask & state->intirr & (~state->int_mask);
+	val &= ~state->intisr;
+	for_each_set_bit(i, &val, 64) {
+		state->intisr |= 0x1ULL << i;
+		irqnum = state->htmsi_vector[i];
+		kvm_debug("msi_irq_handler,%ld,up\n", irqnum);
+		msi_irq_handler(kvm, irqnum, 1);
+	}
+
+	kvm->stat.ls7a_ioapic_update++;
+}
+
+static void kvm_ls7a_ioapic_lower(struct kvm *kvm, unsigned long mask)
+{
+	unsigned long irqnum, val;
+	struct ls7a_kvm_ioapic *s = ls7a_ioapic_irqchip(kvm);
+	struct kvm_ls7a_ioapic_state *state;
+	struct kvm_loongarch_interrupt irq;
+	int i;
+
+	state = &s->ls7a_ioapic;
+	irq.cpu = -1;
+	val = mask & state->intisr;
+	for_each_set_bit(i, &val, 64) {
+		state->intisr &= ~(0x1ULL << i);
+		irqnum = state->htmsi_vector[i];
+		kvm_debug("msi_irq_handler,%ld,down\n", irqnum);
+		msi_irq_handler(kvm, irqnum, 0);
+	}
+
+	kvm->stat.ls7a_ioapic_update++;
+}
+
+int kvm_ls7a_set_msi(struct kvm_kernel_irq_routing_entry *e,
+		struct kvm *kvm, int irq_source_id, int level, bool line_status)
+{
+	if (!level)
+		return -1;
+
+	kvm_debug("msi data is 0x%x\n", e->msi.data);
+	msi_irq_handler(kvm, e->msi.data, 1);
+	return 0;
+}
+
+int kvm_ls7a_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi)
+{
+	struct kvm_kernel_irq_routing_entry route;
+
+	if (msi->flags != 0)
+		return -EINVAL;
+
+	kvm->stat.ls7a_msi_irq++;
+	route.msi.address_lo = msi->address_lo;
+	route.msi.address_hi = msi->address_hi;
+	route.msi.data = msi->data;
+
+	kvm_debug("msi data is 0x%x\n", route.msi.data);
+	return kvm_ls7a_set_msi(&route, kvm,
+				KVM_USERSPACE_IRQ_SOURCE_ID, 1, false);
+
+}
+
+int kvm_ls7a_ioapic_set_irq(struct kvm *kvm, int irq, int level)
+{
+	struct ls7a_kvm_ioapic *s;
+	struct kvm_ls7a_ioapic_state *state;
+	uint64_t mask = 1ULL << irq;
+	s = ls7a_ioapic_irqchip(kvm);
+	state = &s->ls7a_ioapic;
+	BUG_ON(irq < 0 || irq >= LS7A_IOAPIC_NUM_PINS);
+
+	if (state->intedge & mask) {
+		/* edge triggered */
+		if (level) {
+			if ((state->last_intirr & mask) == 0) {
+				state->intirr |= mask;
+				kvm_ls7a_ioapic_raise(kvm, mask);
+			}
+			state->last_intirr |= mask;
+		} else
+			state->last_intirr &= ~mask;
+	} else {
+		/* level triggered */
+		if (!!level) {
+			if ((state->intirr & mask) == 0) {
+				state->intirr |= mask;
+				kvm_ls7a_ioapic_raise(kvm, mask);
+			}
+		} else {
+			if (state->intirr & mask) {
+				state->intirr &= ~mask;
+				kvm_ls7a_ioapic_lower(kvm, mask);
+			}
+		}
+	}
+	kvm->stat.ls7a_ioapic_set_irq++;
+	return 0;
+}
+
+static int ls7a_ioapic_reg_write(struct ls7a_kvm_ioapic *s,
+			  gpa_t addr, int len, const void *val)
+{
+	struct kvm *kvm;
+	struct kvm_ls7a_ioapic_state *state;
+	int64_t offset_tmp;
+	uint64_t offset;
+	uint64_t data, old;
+
+	offset = addr & 0xfff;
+	kvm = s->kvm;
+	state = &(s->ls7a_ioapic);
+
+	if (offset & (len - 1)) {
+		printk("%s(%d):unaligned address access %llx size %d \n",
+			__FUNCTION__, __LINE__, addr, len);
+		return 0;
+	}
+
+	if (8 == len) {
+		data = *(uint64_t *)val;
+		switch (offset) {
+		case LS7A_INT_MASK_OFFSET:
+			old = state->int_mask;
+			state->int_mask = data;
+			if (old & ~data)
+				kvm_ls7a_ioapic_raise(kvm, old & ~data);
+			if (~old & data)
+				kvm_ls7a_ioapic_lower(kvm, ~old & data);
+			break;
+		case LS7A_INT_STATUS_OFFSET:
+			state->intisr = data;
+			break;
+		case LS7A_INT_EDGE_OFFSET:
+			state->intedge = data;
+			break;
+		case LS7A_INT_CLEAR_OFFSET:
+			/*
+			 * only clear edge triggered irq on writing INTCLR reg
+			 * no effect on level triggered irq
+			 */
+			data = data & state->intedge;
+			state->intirr &= ~data;
+			kvm_ls7a_ioapic_lower(kvm, data);
+			state->intisr &= (~data);
+			break;
+		case LS7A_INT_POL_OFFSET:
+			state->int_polarity = data;
+			break;
+		case LS7A_HTMSI_EN_OFFSET:
+			state->htmsi_en = data;
+			break;
+		case LS7A_AUTO_CTRL0_OFFSET:
+		case LS7A_AUTO_CTRL1_OFFSET:
+			break;
+		default:
+			WARN_ONCE(1, "Abnormal address access:addr 0x%llx,len %d\n", addr, len);
+			break;
+		}
+	} else if (1 == len) {
+		data = *(unsigned char *)val;
+		if (offset >= LS7A_HTMSI_VEC_OFFSET) {
+			offset_tmp = offset - LS7A_HTMSI_VEC_OFFSET;
+			if (offset_tmp >= 0 && offset_tmp < 64) {
+				state->htmsi_vector[offset_tmp] =
+					(uint8_t)(data & 0xff);
+			}
+		} else if (offset >=  LS7A_ROUTE_ENTRY_OFFSET) {
+			offset_tmp = offset - LS7A_ROUTE_ENTRY_OFFSET;
+			if (offset_tmp >= 0 && offset_tmp < 64) {
+				state->route_entry[offset_tmp] =
+					(uint8_t)(data & 0xff);
+			}
+		} else {
+			WARN_ONCE(1, "Abnormal address access:addr 0x%llx,len %d\n", addr, len);
+		}
+	} else {
+		WARN_ONCE(1, "Abnormal address access:addr 0x%llx,len %d\n", addr, len);
+	}
+	kvm->stat.ioapic_reg_write++;
+	return 0;
+}
+
+static inline struct ls7a_kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
+{
+	return container_of(dev, struct ls7a_kvm_ioapic, dev_ls7a_ioapic);
+}
+
+static int kvm_ls7a_ioapic_write(struct kvm_vcpu *vcpu,
+				 struct kvm_io_device *this,
+				 gpa_t addr, int len, const void *val)
+{
+	struct ls7a_kvm_ioapic *s = to_ioapic(this);
+	unsigned long flags;
+
+	ls7a_ioapic_lock(s->kvm->arch.v_ioapic, &flags);
+	ls7a_ioapic_reg_write(s, addr, len, val);
+	ls7a_ioapic_unlock(s->kvm->arch.v_ioapic, &flags);
+
+	return 0;
+}
+
+static int ls7a_ioapic_reg_read(struct ls7a_kvm_ioapic *s,
+		       gpa_t addr, int len, void *val)
+{
+	uint64_t offset, offset_tmp;
+	struct kvm *kvm;
+	struct kvm_ls7a_ioapic_state *state;
+	uint64_t result = 0;
+
+	state = &(s->ls7a_ioapic);
+	kvm = s->kvm;
+	offset = addr & 0xfff;
+	if (offset & (len - 1)) {
+		printk("%s(%d):unaligned address access %llx size %d \n",
+			__FUNCTION__, __LINE__, addr, len);
+		return 0;
+	}
+
+	if (8 == len) {
+		switch (offset) {
+		case LS7A_INT_MASK_OFFSET:
+			result = state->int_mask;
+			break;
+		case LS7A_INT_STATUS_OFFSET:
+			result = state->intisr & (~state->int_mask);
+			break;
+		case LS7A_INT_EDGE_OFFSET:
+			result = state->intedge;
+			break;
+		case LS7A_INT_POL_OFFSET:
+			result = state->int_polarity;
+			break;
+		case LS7A_HTMSI_EN_OFFSET:
+			result = state->htmsi_en;
+			break;
+		case LS7A_AUTO_CTRL0_OFFSET:
+		case LS7A_AUTO_CTRL1_OFFSET:
+			break;
+		case LS7A_INT_ID_OFFSET:
+			result = LS7A_INT_ID_VER;
+			result = (result << 32) + LS7A_INT_ID_VAL;
+			break;
+		default:
+			WARN_ONCE(1, "Abnormal address access:addr 0x%llx,len %d\n", addr, len);
+			break;
+		}
+		if (val != NULL)
+			*(uint64_t *)val = result;
+	} else if (1 == len) {
+		if (offset >= LS7A_HTMSI_VEC_OFFSET) {
+			offset_tmp = offset - LS7A_HTMSI_VEC_OFFSET;
+			if (offset_tmp >= 0 && offset_tmp < 64) {
+				result = state->htmsi_vector[offset_tmp];
+			}
+		} else if (offset >=  LS7A_ROUTE_ENTRY_OFFSET) {
+			offset_tmp = offset - LS7A_ROUTE_ENTRY_OFFSET;
+			if (offset_tmp >= 0 && offset_tmp < 64) {
+				result = state->route_entry[offset_tmp];
+			}
+		} else {
+			WARN_ONCE(1, "Abnormal address access:addr 0x%llx,len %d\n", addr, len);
+		}
+		if (val != NULL)
+			*(unsigned char *)val = result;
+	} else {
+		WARN_ONCE(1, "Abnormal address access:addr 0x%llx,len %d\n", addr, len);
+	}
+	kvm->stat.ioapic_reg_read++;
+	return result;
+}
+
+static int kvm_ls7a_ioapic_read(struct kvm_vcpu *vcpu,
+				struct kvm_io_device *this,
+				gpa_t addr, int len, void *val)
+{
+	struct ls7a_kvm_ioapic *s = to_ioapic(this);
+	unsigned long flags;
+	uint64_t result = 0;
+
+	ls7a_ioapic_lock(s->kvm->arch.v_ioapic, &flags);
+	result = ls7a_ioapic_reg_read(s, addr, len, val);
+	ls7a_ioapic_unlock(s->kvm->arch.v_ioapic, &flags);
+	return 0;
+}
+
+static const struct kvm_io_device_ops kvm_ls7a_ioapic_ops = {
+	.read     = kvm_ls7a_ioapic_read,
+	.write    = kvm_ls7a_ioapic_write,
+};
+
+static int kvm_ls7a_ioapic_alias_read(struct kvm_vcpu *vcpu,
+		struct kvm_io_device *this, gpa_t addr, int len, void *val)
+{
+	struct ls7a_kvm_ioapic *s;
+	unsigned long flags;
+
+	s = container_of(this, struct ls7a_kvm_ioapic, ls7a_ioapic_alias);
+	ls7a_ioapic_lock(s->kvm->arch.v_ioapic, &flags);
+	ls7a_ioapic_reg_read(s, addr, len, val);
+	ls7a_ioapic_unlock(s->kvm->arch.v_ioapic, &flags);
+	return 0;
+}
+
+static int kvm_ls7a_ioapic_alias_write(struct kvm_vcpu *vcpu,
+		struct kvm_io_device *this, gpa_t addr, int len, const void *val)
+{
+	struct ls7a_kvm_ioapic *s;
+	unsigned long flags;
+
+	s = container_of(this, struct ls7a_kvm_ioapic, ls7a_ioapic_alias);
+	ls7a_ioapic_lock(s->kvm->arch.v_ioapic, &flags);
+	ls7a_ioapic_reg_write(s, addr, len, val);
+	ls7a_ioapic_unlock(s->kvm->arch.v_ioapic, &flags);
+
+	return 0;
+}
+
+static const struct kvm_io_device_ops kvm_ls7a_ioapic_ops_alias = {
+	.read     = kvm_ls7a_ioapic_alias_read,
+	.write    = kvm_ls7a_ioapic_alias_write,
+};
+
+int kvm_create_ls7a_ioapic(struct kvm *kvm)
+{
+	struct ls7a_kvm_ioapic *s;
+	int ret;
+	unsigned long ls7a_ioapic_reg_base;
+
+	s = kzalloc(sizeof(struct ls7a_kvm_ioapic), GFP_KERNEL);
+	if (!s)
+		return -ENOMEM;
+	spin_lock_init(&s->lock);
+	s->kvm = kvm;
+
+	ls7a_ioapic_reg_base = LS7A_IOAPIC_GUEST_REG_BASE;
+
+	/*
+	 * Initialize MMIO device
+	 */
+	kvm_iodevice_init(&s->dev_ls7a_ioapic, &kvm_ls7a_ioapic_ops);
+	mutex_lock(&kvm->slots_lock);
+	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ls7a_ioapic_reg_base,
+						   0x1000, &s->dev_ls7a_ioapic);
+	if (ret < 0) {
+		kvm_err("Failed register ioapic, err:%d\n", ret);
+		goto fail_unlock;
+	}
+
+	ls7a_ioapic_reg_base = LS7A_IOAPIC_GUEST_REG_BASE_ALIAS;
+	kvm_iodevice_init(&s->ls7a_ioapic_alias, &kvm_ls7a_ioapic_ops_alias);
+	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ls7a_ioapic_reg_base,
+						0x1000, &s->ls7a_ioapic_alias);
+	if (ret < 0) {
+		kvm_err("Failed register alias ioapic, err:%d\n", ret);
+		kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
+				&s->dev_ls7a_ioapic);
+		goto fail_unlock;
+	}
+	mutex_unlock(&kvm->slots_lock);
+
+	kvm->arch.v_ioapic = s;
+
+	return 0;
+
+fail_unlock:
+	mutex_unlock(&kvm->slots_lock);
+	kfree(s);
+
+	return -EFAULT;
+}
+
+
+int kvm_get_ls7a_ioapic(struct kvm *kvm, struct ls7a_ioapic_state *state)
+{
+	struct ls7a_kvm_ioapic *ls7a_ioapic = ls7a_ioapic_irqchip(kvm);
+	struct kvm_ls7a_ioapic_state *ioapic_state =
+					    &(ls7a_ioapic->ls7a_ioapic);
+	unsigned long flags;
+
+	ls7a_ioapic_lock(ls7a_ioapic, &flags);
+	memcpy(state, ioapic_state, sizeof(struct kvm_ls7a_ioapic_state));
+	ls7a_ioapic_unlock(ls7a_ioapic, &flags);
+	kvm->stat.get_ls7a_ioapic++;
+	return 0;
+}
+
+int kvm_set_ls7a_ioapic(struct kvm *kvm, struct ls7a_ioapic_state *state)
+{
+	struct ls7a_kvm_ioapic *ls7a_ioapic = ls7a_ioapic_irqchip(kvm);
+	struct kvm_ls7a_ioapic_state *ioapic_state =
+					    &(ls7a_ioapic->ls7a_ioapic);
+	unsigned long flags;
+
+	if (!ls7a_ioapic)
+		return -EINVAL;
+
+	ls7a_ioapic_lock(ls7a_ioapic, &flags);
+	memcpy(ioapic_state, state, sizeof(struct kvm_ls7a_ioapic_state));
+	ls7a_ioapic_unlock(ls7a_ioapic, &flags);
+	kvm->stat.set_ls7a_ioapic++;
+	return 0;
+}
+
+void kvm_destroy_ls7a_ioapic(struct kvm *kvm)
+{
+	struct ls7a_kvm_ioapic *vpic = kvm->arch.v_ioapic;
+	if (!vpic)
+		return;
+	kvm_io_bus_unregister_dev(vpic->kvm, KVM_MMIO_BUS,
+					&vpic->ls7a_ioapic_alias);
+	kvm_io_bus_unregister_dev(vpic->kvm, KVM_MMIO_BUS,
+					&vpic->dev_ls7a_ioapic);
+	kfree(vpic);
+}
+
+void kvm_dump_ls7a_ioapic_state(struct seq_file *m,
+		struct ls7a_kvm_ioapic *ioapic)
+{
+	struct kvm_ls7a_ioapic_state *ioapic_state;
+	unsigned long flags;
+	int i = 0;
+
+	if (!ioapic)
+		return;
+
+	seq_puts(m, "\nIOAPIC state:\n");
+	ioapic_state = &(ioapic->ls7a_ioapic);
+
+	ls7a_ioapic_lock(ioapic, &flags);
+	seq_puts(m, "irq masked: ");
+	for (i = 0; i < 64; i++) {
+		if (!test_bit(i, (void *)&ioapic_state->int_mask))
+			seq_printf(m, "%d ", i);
+	}
+	seq_printf(m, "\nhtmsi_en:0x%016llx\n"
+			"intedge:0x%016llx",
+			ioapic_state->htmsi_en,
+			ioapic_state->intedge);
+
+	seq_puts(m, "\nroute_entry: ");
+	for (i = 0; i < 64; i++)
+		seq_printf(m, "%d ", ioapic_state->route_entry[i]);
+
+	seq_puts(m, "\nhtmsi_vector: ");
+	for (i = 0; i < 64; i++)
+		seq_printf(m, "%d ", ioapic_state->htmsi_vector[i]);
+
+	seq_printf(m, "\nintirr:%016llx\n"
+			"intisr:%016llx\n",
+			ioapic_state->intirr,
+			ioapic_state->intisr);
+	ls7a_ioapic_unlock(ioapic, &flags);
+}

arch/loongarch/kvm/intc/ls7a_irq.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef __LS7A_KVM_IRQ_H
+#define __LS7A_KVM_IRQ_H
+
+#include <linux/mm_types.h>
+#include <linux/hrtimer.h>
+#include <linux/kvm_host.h>
+#include <linux/spinlock.h>
+#include <loongson-pch.h>
+#include <linux/seq_file.h>
+#include "kvmcpu.h"
+
+#include <kvm/iodev.h>
+
+#define LS7A_APIC_NUM_PINS	64
+
+#define LS7A_ROUTE_ENTRY_OFFSET	0x100
+#define LS7A_INT_ID_OFFSET	0x0
+#define LS7A_INT_ID_VAL		0x7000000UL
+#define LS7A_INT_ID_VER		0x1f0001UL
+#define LS7A_INT_MASK_OFFSET	0x20
+#define LS7A_INT_EDGE_OFFSET	0x60
+#define LS7A_INT_CLEAR_OFFSET	0x80
+#define LS7A_INT_STATUS_OFFSET	0x3a0
+#define LS7A_INT_POL_OFFSET	0x3e0
+#define LS7A_HTMSI_EN_OFFSET	0x40
+#define LS7A_HTMSI_VEC_OFFSET	0x200
+#define LS7A_AUTO_CTRL0_OFFSET	0xc0
+#define LS7A_AUTO_CTRL1_OFFSET	0xe0
+
+#define LS7A_IOAPIC_GUEST_REG_BASE		0x10000000UL
+#define LS7A_IOAPIC_GUEST_REG_BASE_ALIAS	0xe0010000000UL
+
+#define LS7A_IOAPIC_NUM_PINS			32
+
+typedef struct kvm_ls7a_ioapic_state {
+	u64 int_id;
+	/* 0x020 interrupt mask register */
+	u64 int_mask;
+	/* 0x040 1=msi */
+	u64 htmsi_en;
+	/* 0x060 edge=1 level  =0 */
+	u64 intedge;
+	/* 0x080 for clean edge int,set 1 clean,set 0 is noused */
+	u64 intclr;
+	/* 0x0c0 */
+	u64 auto_crtl0;
+	/* 0x0e0 */
+	u64 auto_crtl1;
+	/* 0x100 - 0x140 */
+	u8 route_entry[64];
+	/* 0x200 - 0x240 */
+	u8 htmsi_vector[64];
+	/* 0x300 */
+	u64 intisr_chip0;
+	/* 0x320 */
+	u64 intisr_chip1;
+	/* edge detection */
+	u64 last_intirr;
+	/* 0x380 interrupt request register */
+	u64 intirr;
+	/* 0x3a0 interrupt service register */
+	u64 intisr;
+	/* 0x3e0 interrupt level polarity selection register,
+	 * 0 for high level tirgger
+	 */
+	u64 int_polarity;
+} LS7AApicState;
+
+struct ls7a_kvm_ioapic {
+	spinlock_t lock;
+	bool wakeup_needed;
+	unsigned pending_acks;
+	struct kvm *kvm;
+	struct kvm_ls7a_ioapic_state ls7a_ioapic;
+	struct kvm_io_device dev_ls7a_ioapic;
+	struct kvm_io_device ls7a_ioapic_alias;
+	void (*ack_notifier)(void *opaque, int irq);
+	unsigned long irq_states[LS7A_APIC_NUM_PINS];
+};
+
+static inline struct ls7a_kvm_ioapic *ls7a_ioapic_irqchip(struct kvm *kvm)
+{
+	return kvm->arch.v_ioapic;
+}
+
+static inline int ls7a_ioapic_in_kernel(struct kvm *kvm)
+{
+	int ret;
+
+	ret = (ls7a_ioapic_irqchip(kvm) != NULL);
+	return ret;
+}
+
+int kvm_set_ls7a_ioapic(struct kvm *kvm, struct ls7a_ioapic_state *state);
+int kvm_get_ls7a_ioapic(struct kvm *kvm, struct ls7a_ioapic_state *state);
+int kvm_create_ls7a_ioapic(struct kvm *kvm);
+void kvm_destroy_ls7a_ioapic(struct kvm *kvm);
+int kvm_ls7a_ioapic_set_irq(struct kvm *kvm, int irq, int level);
+
+void ls7a_ioapic_lock(struct ls7a_kvm_ioapic *s, unsigned long *flags);
+void ls7a_ioapic_unlock(struct ls7a_kvm_ioapic *s, unsigned long *flags);
+int kvm_ls7a_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
+int kvm_ls7a_set_msi(struct kvm_kernel_irq_routing_entry *e, struct kvm *kvm,
+					int irq_source_id, int level, bool line_status);
+
+void kvm_dump_ls7a_ioapic_state(struct seq_file *m, struct ls7a_kvm_ioapic *ioapic);
+#endif

arch/loongarch/kvm/interrupt.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+#include <asm/cacheflush.h>
+#include "kvmcpu.h"
+#include <linux/kvm_host.h>
+#include "kvm_compat.h"
+
+static u32 int_to_coreint[LOONGARCH_EXC_MAX] = {
+	[LARCH_INT_TIMER]	= CPU_TIMER,
+	[LARCH_INT_IPI]		= CPU_IPI,
+	[LARCH_INT_SIP0]	= CPU_SIP0,
+	[LARCH_INT_SIP1]	= CPU_SIP1,
+	[LARCH_INT_IP0]		= CPU_IP0,
+	[LARCH_INT_IP1]		= CPU_IP1,
+	[LARCH_INT_IP2]		= CPU_IP2,
+	[LARCH_INT_IP3]		= CPU_IP3,
+	[LARCH_INT_IP4]		= CPU_IP4,
+	[LARCH_INT_IP5]		= CPU_IP5,
+	[LARCH_INT_IP6]		= CPU_IP6,
+	[LARCH_INT_IP7]		= CPU_IP7,
+};
+
+static int _kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority)
+{
+	unsigned int irq = 0;
+
+	clear_bit(priority, &vcpu->arch.irq_pending);
+	if (priority < LOONGARCH_EXC_MAX)
+		irq = int_to_coreint[priority];
+
+	switch (priority) {
+	case LARCH_INT_TIMER:
+	case LARCH_INT_IPI:
+	case LARCH_INT_SIP0:
+	case LARCH_INT_SIP1:
+		kvm_set_gcsr_estat(irq);
+		break;
+
+	case LARCH_INT_IP0:
+	case LARCH_INT_IP1:
+	case LARCH_INT_IP2:
+	case LARCH_INT_IP3:
+	case LARCH_INT_IP4:
+	case LARCH_INT_IP5:
+	case LARCH_INT_IP6:
+	case LARCH_INT_IP7:
+		kvm_set_csr_gintc(irq);
+		break;
+
+	default:
+		break;
+	}
+
+	return 1;
+}
+
+static int _kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority)
+{
+	unsigned int irq = 0;
+
+	clear_bit(priority, &vcpu->arch.irq_clear);
+	if (priority < LOONGARCH_EXC_MAX)
+		irq = int_to_coreint[priority];
+
+	switch (priority) {
+	case LARCH_INT_TIMER:
+	case LARCH_INT_IPI:
+	case LARCH_INT_SIP0:
+	case LARCH_INT_SIP1:
+		kvm_clear_gcsr_estat(irq);
+		break;
+
+	case LARCH_INT_IP0:
+	case LARCH_INT_IP1:
+	case LARCH_INT_IP2:
+	case LARCH_INT_IP3:
+	case LARCH_INT_IP4:
+	case LARCH_INT_IP5:
+	case LARCH_INT_IP6:
+	case LARCH_INT_IP7:
+		kvm_clear_csr_gintc(irq);
+		break;
+
+	default:
+		break;
+	}
+
+	return 1;
+}
+
+void _kvm_deliver_intr(struct kvm_vcpu *vcpu)
+{
+	unsigned long *pending = &vcpu->arch.irq_pending;
+	unsigned long *pending_clr = &vcpu->arch.irq_clear;
+	unsigned int priority;
+
+	if (!(*pending) && !(*pending_clr))
+		return;
+
+	if (*pending_clr) {
+		priority = __ffs(*pending_clr);
+		while (priority <= LOONGARCH_EXC_IPNUM) {
+			_kvm_irq_clear(vcpu, priority);
+			priority = find_next_bit(pending_clr,
+					BITS_PER_BYTE * sizeof(*pending_clr),
+					priority + 1);
+		}
+	}
+
+	if (*pending) {
+		priority = __ffs(*pending);
+		while (priority <= LOONGARCH_EXC_IPNUM) {
+			_kvm_irq_deliver(vcpu, priority);
+			priority = find_next_bit(pending,
+					BITS_PER_BYTE * sizeof(*pending),
+					priority + 1);
+		}
+	}
+
+}
+
+int _kvm_pending_timer(struct kvm_vcpu *vcpu)
+{
+	return test_bit(LARCH_INT_TIMER, &vcpu->arch.irq_pending);
+}

arch/loongarch/kvm/ls_irq.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef __LOONGHARCH_KVM_IRQ_H__
+#define __LOONGHARCH_KVM_IRQ_H__
+
+static inline int irqchip_in_kernel(struct kvm *kvm)
+{
+	return kvm->arch.v_ioapic ? 1 : 0;
+}
+
+#endif