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提交 8d759bec 编写于 作者: L Longfang Liu 提交者： Herbert Xu
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crypto: hisilicon/sec - fixes some driver coding style 

cleanup static check errors for SEC
Signed-off-by: NLongfang Liu <liulongfang@huawei.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
上级 a44dce50
隐藏空白更改
内联 并排
Showing with 76 addition and 55 deletion
drivers/crypto/hisilicon/sec2/sec_main.c
浏览文件 @ 8d759bec
...@@ -35,15 +35,13 @@ ...@@ -35,15 +35,13 @@
#define SEC_CTX_Q_NUM_MAX 32 #define SEC_CTX_Q_NUM_MAX 32
#define SEC_CTRL_CNT_CLR_CE 0x301120 #define SEC_CTRL_CNT_CLR_CE 0x301120
#define SEC_CTRL_CNT_CLR_CE_BIT BIT(0) #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
#define SEC_ENGINE_PF_CFG_OFF 0x300000
#define SEC_ACC_COMMON_REG_OFF 0x1000
#define SEC_CORE_INT_SOURCE 0x301010 #define SEC_CORE_INT_SOURCE 0x301010
#define SEC_CORE_INT_MASK 0x301000 #define SEC_CORE_INT_MASK 0x301000
#define SEC_CORE_INT_STATUS 0x301008 #define SEC_CORE_INT_STATUS 0x301008
#define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
#define SEC_ECC_NUM(err) (((err) >> 16) & 0xFF) #define SEC_ECC_NUM 16
#define SEC_ECC_ADDR(err) ((err) >> 0) #define SEC_ECC_MASH 0xFF
#define SEC_CORE_INT_DISABLE 0x0 #define SEC_CORE_INT_DISABLE 0x0
#define SEC_CORE_INT_ENABLE 0x1ff #define SEC_CORE_INT_ENABLE 0x1ff
#define SEC_CORE_INT_CLEAR 0x1ff #define SEC_CORE_INT_CLEAR 0x1ff
...@@ -55,23 +53,23 @@ ...@@ -55,23 +53,23 @@
#define SEC_RAS_CE_ENB_MSK 0x88 #define SEC_RAS_CE_ENB_MSK 0x88
#define SEC_RAS_FE_ENB_MSK 0x0 #define SEC_RAS_FE_ENB_MSK 0x0
#define SEC_RAS_NFE_ENB_MSK 0x177 #define SEC_RAS_NFE_ENB_MSK 0x177
#define SEC_RAS_DISABLE 0x0 #define SEC_RAS_DISABLE 0x0
#define SEC_MEM_START_INIT_REG 0x0100 #define SEC_MEM_START_INIT_REG 0x301100
#define SEC_MEM_INIT_DONE_REG 0x0104 #define SEC_MEM_INIT_DONE_REG 0x301104
#define SEC_CONTROL_REG 0x0200 #define SEC_CONTROL_REG 0x301200
#define SEC_TRNG_EN_SHIFT 8 #define SEC_TRNG_EN_SHIFT 8
#define SEC_CLK_GATE_ENABLE BIT(3) #define SEC_CLK_GATE_ENABLE BIT(3)
#define SEC_CLK_GATE_DISABLE (~BIT(3)) #define SEC_CLK_GATE_DISABLE (~BIT(3))
#define SEC_AXI_SHUTDOWN_ENABLE BIT(12) #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
#define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
#define SEC_INTERFACE_USER_CTRL0_REG 0x0220 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
#define SEC_INTERFACE_USER_CTRL1_REG 0x0224 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
#define SEC_SAA_EN_REG 0x0270 #define SEC_SAA_EN_REG 0x301270
#define SEC_BD_ERR_CHK_EN_REG0 0x0380 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
#define SEC_BD_ERR_CHK_EN_REG1 0x0384 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
#define SEC_BD_ERR_CHK_EN_REG3 0x038c #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
#define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15)) #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
#define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7)) #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
...@@ -95,9 +93,6 @@ ...@@ -95,9 +93,6 @@
#define SEC_SQE_MASK_OFFSET 64 #define SEC_SQE_MASK_OFFSET 64
#define SEC_SQE_MASK_LEN 48 #define SEC_SQE_MASK_LEN 48
#define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \
SEC_ENGINE_PF_CFG_OFF + SEC_ACC_COMMON_REG_OFF)
struct sec_hw_error { struct sec_hw_error {
u32 int_msk; u32 int_msk;
const char *msg; const char *msg;
...@@ -117,16 +112,43 @@ static struct hisi_qm_list sec_devices = { ...@@ -117,16 +112,43 @@ static struct hisi_qm_list sec_devices = {
}; };
static const struct sec_hw_error sec_hw_errors[] = { static const struct sec_hw_error sec_hw_errors[] = {
{.int_msk = BIT(0), .msg = "sec_axi_rresp_err_rint"}, {
{.int_msk = BIT(1), .msg = "sec_axi_bresp_err_rint"}, .int_msk = BIT(0),
{.int_msk = BIT(2), .msg = "sec_ecc_2bit_err_rint"}, .msg = "sec_axi_rresp_err_rint"
{.int_msk = BIT(3), .msg = "sec_ecc_1bit_err_rint"}, },
{.int_msk = BIT(4), .msg = "sec_req_trng_timeout_rint"}, {
{.int_msk = BIT(5), .msg = "sec_fsm_hbeat_rint"}, .int_msk = BIT(1),
{.int_msk = BIT(6), .msg = "sec_channel_req_rng_timeout_rint"}, .msg = "sec_axi_bresp_err_rint"
{.int_msk = BIT(7), .msg = "sec_bd_err_rint"}, },
{.int_msk = BIT(8), .msg = "sec_chain_buff_err_rint"}, {
{ /* sentinel */ } .int_msk = BIT(2),
.msg = "sec_ecc_2bit_err_rint"
},
{
.int_msk = BIT(3),
.msg = "sec_ecc_1bit_err_rint"
},
{
.int_msk = BIT(4),
.msg = "sec_req_trng_timeout_rint"
},
{
.int_msk = BIT(5),
.msg = "sec_fsm_hbeat_rint"
},
{
.int_msk = BIT(6),
.msg = "sec_channel_req_rng_timeout_rint"
},
{
.int_msk = BIT(7),
.msg = "sec_bd_err_rint"
},
{
.int_msk = BIT(8),
.msg = "sec_chain_buff_err_rint"
},
{}
}; };
static const char * const sec_dbg_file_name[] = { static const char * const sec_dbg_file_name[] = {
...@@ -277,9 +299,7 @@ static u8 sec_get_endian(struct hisi_qm *qm) ...@@ -277,9 +299,7 @@ static u8 sec_get_endian(struct hisi_qm *qm)
"cannot access a register in VF!\n"); "cannot access a register in VF!\n");
return SEC_LE; return SEC_LE;
} }
reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF + reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
SEC_ACC_COMMON_REG_OFF + SEC_CONTROL_REG);
/* BD little endian mode */ /* BD little endian mode */
if (!(reg & BIT(0))) if (!(reg & BIT(0)))
return SEC_LE; return SEC_LE;
...@@ -299,13 +319,13 @@ static int sec_engine_init(struct hisi_qm *qm) ...@@ -299,13 +319,13 @@ static int sec_engine_init(struct hisi_qm *qm)
u32 reg; u32 reg;
/* disable clock gate control */ /* disable clock gate control */
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
reg &= SEC_CLK_GATE_DISABLE; reg &= SEC_CLK_GATE_DISABLE;
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
writel_relaxed(0x1, SEC_ADDR(qm, SEC_MEM_START_INIT_REG)); writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
ret = readl_relaxed_poll_timeout(SEC_ADDR(qm, SEC_MEM_INIT_DONE_REG), ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
reg, reg & 0x1, SEC_DELAY_10_US, reg, reg & 0x1, SEC_DELAY_10_US,
SEC_POLL_TIMEOUT_US); SEC_POLL_TIMEOUT_US);
if (ret) { if (ret) {
...@@ -313,40 +333,40 @@ static int sec_engine_init(struct hisi_qm *qm) ...@@ -313,40 +333,40 @@ static int sec_engine_init(struct hisi_qm *qm)
return ret; return ret;
} }
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
reg |= (0x1 << SEC_TRNG_EN_SHIFT); reg |= (0x1 << SEC_TRNG_EN_SHIFT);
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG)); reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL0_REG);
reg |= SEC_USER0_SMMU_NORMAL; reg |= SEC_USER0_SMMU_NORMAL;
writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG)); writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL0_REG);
reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG)); reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL1_REG);
reg &= SEC_USER1_SMMU_MASK; reg &= SEC_USER1_SMMU_MASK;
if (qm->use_sva && qm->ver == QM_HW_V2) if (qm->use_sva && qm->ver == QM_HW_V2)
reg |= SEC_USER1_SMMU_SVA; reg |= SEC_USER1_SMMU_SVA;
else else
reg |= SEC_USER1_SMMU_NORMAL; reg |= SEC_USER1_SMMU_NORMAL;
writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG)); writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG);
writel(SEC_SINGLE_PORT_MAX_TRANS, writel(SEC_SINGLE_PORT_MAX_TRANS,
qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
writel(SEC_SAA_ENABLE, SEC_ADDR(qm, SEC_SAA_EN_REG)); writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);
/* Enable sm4 extra mode, as ctr/ecb */ /* Enable sm4 extra mode, as ctr/ecb */
writel_relaxed(SEC_BD_ERR_CHK_EN0, writel_relaxed(SEC_BD_ERR_CHK_EN0,
SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG0)); qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
/* Enable sm4 xts mode multiple iv */ /* Enable sm4 xts mode multiple iv */
writel_relaxed(SEC_BD_ERR_CHK_EN1, writel_relaxed(SEC_BD_ERR_CHK_EN1,
SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG1)); qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
writel_relaxed(SEC_BD_ERR_CHK_EN3, writel_relaxed(SEC_BD_ERR_CHK_EN3,
SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG3)); qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
/* config endian */ /* config endian */
reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
reg |= sec_get_endian(qm); reg |= sec_get_endian(qm);
writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
return 0; return 0;
} }
...@@ -406,7 +426,7 @@ static void sec_hw_error_enable(struct hisi_qm *qm) ...@@ -406,7 +426,7 @@ static void sec_hw_error_enable(struct hisi_qm *qm)
return; return;
} }
val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); val = readl(qm->io_base + SEC_CONTROL_REG);
/* clear SEC hw error source if having */ /* clear SEC hw error source if having */
writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE); writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE);
...@@ -422,14 +442,14 @@ static void sec_hw_error_enable(struct hisi_qm *qm) ...@@ -422,14 +442,14 @@ static void sec_hw_error_enable(struct hisi_qm *qm)
/* enable SEC block master OOO when m-bit error occur */ /* enable SEC block master OOO when m-bit error occur */
val = val | SEC_AXI_SHUTDOWN_ENABLE; val = val | SEC_AXI_SHUTDOWN_ENABLE;
writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); writel(val, qm->io_base + SEC_CONTROL_REG);
} }
static void sec_hw_error_disable(struct hisi_qm *qm) static void sec_hw_error_disable(struct hisi_qm *qm)
{ {
u32 val; u32 val;
val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); val = readl(qm->io_base + SEC_CONTROL_REG);
/* disable RAS int */ /* disable RAS int */
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
...@@ -442,7 +462,7 @@ static void sec_hw_error_disable(struct hisi_qm *qm) ...@@ -442,7 +462,7 @@ static void sec_hw_error_disable(struct hisi_qm *qm)
/* disable SEC block master OOO when m-bit error occur */ /* disable SEC block master OOO when m-bit error occur */
val = val & SEC_AXI_SHUTDOWN_DISABLE; val = val & SEC_AXI_SHUTDOWN_DISABLE;
writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); writel(val, qm->io_base + SEC_CONTROL_REG);
} }
static u32 sec_current_qm_read(struct sec_debug_file *file) static u32 sec_current_qm_read(struct sec_debug_file *file)
...@@ -712,7 +732,8 @@ static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) ...@@ -712,7 +732,8 @@ static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
err_val = readl(qm->io_base + err_val = readl(qm->io_base +
SEC_CORE_SRAM_ECC_ERR_INFO); SEC_CORE_SRAM_ECC_ERR_INFO);
dev_err(dev, "multi ecc sram num=0x%x\n", dev_err(dev, "multi ecc sram num=0x%x\n",
SEC_ECC_NUM(err_val)); ((err_val) >> SEC_ECC_NUM) &
SEC_ECC_MASH);
} }
} }
errs++; errs++;
...@@ -733,9 +754,9 @@ static void sec_open_axi_master_ooo(struct hisi_qm *qm) ...@@ -733,9 +754,9 @@ static void sec_open_axi_master_ooo(struct hisi_qm *qm)
{ {
u32 val; u32 val;
val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); val = readl(qm->io_base + SEC_CONTROL_REG);
writel(val & SEC_AXI_SHUTDOWN_DISABLE, SEC_ADDR(qm, SEC_CONTROL_REG)); writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
writel(val | SEC_AXI_SHUTDOWN_ENABLE, SEC_ADDR(qm, SEC_CONTROL_REG)); writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
} }
static const struct hisi_qm_err_ini sec_err_ini = { static const struct hisi_qm_err_ini sec_err_ini = {
......
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