staging: ccree: remove ccree staging driver copy

The ccree driver is now in the cryptodev tree, so remove it from
drivers/staging as it's no longer needed here.

Based on a patch from Gilad, but the mailing list didn't like it :(
Signed-off-by: NGilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/staging/Kconfig

@@ -114,8 +114,6 @@ source "drivers/staging/greybus/Kconfig"
 
 source "drivers/staging/vc04_services/Kconfig"
 
-source "drivers/staging/ccree/Kconfig"
-
 source "drivers/staging/typec/Kconfig"
 
 source "drivers/staging/vboxvideo/Kconfig"

drivers/staging/Makefile

@@ -49,6 +49,5 @@ obj-$(CONFIG_MOST)		+= most/
 obj-$(CONFIG_KS7010)		+= ks7010/
 obj-$(CONFIG_GREYBUS)		+= greybus/
 obj-$(CONFIG_BCM2835_VCHIQ)	+= vc04_services/
-obj-$(CONFIG_CRYPTO_DEV_CCREE)	+= ccree/
 obj-$(CONFIG_DRM_VBOXVIDEO)	+= vboxvideo/
 obj-$(CONFIG_PI433)		+= pi433/

drivers/staging/ccree/Kconfig

-# SPDX-License-Identifier: GPL-2.0
-
-config CRYPTO_DEV_CCREE
-	tristate "Support for ARM TrustZone CryptoCell C7XX family of Crypto accelerators"
-	depends on CRYPTO && CRYPTO_HW && OF && HAS_DMA
-	default n
-	select CRYPTO_HASH
-	select CRYPTO_BLKCIPHER
-	select CRYPTO_DES
-	select CRYPTO_AEAD
-	select CRYPTO_AUTHENC
-	select CRYPTO_SHA1
-	select CRYPTO_MD5
-	select CRYPTO_SHA256
-	select CRYPTO_SHA512
-	select CRYPTO_HMAC
-	select CRYPTO_AES
-	select CRYPTO_CBC
-	select CRYPTO_ECB
-	select CRYPTO_CTR
-	select CRYPTO_XTS
-	help
-	  Say 'Y' to enable a driver for the Arm TrustZone CryptoCell
-	  C7xx. Currently only the CryptoCell 712 REE is supported.
-	  Choose this if you wish to use hardware acceleration of
-	  cryptographic operations on the system REE.
-	  If unsure say Y.

drivers/staging/ccree/Makefile

-# SPDX-License-Identifier: GPL-2.0
-
-obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
-ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_hash.o cc_aead.o cc_ivgen.o cc_sram_mgr.o
-ccree-$(CONFIG_CRYPTO_FIPS) += cc_fips.o
-ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o
-ccree-$(CONFIG_PM) += cc_pm.o

drivers/staging/ccree/TODO

-
-
-*************************************************************************
-*									*
-* Arm Trust Zone CryptoCell REE Linux driver upstreaming TODO items	*
-*									*
-*************************************************************************
-
-1. ???
-

drivers/staging/ccree/cc_aead.h

-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
-
-/* \file cc_aead.h
- * ARM CryptoCell AEAD Crypto API
- */
-
-#ifndef __CC_AEAD_H__
-#define __CC_AEAD_H__
-
-#include <linux/kernel.h>
-#include <crypto/algapi.h>
-#include <crypto/ctr.h>
-
-/* mac_cmp - HW writes 8 B but all bytes hold the same value */
-#define ICV_CMP_SIZE 8
-#define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3)
-#define MAX_MAC_SIZE SHA256_DIGEST_SIZE
-
-/* defines for AES GCM configuration buffer */
-#define GCM_BLOCK_LEN_SIZE 8
-
-#define GCM_BLOCK_RFC4_IV_OFFSET	4
-#define GCM_BLOCK_RFC4_IV_SIZE		8  /* IV size for rfc's */
-#define GCM_BLOCK_RFC4_NONCE_OFFSET	0
-#define GCM_BLOCK_RFC4_NONCE_SIZE	4
-
-/* Offsets into AES CCM configuration buffer */
-#define CCM_B0_OFFSET 0
-#define CCM_A0_OFFSET 16
-#define CCM_CTR_COUNT_0_OFFSET 32
-/* CCM B0 and CTR_COUNT constants. */
-#define CCM_BLOCK_NONCE_OFFSET 1  /* Nonce offset inside B0 and CTR_COUNT */
-#define CCM_BLOCK_NONCE_SIZE   3  /* Nonce size inside B0 and CTR_COUNT */
-#define CCM_BLOCK_IV_OFFSET    4  /* IV offset inside B0 and CTR_COUNT */
-#define CCM_BLOCK_IV_SIZE      8  /* IV size inside B0 and CTR_COUNT */
-
-enum aead_ccm_header_size {
-	ccm_header_size_null = -1,
-	ccm_header_size_zero = 0,
-	ccm_header_size_2 = 2,
-	ccm_header_size_6 = 6,
-	ccm_header_size_max = S32_MAX
-};
-
-struct aead_req_ctx {
-	/* Allocate cache line although only 4 bytes are needed to
-	 *  assure next field falls @ cache line
-	 *  Used for both: digest HW compare and CCM/GCM MAC value
-	 */
-	u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
-	u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
-
-	//used in gcm
-	u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
-	u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
-	u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
-	struct {
-		u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
-		u8 len_c[GCM_BLOCK_LEN_SIZE];
-	} gcm_len_block;
-
-	u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
-	/* HW actual size input */
-	unsigned int hw_iv_size ____cacheline_aligned;
-	/* used to prevent cache coherence problem */
-	u8 backup_mac[MAX_MAC_SIZE];
-	u8 *backup_iv; /*store iv for generated IV flow*/
-	u8 *backup_giv; /*store iv for rfc3686(ctr) flow*/
-	dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */
-	/* buffer for internal ccm configurations */
-	dma_addr_t ccm_iv0_dma_addr;
-	dma_addr_t icv_dma_addr; /* Phys. address of ICV */
-
-	//used in gcm
-	/* buffer for internal gcm configurations */
-	dma_addr_t gcm_iv_inc1_dma_addr;
-	/* buffer for internal gcm configurations */
-	dma_addr_t gcm_iv_inc2_dma_addr;
-	dma_addr_t hkey_dma_addr; /* Phys. address of hkey */
-	dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */
-	bool is_gcm4543;
-
-	u8 *icv_virt_addr; /* Virt. address of ICV */
-	struct async_gen_req_ctx gen_ctx;
-	struct cc_mlli assoc;
-	struct cc_mlli src;
-	struct cc_mlli dst;
-	struct scatterlist *src_sgl;
-	struct scatterlist *dst_sgl;
-	unsigned int src_offset;
-	unsigned int dst_offset;
-	enum cc_req_dma_buf_type assoc_buff_type;
-	enum cc_req_dma_buf_type data_buff_type;
-	struct mlli_params mlli_params;
-	unsigned int cryptlen;
-	struct scatterlist ccm_adata_sg;
-	enum aead_ccm_header_size ccm_hdr_size;
-	unsigned int req_authsize;
-	enum drv_cipher_mode cipher_mode;
-	bool is_icv_fragmented;
-	bool is_single_pass;
-	bool plaintext_authenticate_only; //for gcm_rfc4543
-};
-
-int cc_aead_alloc(struct cc_drvdata *drvdata);
-int cc_aead_free(struct cc_drvdata *drvdata);
-
-#endif /*__CC_AEAD_H__*/

drivers/staging/ccree/cc_buffer_mgr.h

-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
-
-/* \file cc_buffer_mgr.h
- * Buffer Manager
- */
-
-#ifndef __CC_BUFFER_MGR_H__
-#define __CC_BUFFER_MGR_H__
-
-#include <crypto/algapi.h>
-
-#include "cc_driver.h"
-
-enum cc_req_dma_buf_type {
-	CC_DMA_BUF_NULL = 0,
-	CC_DMA_BUF_DLLI,
-	CC_DMA_BUF_MLLI
-};
-
-enum cc_sg_cpy_direct {
-	CC_SG_TO_BUF = 0,
-	CC_SG_FROM_BUF = 1
-};
-
-struct cc_mlli {
-	cc_sram_addr_t sram_addr;
-	unsigned int nents; //sg nents
-	unsigned int mlli_nents; //mlli nents might be different than the above
-};
-
-struct mlli_params {
-	struct dma_pool *curr_pool;
-	u8 *mlli_virt_addr;
-	dma_addr_t mlli_dma_addr;
-	u32 mlli_len;
-};
-
-int cc_buffer_mgr_init(struct cc_drvdata *drvdata);
-
-int cc_buffer_mgr_fini(struct cc_drvdata *drvdata);
-
-int cc_map_blkcipher_request(struct cc_drvdata *drvdata, void *ctx,
-			     unsigned int ivsize, unsigned int nbytes,
-			     void *info, struct scatterlist *src,
-			     struct scatterlist *dst, gfp_t flags);
-
-void cc_unmap_blkcipher_request(struct device *dev, void *ctx,
-				unsigned int ivsize,
-				struct scatterlist *src,
-				struct scatterlist *dst);
-
-int cc_map_aead_request(struct cc_drvdata *drvdata, struct aead_request *req);
-
-void cc_unmap_aead_request(struct device *dev, struct aead_request *req);
-
-int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx,
-			      struct scatterlist *src, unsigned int nbytes,
-			      bool do_update, gfp_t flags);
-
-int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx,
-			       struct scatterlist *src, unsigned int nbytes,
-			       unsigned int block_size, gfp_t flags);
-
-void cc_unmap_hash_request(struct device *dev, void *ctx,
-			   struct scatterlist *src, bool do_revert);
-
-void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg,
-			u32 to_skip, u32 end, enum cc_sg_cpy_direct direct);
-
-void cc_zero_sgl(struct scatterlist *sgl, u32 data_len);
-
-#endif /*__BUFFER_MGR_H__*/
-

drivers/staging/ccree/cc_cipher.h

-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
-
-/* \file cc_cipher.h
- * ARM CryptoCell Cipher Crypto API
- */
-
-#ifndef __CC_CIPHER_H__
-#define __CC_CIPHER_H__
-
-#include <linux/kernel.h>
-#include <crypto/algapi.h>
-#include "cc_driver.h"
-#include "cc_buffer_mgr.h"
-
-/* Crypto cipher flags */
-#define CC_CRYPTO_CIPHER_KEY_KFDE0	BIT(0)
-#define CC_CRYPTO_CIPHER_KEY_KFDE1	BIT(1)
-#define CC_CRYPTO_CIPHER_KEY_KFDE2	BIT(2)
-#define CC_CRYPTO_CIPHER_KEY_KFDE3	BIT(3)
-#define CC_CRYPTO_CIPHER_DU_SIZE_512B	BIT(4)
-
-#define CC_CRYPTO_CIPHER_KEY_KFDE_MASK (CC_CRYPTO_CIPHER_KEY_KFDE0 | \
-					CC_CRYPTO_CIPHER_KEY_KFDE1 | \
-					CC_CRYPTO_CIPHER_KEY_KFDE2 | \
-					CC_CRYPTO_CIPHER_KEY_KFDE3)
-
-struct blkcipher_req_ctx {
-	struct async_gen_req_ctx gen_ctx;
-	enum cc_req_dma_buf_type dma_buf_type;
-	u32 in_nents;
-	u32 in_mlli_nents;
-	u32 out_nents;
-	u32 out_mlli_nents;
-	u8 *backup_info; /*store iv for generated IV flow*/
-	u8 *iv;
-	bool is_giv;
-	struct mlli_params mlli_params;
-};
-
-int cc_cipher_alloc(struct cc_drvdata *drvdata);
-
-int cc_cipher_free(struct cc_drvdata *drvdata);
-
-#ifndef CRYPTO_ALG_BULK_MASK
-
-#define CRYPTO_ALG_BULK_DU_512	0x00002000
-#define CRYPTO_ALG_BULK_DU_4096	0x00004000
-#define CRYPTO_ALG_BULK_MASK	(CRYPTO_ALG_BULK_DU_512 |\
-				CRYPTO_ALG_BULK_DU_4096)
-#endif /* CRYPTO_ALG_BULK_MASK */
-
-#ifdef CRYPTO_TFM_REQ_HW_KEY
-
-static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
-{
-	return (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_HW_KEY);
-}
-
-#else
-
-struct arm_hw_key_info {
-	int hw_key1;
-	int hw_key2;
-};
-
-static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
-{
-	return false;
-}
-
-#endif /* CRYPTO_TFM_REQ_HW_KEY */
-
-#endif /*__CC_CIPHER_H__*/

drivers/staging/ccree/cc_crypto_ctx.h

-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
-
-#ifndef _CC_CRYPTO_CTX_H_
-#define _CC_CRYPTO_CTX_H_
-
-#include <linux/types.h>
-
-/* context size */
-#ifndef CC_CTX_SIZE_LOG2
-#if (CC_DEV_SHA_MAX > 256)
-#define CC_CTX_SIZE_LOG2 8
-#else
-#define CC_CTX_SIZE_LOG2 7
-#endif
-#endif
-#define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2)
-#define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)
-
-#define CC_DRV_DES_IV_SIZE 8
-#define CC_DRV_DES_BLOCK_SIZE 8
-
-#define CC_DRV_DES_ONE_KEY_SIZE 8
-#define CC_DRV_DES_DOUBLE_KEY_SIZE 16
-#define CC_DRV_DES_TRIPLE_KEY_SIZE 24
-#define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE
-
-#define CC_AES_IV_SIZE 16
-#define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2)
-
-#define CC_AES_BLOCK_SIZE 16
-#define CC_AES_BLOCK_SIZE_WORDS 4
-
-#define CC_AES_128_BIT_KEY_SIZE 16
-#define CC_AES_128_BIT_KEY_SIZE_WORDS	(CC_AES_128_BIT_KEY_SIZE >> 2)
-#define CC_AES_192_BIT_KEY_SIZE 24
-#define CC_AES_192_BIT_KEY_SIZE_WORDS	(CC_AES_192_BIT_KEY_SIZE >> 2)
-#define CC_AES_256_BIT_KEY_SIZE 32
-#define CC_AES_256_BIT_KEY_SIZE_WORDS	(CC_AES_256_BIT_KEY_SIZE >> 2)
-#define CC_AES_KEY_SIZE_MAX			CC_AES_256_BIT_KEY_SIZE
-#define CC_AES_KEY_SIZE_WORDS_MAX		(CC_AES_KEY_SIZE_MAX >> 2)
-
-#define CC_MD5_DIGEST_SIZE	16
-#define CC_SHA1_DIGEST_SIZE	20
-#define CC_SHA224_DIGEST_SIZE	28
-#define CC_SHA256_DIGEST_SIZE	32
-#define CC_SHA256_DIGEST_SIZE_IN_WORDS 8
-#define CC_SHA384_DIGEST_SIZE	48
-#define CC_SHA512_DIGEST_SIZE	64
-
-#define CC_SHA1_BLOCK_SIZE 64
-#define CC_SHA1_BLOCK_SIZE_IN_WORDS 16
-#define CC_MD5_BLOCK_SIZE 64
-#define CC_MD5_BLOCK_SIZE_IN_WORDS 16
-#define CC_SHA224_BLOCK_SIZE 64
-#define CC_SHA256_BLOCK_SIZE 64
-#define CC_SHA256_BLOCK_SIZE_IN_WORDS 16
-#define CC_SHA1_224_256_BLOCK_SIZE 64
-#define CC_SHA384_BLOCK_SIZE 128
-#define CC_SHA512_BLOCK_SIZE 128
-
-#if (CC_DEV_SHA_MAX > 256)
-#define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
-#define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
-#else /* Only up to SHA256 */
-#define CC_DIGEST_SIZE_MAX CC_SHA256_DIGEST_SIZE
-#define CC_HASH_BLOCK_SIZE_MAX CC_SHA256_BLOCK_SIZE /*512b*/
-#endif
-
-#define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
-
-#define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
-
-enum drv_engine_type {
-	DRV_ENGINE_NULL = 0,
-	DRV_ENGINE_AES = 1,
-	DRV_ENGINE_DES = 2,
-	DRV_ENGINE_HASH = 3,
-	DRV_ENGINE_RC4 = 4,
-	DRV_ENGINE_DOUT = 5,
-	DRV_ENGINE_RESERVE32B = S32_MAX,
-};
-
-enum drv_crypto_alg {
-	DRV_CRYPTO_ALG_NULL = -1,
-	DRV_CRYPTO_ALG_AES  = 0,
-	DRV_CRYPTO_ALG_DES  = 1,
-	DRV_CRYPTO_ALG_HASH = 2,
-	DRV_CRYPTO_ALG_C2   = 3,
-	DRV_CRYPTO_ALG_HMAC = 4,
-	DRV_CRYPTO_ALG_AEAD = 5,
-	DRV_CRYPTO_ALG_BYPASS = 6,
-	DRV_CRYPTO_ALG_NUM = 7,
-	DRV_CRYPTO_ALG_RESERVE32B = S32_MAX
-};
-
-enum drv_crypto_direction {
-	DRV_CRYPTO_DIRECTION_NULL = -1,
-	DRV_CRYPTO_DIRECTION_ENCRYPT = 0,
-	DRV_CRYPTO_DIRECTION_DECRYPT = 1,
-	DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3,
-	DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX
-};
-
-enum drv_cipher_mode {
-	DRV_CIPHER_NULL_MODE = -1,
-	DRV_CIPHER_ECB = 0,
-	DRV_CIPHER_CBC = 1,
-	DRV_CIPHER_CTR = 2,
-	DRV_CIPHER_CBC_MAC = 3,
-	DRV_CIPHER_XTS = 4,
-	DRV_CIPHER_XCBC_MAC = 5,
-	DRV_CIPHER_OFB = 6,
-	DRV_CIPHER_CMAC = 7,
-	DRV_CIPHER_CCM = 8,
-	DRV_CIPHER_CBC_CTS = 11,
-	DRV_CIPHER_GCTR = 12,
-	DRV_CIPHER_ESSIV = 13,
-	DRV_CIPHER_BITLOCKER = 14,
-	DRV_CIPHER_RESERVE32B = S32_MAX
-};
-
-enum drv_hash_mode {
-	DRV_HASH_NULL = -1,
-	DRV_HASH_SHA1 = 0,
-	DRV_HASH_SHA256 = 1,
-	DRV_HASH_SHA224 = 2,
-	DRV_HASH_SHA512 = 3,
-	DRV_HASH_SHA384 = 4,
-	DRV_HASH_MD5 = 5,
-	DRV_HASH_CBC_MAC = 6,
-	DRV_HASH_XCBC_MAC = 7,
-	DRV_HASH_CMAC = 8,
-	DRV_HASH_MODE_NUM = 9,
-	DRV_HASH_RESERVE32B = S32_MAX
-};
-
-enum drv_hash_hw_mode {
-	DRV_HASH_HW_MD5 = 0,
-	DRV_HASH_HW_SHA1 = 1,
-	DRV_HASH_HW_SHA256 = 2,
-	DRV_HASH_HW_SHA224 = 10,
-	DRV_HASH_HW_SHA512 = 4,
-	DRV_HASH_HW_SHA384 = 12,
-	DRV_HASH_HW_GHASH = 6,
-	DRV_HASH_HW_RESERVE32B = S32_MAX
-};
-
-/* drv_crypto_key_type[1:0] is mapped to cipher_do[1:0] */
-/* drv_crypto_key_type[2] is mapped to cipher_config2 */
-enum drv_crypto_key_type {
-	DRV_NULL_KEY = -1,
-	DRV_USER_KEY = 0,		/* 0x000 */
-	DRV_ROOT_KEY = 1,		/* 0x001 */
-	DRV_PROVISIONING_KEY = 2,	/* 0x010 */
-	DRV_SESSION_KEY = 3,		/* 0x011 */
-	DRV_APPLET_KEY = 4,		/* NA */
-	DRV_PLATFORM_KEY = 5,		/* 0x101 */
-	DRV_CUSTOMER_KEY = 6,		/* 0x110 */
-	DRV_END_OF_KEYS = S32_MAX,
-};
-
-enum drv_crypto_padding_type {
-	DRV_PADDING_NONE = 0,
-	DRV_PADDING_PKCS7 = 1,
-	DRV_PADDING_RESERVE32B = S32_MAX
-};
-
-#endif /* _CC_CRYPTO_CTX_H_ */
-

drivers/staging/ccree/cc_debugfs.c

-// SPDX-License-Identifier: GPL-2.0
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
-
-#include <linux/kernel.h>
-#include <linux/debugfs.h>
-#include <linux/stringify.h>
-#include "cc_driver.h"
-#include "cc_crypto_ctx.h"
-#include "cc_debugfs.h"
-
-struct cc_debugfs_ctx {
-	struct dentry *dir;
-};
-
-#define CC_DEBUG_REG(_X) {	\
-	.name = __stringify(_X),\
-	.offset = CC_REG(_X)	\
-	}
-
-/*
- * This is a global var for the dentry of the
- * debugfs ccree/ dir. It is not tied down to
- * a specific instance of ccree, hence it is
- * global.
- */
-static struct dentry *cc_debugfs_dir;
-
-static struct debugfs_reg32 debug_regs[] = {
-	CC_DEBUG_REG(HOST_SIGNATURE),
-	CC_DEBUG_REG(HOST_IRR),
-	CC_DEBUG_REG(HOST_POWER_DOWN_EN),
-	CC_DEBUG_REG(AXIM_MON_ERR),
-	CC_DEBUG_REG(DSCRPTR_QUEUE_CONTENT),
-	CC_DEBUG_REG(HOST_IMR),
-	CC_DEBUG_REG(AXIM_CFG),
-	CC_DEBUG_REG(AXIM_CACHE_PARAMS),
-	CC_DEBUG_REG(HOST_VERSION),
-	CC_DEBUG_REG(GPR_HOST),
-	CC_DEBUG_REG(AXIM_MON_COMP),
-};
-
-int __init cc_debugfs_global_init(void)
-{
-	cc_debugfs_dir = debugfs_create_dir("ccree", NULL);
-
-	return !cc_debugfs_dir;
-}
-
-void __exit cc_debugfs_global_fini(void)
-{
-	debugfs_remove(cc_debugfs_dir);
-}
-
-int cc_debugfs_init(struct cc_drvdata *drvdata)
-{
-	struct device *dev = drvdata_to_dev(drvdata);
-	struct cc_debugfs_ctx *ctx;
-	struct debugfs_regset32 *regset;
-	struct dentry *file;
-
-	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
-
-	regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
-	if (!regset)
-		return -ENOMEM;
-
-	regset->regs = debug_regs;
-	regset->nregs = ARRAY_SIZE(debug_regs);
-	regset->base = drvdata->cc_base;
-
-	ctx->dir = debugfs_create_dir(drvdata->plat_dev->name, cc_debugfs_dir);
-	if (!ctx->dir)
-		return -ENFILE;
-
-	file = debugfs_create_regset32("regs", 0400, ctx->dir, regset);
-	if (!file) {
-		debugfs_remove(ctx->dir);
-		return -ENFILE;
-	}
-
-	file = debugfs_create_bool("coherent", 0400, ctx->dir,
-				   &drvdata->coherent);
-
-	if (!file) {
-		debugfs_remove_recursive(ctx->dir);
-		return -ENFILE;
-	}
-
-	drvdata->debugfs = ctx;
-
-	return 0;
-}
-
-void cc_debugfs_fini(struct cc_drvdata *drvdata)
-{
-	struct cc_debugfs_ctx *ctx = (struct cc_debugfs_ctx *)drvdata->debugfs;
-
-	debugfs_remove_recursive(ctx->dir);
-}

drivers/staging/ccree/cc_debugfs.h

-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
-
-#ifndef __CC_DEBUGFS_H__
-#define __CC_DEBUGFS_H__
-
-#ifdef CONFIG_DEBUG_FS
-int cc_debugfs_global_init(void);
-void cc_debugfs_global_fini(void);
-
-int cc_debugfs_init(struct cc_drvdata *drvdata);
-void cc_debugfs_fini(struct cc_drvdata *drvdata);
-
-#else
-
-static inline int cc_debugfs_global_init(void)
-{
-	return 0;
-}
-
-static inline void cc_debugfs_global_fini(void) {}
-
-static inline int cc_debugfs_init(struct cc_drvdata *drvdata)
-{
-	return 0;
-}
-
-static inline void cc_debugfs_fini(struct cc_drvdata *drvdata) {}
-
-#endif
-
-#endif /*__CC_SYSFS_H__*/