openeuler: net: ngbe: add ngbe module source code

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I61PSD
CVE: NA

Supported Features:
-------------
- Support 10/100/1000M full and Autoneg.
- Support Legacy/MSI/MSI-X interrupt.
- Support ipv4/ipv6, Support promisc mode.
- Support RSS.
- Support Vlan.
- Support Tx/Rx checksum offload.
- Support TSO.
- Support Jumbo Frames.
- Support IEEE 1588.
- Support Linux bond.
- Support L2 Filter.
Signed-off-by: NDuanqiang Wen <duanqiangwen@net-swift.com>

drivers/net/ethernet/netswift/ngbe/Makefile

+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2015 - 2017 Beijing WangXun Technology Co., Ltd.
+#
+# Makefile for the Netswift Gigabit PCI Express ethernet driver
+#
+
+obj-$(CONFIG_NGBE) += ngbe.o
+
+ngbe-objs := ngbe_main.o ngbe_ethtool.o \
+              ngbe_hw.o ngbe_phy.o ngbe_sriov.o \
+              ngbe_mbx.o ngbe_pcierr.o ngbe_param.o ngbe_lib.o ngbe_ptp.o
+
+ngbe-$(CONFIG_NGBE_HWMON) += ngbe_sysfs.o
+ngbe-$(CONFIG_NGBE_DEBUG_FS) += ngbe_debugfs.o
+ngbe-$(CONFIG_NGBE_SYSFS) += ngbe_sysfs.o

drivers/net/ethernet/netswift/ngbe/ngbe_debugfs.c

+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
+
+#include "ngbe.h"
+
+#ifdef CONFIG_NGBE_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/module.h>
+
+static struct dentry *ngbe_dbg_root;
+static int ngbe_data_mode;
+
+#define NGBE_DATA_FUNC(dm)  ((dm) & ~0xFFFF)
+#define NGBE_DATA_ARGS(dm)  ((dm) & 0xFFFF)
+enum ngbe_data_func {
+	NGBE_FUNC_NONE        = (0 << 16),
+	NGBE_FUNC_DUMP_BAR    = (1 << 16),
+	NGBE_FUNC_DUMP_RDESC  = (2 << 16),
+	NGBE_FUNC_DUMP_TDESC  = (3 << 16),
+	NGBE_FUNC_FLASH_READ  = (4 << 16),
+	NGBE_FUNC_FLASH_WRITE = (5 << 16),
+};
+
+/**
+ * data operation
+ **/
+ssize_t
+ngbe_simple_read_from_pcibar(struct ngbe_adapter *adapter, int res,
+		void __user *buf, size_t size, loff_t *ppos)
+{
+	loff_t pos = *ppos;
+	u32 miss, len, limit = pci_resource_len(adapter->pdev, res);
+
+	if (pos < 0)
+		return 0;
+
+	limit = (pos + size <= limit ? pos + size : limit);
+	for (miss = 0; pos < limit && !miss; buf += len, pos += len) {
+		u32 val = 0, reg = round_down(pos, 4);
+		u32 off = pos - reg;
+
+		len = (reg + 4 <= limit ? 4 - off : 4 - off - (limit - reg - 4));
+		val = ngbe_rd32(adapter->io_addr + reg);
+		miss = copy_to_user(buf, &val + off, len);
+	}
+
+	size = pos - *ppos - miss;
+	*ppos += size;
+
+	return size;
+}
+
+ssize_t
+ngbe_simple_read_from_flash(struct ngbe_adapter *adapter,
+		void __user *buf, size_t size, loff_t *ppos)
+{
+	struct ngbe_hw *hw = &adapter->hw;
+	loff_t pos = *ppos;
+	size_t ret = 0;
+	loff_t rpos, rtail;
+	void __user *to = buf;
+	size_t available = adapter->hw.flash.dword_size << 2;
+
+	if (pos < 0)
+		return -EINVAL;
+	if (pos >= available || !size)
+		return 0;
+	if (size > available - pos)
+		size = available - pos;
+
+	rpos = round_up(pos, 4);
+	rtail = round_down(pos + size, 4);
+	if (rtail < rpos)
+		return 0;
+
+	to += rpos - pos;
+	while (rpos <= rtail) {
+		u32 value = ngbe_rd32(adapter->io_addr + rpos);
+
+		if (TCALL(hw, flash.ops.write_buffer, rpos >> 2, 1, &value)) {
+			ret = size;
+			break;
+		}
+		if (copy_to_user(to, &value, 4) == 4) {
+			ret = size;
+			break;
+		}
+		to += 4;
+		rpos += 4;
+	}
+
+	if (ret == size)
+		return -EFAULT;
+	size -= ret;
+	*ppos = pos + size;
+	return size;
+}
+
+ssize_t
+ngbe_simple_write_to_flash(struct ngbe_adapter *adapter,
+	const void __user *from, size_t size, loff_t *ppos, size_t available)
+{
+	return size;
+}
+
+static ssize_t
+ngbe_dbg_data_ops_read(struct file *filp, char __user *buffer,
+				    size_t size, loff_t *ppos)
+{
+	struct ngbe_adapter *adapter = filp->private_data;
+	u32 func = NGBE_DATA_FUNC(ngbe_data_mode);
+
+	/* Ensure all reads are done */
+	rmb();
+
+	switch (func) {
+	case NGBE_FUNC_DUMP_BAR: {
+		u32 bar = NGBE_DATA_ARGS(ngbe_data_mode);
+
+		return ngbe_simple_read_from_pcibar(adapter, bar, buffer, size,
+					       ppos);
+	}
+	case NGBE_FUNC_FLASH_READ: {
+		return ngbe_simple_read_from_flash(adapter, buffer, size, ppos);
+	}
+	case NGBE_FUNC_DUMP_RDESC: {
+		struct ngbe_ring *ring;
+		u32 queue = NGBE_DATA_ARGS(ngbe_data_mode);
+
+		if (queue >= adapter->num_rx_queues)
+			return 0;
+		queue += VMDQ_P(0) * adapter->queues_per_pool;
+		ring = adapter->rx_ring[queue];
+
+		return simple_read_from_buffer(buffer, size, ppos,
+			ring->desc, ring->size);
+		break;
+	}
+	case NGBE_FUNC_DUMP_TDESC: {
+		struct ngbe_ring *ring;
+		u32 queue = NGBE_DATA_ARGS(ngbe_data_mode);
+
+		if (queue >= adapter->num_tx_queues)
+			return 0;
+		queue += VMDQ_P(0) * adapter->queues_per_pool;
+		ring = adapter->tx_ring[queue];
+
+		return simple_read_from_buffer(buffer, size, ppos,
+			ring->desc, ring->size);
+		break;
+	}
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static ssize_t
+ngbe_dbg_data_ops_write(struct file *filp,
+				     const char __user *buffer,
+				     size_t size, loff_t *ppos)
+{
+	struct ngbe_adapter *adapter = filp->private_data;
+	u32 func = NGBE_DATA_FUNC(ngbe_data_mode);
+
+	/* Ensure all reads are done */
+	rmb();
+
+	switch (func) {
+	case NGBE_FUNC_FLASH_WRITE: {
+		u32 size = NGBE_DATA_ARGS(ngbe_data_mode);
+
+		if (size > adapter->hw.flash.dword_size << 2)
+			size = adapter->hw.flash.dword_size << 2;
+
+		return ngbe_simple_write_to_flash(adapter, buffer, size, ppos, size);
+	}
+	default:
+		break;
+	}
+
+	return size;
+}
+static const struct file_operations ngbe_dbg_data_ops_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = ngbe_dbg_data_ops_read,
+	.write = ngbe_dbg_data_ops_write,
+};
+
+/**
+ * reg_ops operation
+ **/
+static char ngbe_dbg_reg_ops_buf[256] = "";
+static ssize_t
+ngbe_dbg_reg_ops_read(struct file *filp, char __user *buffer,
+				    size_t count, loff_t *ppos)
+{
+	struct ngbe_adapter *adapter = filp->private_data;
+	char *buf;
+	int len;
+
+	/* don't allow partial reads */
+	if (*ppos != 0)
+		return 0;
+
+	buf = kasprintf(GFP_KERNEL, "%s: mode=0x%08x\n%s\n",
+			adapter->netdev->name, ngbe_data_mode,
+			ngbe_dbg_reg_ops_buf);
+	if (!buf)
+		return -ENOMEM;
+
+	if (count < strlen(buf)) {
+		kfree(buf);
+		return -ENOSPC;
+	}
+
+	len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
+
+	kfree(buf);
+	return len;
+}
+
+static ssize_t
+ngbe_dbg_reg_ops_write(struct file *filp,
+				     const char __user *buffer,
+				     size_t count, loff_t *ppos)
+{
+	struct ngbe_adapter *adapter = filp->private_data;
+	char *pc = ngbe_dbg_reg_ops_buf;
+	int len;
+	int ret;
+
+	/* don't allow partial writes */
+	if (*ppos != 0)
+		return 0;
+
+	if (count >= sizeof(ngbe_dbg_reg_ops_buf))
+		return -ENOSPC;
+
+	len = simple_write_to_buffer(ngbe_dbg_reg_ops_buf,
+				     sizeof(ngbe_dbg_reg_ops_buf) - 1,
+				     ppos,
+				     buffer,
+				     count);
+	if (len < 0)
+		return len;
+
+	pc[len] = '\0';
+
+	if (strncmp(pc, "dump", 4) == 0) {
+		u32 mode = 0;
+		u16 args;
+
+		pc += 4;
+		pc += strspn(pc, " \t");
+
+		if (!strncmp(pc, "bar", 3)) {
+			pc += 3;
+			mode = NGBE_FUNC_DUMP_BAR;
+		} else if (!strncmp(pc, "rdesc", 5)) {
+			pc += 5;
+			mode = NGBE_FUNC_DUMP_RDESC;
+		} else if (!strncmp(pc, "tdesc", 5)) {
+			pc += 5;
+			mode = NGBE_FUNC_DUMP_TDESC;
+		} else {
+			ngbe_dump(adapter);
+		}
+
+		if (mode && kstrtou16(pc, 1, &args) == 0)
+			mode |= args;
+
+		ngbe_data_mode = mode;
+	} else if (strncmp(pc, "flash", 4) == 0) {
+		u32 mode = 0;
+		u16 args;
+
+		pc += 5;
+		pc += strspn(pc, " \t");
+		if (!strncmp(pc, "read", 3)) {
+			pc += 4;
+			mode = NGBE_FUNC_FLASH_READ;
+		} else if (!strncmp(pc, "write", 5)) {
+			pc += 5;
+			mode = NGBE_FUNC_FLASH_WRITE;
+		}
+
+		if (mode && kstrtou16(pc, 1, &args) == 0)
+			mode |= args;
+
+		ngbe_data_mode = mode;
+	} else if (strncmp(ngbe_dbg_reg_ops_buf, "write", 5) == 0) {
+		u32 reg, value;
+		int cnt;
+
+		cnt = sscanf(&ngbe_dbg_reg_ops_buf[5], "%x %x", &reg, &value);
+		if (cnt == 2) {
+			wr32(&adapter->hw, reg, value);
+			e_dev_info("write: 0x%08x = 0x%08x\n", reg, value);
+		} else {
+			e_dev_info("write <reg> <value>\n");
+		}
+	} else if (strncmp(ngbe_dbg_reg_ops_buf, "read", 4) == 0) {
+		u32 reg, value;
+		int cnt;
+
+		ret = kstrtou32(&ngbe_dbg_reg_ops_buf[4], 1, &reg);
+		if (cnt == 1) {
+			value = rd32(&adapter->hw, reg);
+			e_dev_info("read 0x%08x = 0x%08x\n", reg, value);
+		} else {
+			e_dev_info("read <reg>\n");
+		}
+	} else {
+		e_dev_info("Unknown command %s\n", ngbe_dbg_reg_ops_buf);
+		e_dev_info("Available commands:\n");
+		e_dev_info("   read <reg>\n");
+		e_dev_info("   write <reg> <value>\n");
+	}
+	return count;
+}
+
+static const struct file_operations ngbe_dbg_reg_ops_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read =  ngbe_dbg_reg_ops_read,
+	.write = ngbe_dbg_reg_ops_write,
+};
+
+/**
+ * netdev_ops operation
+ **/
+static char ngbe_dbg_netdev_ops_buf[256] = "";
+static ssize_t
+ngbe_dbg_netdev_ops_read(struct file *filp,
+					 char __user *buffer,
+					 size_t count, loff_t *ppos)
+{
+	struct ngbe_adapter *adapter = filp->private_data;
+	char *buf;
+	int len;
+
+	/* don't allow partial reads */
+	if (*ppos != 0)
+		return 0;
+
+	buf = kasprintf(GFP_KERNEL, "%s: mode=0x%08x\n%s\n",
+			adapter->netdev->name, ngbe_data_mode,
+			ngbe_dbg_netdev_ops_buf);
+	if (!buf)
+		return -ENOMEM;
+
+	if (count < strlen(buf)) {
+		kfree(buf);
+		return -ENOSPC;
+	}
+
+	len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
+
+	kfree(buf);
+	return len;
+}
+
+static ssize_t
+ngbe_dbg_netdev_ops_write(struct file *filp,
+					  const char __user *buffer,
+					  size_t count, loff_t *ppos)
+{
+	struct ngbe_adapter *adapter = filp->private_data;
+	int len;
+
+	/* don't allow partial writes */
+	if (*ppos != 0)
+		return 0;
+	if (count >= sizeof(ngbe_dbg_netdev_ops_buf))
+		return -ENOSPC;
+
+	len = simple_write_to_buffer(ngbe_dbg_netdev_ops_buf,
+				     sizeof(ngbe_dbg_netdev_ops_buf) - 1,
+				     ppos,
+				     buffer,
+				     count);
+	if (len < 0)
+		return len;
+
+	ngbe_dbg_netdev_ops_buf[len] = '\0';
+
+	if (strncmp(ngbe_dbg_netdev_ops_buf, "tx_timeout", 10) == 0) {
+		adapter->netdev->netdev_ops->ndo_tx_timeout(adapter->netdev, UINT_MAX);
+		e_dev_info("tx_timeout called\n");
+	} else {
+		e_dev_info("Unknown command: %s\n", ngbe_dbg_netdev_ops_buf);
+		e_dev_info("Available commands:\n");
+		e_dev_info("    tx_timeout\n");
+	}
+	return count;
+}
+
+static const struct file_operations ngbe_dbg_netdev_ops_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = ngbe_dbg_netdev_ops_read,
+	.write = ngbe_dbg_netdev_ops_write,
+};
+
+/**
+ * ngbe_dbg_adapter_init - setup the debugfs directory for the adapter
+ * @adapter: the adapter that is starting up
+ **/
+void ngbe_dbg_adapter_init(struct ngbe_adapter *adapter)
+{
+	const char *name = pci_name(adapter->pdev);
+	struct dentry *pfile;
+
+	adapter->ngbe_dbg_adapter = debugfs_create_dir(name, ngbe_dbg_root);
+	if (!adapter->ngbe_dbg_adapter) {
+		e_dev_err("debugfs entry for %s failed\n", name);
+		return;
+	}
+
+	pfile = debugfs_create_file("data", 0600,
+				    adapter->ngbe_dbg_adapter, adapter,
+				    &ngbe_dbg_data_ops_fops);
+	if (!pfile)
+		e_dev_err("debugfs netdev_ops for %s failed\n", name);
+
+	pfile = debugfs_create_file("reg_ops", 0600,
+				    adapter->ngbe_dbg_adapter, adapter,
+				    &ngbe_dbg_reg_ops_fops);
+	if (!pfile)
+		e_dev_err("debugfs reg_ops for %s failed\n", name);
+
+	pfile = debugfs_create_file("netdev_ops", 0600,
+				    adapter->ngbe_dbg_adapter, adapter,
+				    &ngbe_dbg_netdev_ops_fops);
+	if (!pfile)
+		e_dev_err("debugfs netdev_ops for %s failed\n", name);
+}
+
+/**
+ * ngbe_dbg_adapter_exit - clear out the adapter's debugfs entries
+ * @pf: the pf that is stopping
+ **/
+void ngbe_dbg_adapter_exit(struct ngbe_adapter *adapter)
+{
+	debugfs_remove_recursive(adapter->ngbe_dbg_adapter);
+	adapter->ngbe_dbg_adapter = NULL;
+}
+
+/**
+ * ngbe_dbg_init - start up debugfs for the driver
+ **/
+void ngbe_dbg_init(void)
+{
+	ngbe_dbg_root = debugfs_create_dir(ngbe_driver_name, NULL);
+	if (!ngbe_dbg_root)
+		pr_err("init of debugfs failed\n");
+}
+
+/**
+ * ngbe_dbg_exit - clean out the driver's debugfs entries
+ **/
+void ngbe_dbg_exit(void)
+{
+	debugfs_remove_recursive(ngbe_dbg_root);
+}
+
+#endif /* CONFIG_NGBE_DEBUG_FS */
+
+struct ngbe_reg_info {
+	u32 offset;
+	u32 length;
+	char *name;
+};
+
+static struct ngbe_reg_info ngbe_reg_info_tbl[] = {
+	/* General Registers */
+	{NGBE_CFG_PORT_CTL, 1, "CTRL"},
+	{NGBE_CFG_PORT_ST, 1, "STATUS"},
+
+	/* RX Registers */
+	{NGBE_PX_RR_CFG(0), 1, "SRRCTL"},
+	{NGBE_PX_RR_RP(0), 1, "RDH"},
+	{NGBE_PX_RR_WP(0), 1, "RDT"},
+	{NGBE_PX_RR_CFG(0), 1, "RXDCTL"},
+	{NGBE_PX_RR_BAL(0), 1, "RDBAL"},
+	{NGBE_PX_RR_BAH(0), 1, "RDBAH"},
+
+	/* TX Registers */
+	{NGBE_PX_TR_BAL(0), 1, "TDBAL"},
+	{NGBE_PX_TR_BAH(0), 1, "TDBAH"},
+	{NGBE_PX_TR_RP(0), 1, "TDH"},
+	{NGBE_PX_TR_WP(0), 1, "TDT"},
+	{NGBE_PX_TR_CFG(0), 1, "TXDCTL"},
+
+	/* MACVLAN */
+	{NGBE_PSR_MAC_SWC_VM, 128, "PSR_MAC_SWC_VM"},
+	{NGBE_PSR_MAC_SWC_AD_L, 32, "PSR_MAC_SWC_AD"},
+	{NGBE_PSR_VLAN_TBL(0),  128, "PSR_VLAN_TBL"},
+
+	/* List Terminator */
+	{ .name = NULL }
+};
+
+/**
+ * ngbe_regdump - register printout routine
+ **/
+static void
+ngbe_regdump(struct ngbe_hw *hw, struct ngbe_reg_info *reg_info)
+{
+	int i, n = 0;
+	u32 buffer[256];
+
+	switch (reg_info->offset) {
+	case NGBE_PSR_MAC_SWC_AD_L:
+		for (i = 0; i < reg_info->length; i++) {
+			wr32(hw, NGBE_PSR_MAC_SWC_IDX, i);
+			buffer[n++] =
+				rd32(hw, NGBE_PSR_MAC_SWC_AD_H);
+			buffer[n++] =
+				rd32(hw, NGBE_PSR_MAC_SWC_AD_L);
+		}
+		break;
+	default:
+		for (i = 0; i < reg_info->length; i++) {
+			buffer[n++] = rd32(hw,
+				reg_info->offset + i << 2);
+		}
+		break;
+	}
+	WARN_ON(n);
+}
+
+/**
+ * ngbe_dump - Print registers, tx-rings and rx-rings
+ **/
+void ngbe_dump(struct ngbe_adapter *adapter)
+{
+	struct net_device *netdev = adapter->netdev;
+	struct ngbe_hw *hw = &adapter->hw;
+	struct ngbe_reg_info *reg_info;
+	int n = 0;
+	struct ngbe_ring *tx_ring;
+	struct ngbe_tx_buffer *tx_buffer;
+	union ngbe_tx_desc *tx_desc;
+	struct my_u0 { u64 a; u64 b; } *u0;
+	struct ngbe_ring *rx_ring;
+	union ngbe_rx_desc *rx_desc;
+	struct ngbe_rx_buffer *rx_buffer_info;
+	u32 staterr;
+	int i = 0;
+
+	if (!netif_msg_hw(adapter))
+		return;
+
+	/* Print Registers */
+	dev_info(&adapter->pdev->dev, "Register Dump\n");
+	pr_info(" Register Name   Value\n");
+	for (reg_info = ngbe_reg_info_tbl; reg_info->name; reg_info++)
+		ngbe_regdump(hw, reg_info);
+
+	/* Print TX Ring Summary */
+	if (!netdev || !netif_running(netdev))
+		return;
+
+	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
+	pr_info(" %s     %s              %s        %s\n",
+		"Queue [NTU] [NTC] [bi(ntc)->dma  ]",
+		"leng", "ntw", "timestamp");
+	for (n = 0; n < adapter->num_tx_queues; n++) {
+		tx_ring = adapter->tx_ring[n];
+		tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
+		pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
+			   n, tx_ring->next_to_use, tx_ring->next_to_clean,
+			   (u64)dma_unmap_addr(tx_buffer, dma),
+			   dma_unmap_len(tx_buffer, len),
+			   tx_buffer->next_to_watch,
+			   (u64)tx_buffer->time_stamp);
+	}
+
+	/* Print TX Rings */
+	if (!netif_msg_tx_done(adapter))
+		goto rx_ring_summary;
+
+	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
+
+	/* Transmit Descriptor Formats
+	 *
+	 * Transmit Descriptor (Read)
+	 *   +--------------------------------------------------------------+
+	 * 0 |         Buffer Address [63:0]                                |
+	 *   +--------------------------------------------------------------+
+	 * 8 |PAYLEN  |POPTS|CC|IDX  |STA  |DCMD  |DTYP |MAC  |RSV  |DTALEN |
+	 *   +--------------------------------------------------------------+
+	 *   63     46 45 40 39 38 36 35 32 31  24 23 20 19 18 17 16 15     0
+	 *
+	 * Transmit Descriptor (Write-Back)
+	 *   +--------------------------------------------------------------+
+	 * 0 |                          RSV [63:0]                          |
+	 *   +--------------------------------------------------------------+
+	 * 8 |            RSV           |  STA  |           RSV             |
+	 *   +--------------------------------------------------------------+
+	 *   63                       36 35   32 31                         0
+	 */
+
+	for (n = 0; n < adapter->num_tx_queues; n++) {
+		tx_ring = adapter->tx_ring[n];
+		pr_info("------------------------------------\n");
+		pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
+		pr_info("------------------------------------\n");
+		pr_info("%s%s    %s              %s        %s          %s\n",
+			"T [desc]     [address 63:0  ] ",
+			"[PlPOIdStDDt Ln] [bi->dma       ] ",
+			"leng", "ntw", "timestamp", "bi->skb");
+
+		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
+			tx_desc = NGBE_TX_DESC(tx_ring, i);
+			tx_buffer = &tx_ring->tx_buffer_info[i];
+			u0 = (struct my_u0 *)tx_desc;
+			if (dma_unmap_len(tx_buffer, len) > 0) {
+				pr_info("T [0x%03X]    %016llX %016llX %016llX %08X %p %016llX %p",
+					i,
+					le64_to_cpu(u0->a),
+					le64_to_cpu(u0->b),
+					(u64)dma_unmap_addr(tx_buffer, dma),
+					dma_unmap_len(tx_buffer, len),
+					tx_buffer->next_to_watch,
+					(u64)tx_buffer->time_stamp,
+					tx_buffer->skb);
+
+				if (netif_msg_pktdata(adapter) &&
+				    tx_buffer->skb)
+					print_hex_dump(KERN_INFO, "",
+						DUMP_PREFIX_ADDRESS, 16, 1,
+						tx_buffer->skb->data,
+						dma_unmap_len(tx_buffer, len),
+						true);
+			}
+		}
+	}
+
+	/* Print RX Rings Summary */
+rx_ring_summary:
+	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
+	pr_info("Queue [NTU] [NTC]\n");
+	for (n = 0; n < adapter->num_rx_queues; n++) {
+		rx_ring = adapter->rx_ring[n];
+		pr_info("%5d %5X %5X\n",
+			n, rx_ring->next_to_use, rx_ring->next_to_clean);
+	}
+
+	/* Print RX Rings */
+	if (!netif_msg_rx_status(adapter))
+		return;
+
+	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
+
+	/* Receive Descriptor Formats
+	 *
+	 * Receive Descriptor (Read)
+	 *    63                                           1        0
+	 *    +-----------------------------------------------------+
+	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
+	 *    +----------------------------------------------+------+
+	 *  8 |       Header Buffer Address [63:1]           |  DD  |
+	 *    +-----------------------------------------------------+
+	 *
+	 *
+	 * Receive Descriptor (Write-Back)
+	 *
+	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
+	 *   +------------------------------------------------------+
+	 * 0 |RSS / Frag Checksum|SPH| HDR_LEN  |RSC- |Packet|  RSS |
+	 *   |/ RTT / PCoE_PARAM |   |          | CNT | Type | Type |
+	 *   |/ Flow Dir Flt ID  |   |          |     |      |      |
+	 *   +------------------------------------------------------+
+	 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
+	 *   +------------------------------------------------------+
+	 *   63       48 47    32 31          20 19                 0
+	 */
+
+	for (n = 0; n < adapter->num_rx_queues; n++) {
+		rx_ring = adapter->rx_ring[n];
+		pr_info("------------------------------------\n");
+		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
+		pr_info("------------------------------------\n");
+		pr_info("%s%s%s",
+			"R  [desc]      [ PktBuf     A0] ",
+			"[  HeadBuf   DD] [bi->dma       ] [bi->skb       ] ",
+			"<-- Adv Rx Read format\n");
+		pr_info("%s%s%s",
+			"RWB[desc]      [PcsmIpSHl PtRs] ",
+			"[vl er S cks ln] ---------------- [bi->skb       ] ",
+			"<-- Adv Rx Write-Back format\n");
+
+		for (i = 0; i < rx_ring->count; i++) {
+			rx_buffer_info = &rx_ring->rx_buffer_info[i];
+			rx_desc = NGBE_RX_DESC(rx_ring, i);
+			u0 = (struct my_u0 *)rx_desc;
+			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
+			if (staterr & NGBE_RXD_STAT_DD) {
+				/* Descriptor Done */
+				pr_info("RWB[0x%03X]     %016llX %016llX %p", i,
+					le64_to_cpu(u0->a),
+					le64_to_cpu(u0->b),
+					rx_buffer_info->skb);
+			} else {
+				pr_info("R  [0x%03X]     %016llX %016llX %016llX %p", i,
+					le64_to_cpu(u0->a),
+					le64_to_cpu(u0->b),
+					(u64)rx_buffer_info->page_dma,
+					rx_buffer_info->skb);
+
+				if (netif_msg_pktdata(adapter) &&
+				    rx_buffer_info->page_dma) {
+					print_hex_dump(KERN_INFO, "",
+					   DUMP_PREFIX_ADDRESS, 16, 1,
+					   page_address(rx_buffer_info->page) +
+						    rx_buffer_info->page_offset,
+					   ngbe_rx_bufsz(rx_ring), true);
+				}
+			}
+		}
+	}
+}

drivers/net/ethernet/netswift/ngbe/ngbe_hw.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
+
+#ifndef _NGBE_HW_H_
+#define _NGBE_HW_H_
+
+#define NGBE_EMC_INTERNAL_DATA         0x00
+#define NGBE_EMC_INTERNAL_THERM_LIMIT  0x20
+#define NGBE_EMC_DIODE1_DATA           0x01
+#define NGBE_EMC_DIODE1_THERM_LIMIT    0x19
+#define NGBE_EMC_DIODE2_DATA           0x23
+#define NGBE_EMC_DIODE2_THERM_LIMIT    0x1A
+#define NGBE_EMC_DIODE3_DATA           0x2A
+#define NGBE_EMC_DIODE3_THERM_LIMIT    0x30
+
+#define SPI_CLK_DIV                        3
+
+#define SPI_CMD_ERASE_CHIP                 4  // SPI erase chip command
+#define SPI_CMD_ERASE_SECTOR               3  // SPI erase sector command
+#define SPI_CMD_WRITE_DWORD                0  // SPI write a dword command
+#define SPI_CMD_READ_DWORD                 1  // SPI read a dword command
+#define SPI_CMD_USER_CMD                   5  // SPI user command
+
+#define SPI_CLK_CMD_OFFSET                28  // SPI command field offset in Command register
+#define SPI_CLK_DIV_OFFSET                25  // SPI clock divide field offset in Command register
+
+#define SPI_TIME_OUT_VALUE             10000
+#define SPI_SECTOR_SIZE          (4 * 1024)  // FLASH sector size is 64KB
+#define SPI_H_CMD_REG_ADDR           0x10104  // SPI Command register address
+#define SPI_H_DAT_REG_ADDR           0x10108  // SPI Data register address
+#define SPI_H_STA_REG_ADDR           0x1010c  // SPI Status register address
+#define SPI_H_USR_CMD_REG_ADDR       0x10110  // SPI User Command register address
+#define SPI_CMD_CFG1_ADDR            0x10118  // Flash command configuration register 1
+#define MISC_RST_REG_ADDR            0x1000c  // Misc reset register address
+#define MGR_FLASH_RELOAD_REG_ADDR    0x101a0  // MGR reload flash read
+
+#define MAC_ADDR0_WORD0_OFFSET_1G    0x006000c  // MAC Address for LAN0, stored in external FLASH
+#define MAC_ADDR0_WORD1_OFFSET_1G    0x0060014
+#define MAC_ADDR1_WORD0_OFFSET_1G    0x006800c  // MAC Address for LAN1, stored in external FLASH
+#define MAC_ADDR1_WORD1_OFFSET_1G    0x0068014
+#define MAC_ADDR2_WORD0_OFFSET_1G    0x007000c  // MAC Address for LAN2, stored in external FLASH
+#define MAC_ADDR2_WORD1_OFFSET_1G    0x0070014
+#define MAC_ADDR3_WORD0_OFFSET_1G    0x007800c  // MAC Address for LAN3, stored in external FLASH
+#define MAC_ADDR3_WORD1_OFFSET_1G    0x0078014
+#define PRODUCT_SERIAL_NUM_OFFSET_1G    0x00f0000  // Product Serial Number, stored in external FLASH last sector
+
+struct ngbe_hic_read_cab {
+	union ngbe_hic_hdr2 hdr;
+	union {
+		u8 d8[252];
+		u16 d16[126];
+		u32 d32[63];
+	} dbuf;
+};
+
+/**
+ * Packet Type decoding
+ **/
+/* ngbe_dec_ptype.mac: outer mac */
+enum ngbe_dec_ptype_mac {
+	NGBE_DEC_PTYPE_MAC_IP = 0,
+	NGBE_DEC_PTYPE_MAC_L2 = 2,
+	NGBE_DEC_PTYPE_MAC_FCOE = 3,
+};
+
+/* ngbe_dec_ptype.[e]ip: outer&encaped ip */
+#define NGBE_DEC_PTYPE_IP_FRAG (0x4)
+enum ngbe_dec_ptype_ip {
+	NGBE_DEC_PTYPE_IP_NONE = 0,
+	NGBE_DEC_PTYPE_IP_IPV4 = 1,
+	NGBE_DEC_PTYPE_IP_IPV6 = 2,
+	NGBE_DEC_PTYPE_IP_FGV4 =
+		(NGBE_DEC_PTYPE_IP_FRAG | NGBE_DEC_PTYPE_IP_IPV4),
+	NGBE_DEC_PTYPE_IP_FGV6 =
+		(NGBE_DEC_PTYPE_IP_FRAG | NGBE_DEC_PTYPE_IP_IPV6),
+};
+
+/* ngbe_dec_ptype.etype: encaped type */
+enum ngbe_dec_ptype_etype {
+	NGBE_DEC_PTYPE_ETYPE_NONE = 0,
+	NGBE_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
+	NGBE_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
+	NGBE_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
+	NGBE_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
+};
+
+/* ngbe_dec_ptype.proto: payload proto */
+enum ngbe_dec_ptype_prot {
+	NGBE_DEC_PTYPE_PROT_NONE = 0,
+	NGBE_DEC_PTYPE_PROT_UDP = 1,
+	NGBE_DEC_PTYPE_PROT_TCP = 2,
+	NGBE_DEC_PTYPE_PROT_SCTP = 3,
+	NGBE_DEC_PTYPE_PROT_ICMP = 4,
+	NGBE_DEC_PTYPE_PROT_TS = 5, /* time sync */
+};
+
+/* ngbe_dec_ptype.layer: payload layer */
+enum ngbe_dec_ptype_layer {
+	NGBE_DEC_PTYPE_LAYER_NONE = 0,
+	NGBE_DEC_PTYPE_LAYER_PAY2 = 1,
+	NGBE_DEC_PTYPE_LAYER_PAY3 = 2,
+	NGBE_DEC_PTYPE_LAYER_PAY4 = 3,
+};
+
+struct ngbe_dec_ptype {
+	u32 ptype:8;
+	u32 known:1;
+	u32 mac:2; /* outer mac */
+	u32 ip:3; /* outer ip*/
+	u32 etype:3; /* encaped type */
+	u32 eip:3; /* encaped ip */
+	u32 prot:4; /* payload proto */
+	u32 layer:3; /* payload layer */
+};
+typedef struct ngbe_dec_ptype ngbe_dptype;
+
+u16 ngbe_get_pcie_msix_count(struct ngbe_hw *hw);
+s32 ngbe_init_hw(struct ngbe_hw *hw);
+s32 ngbe_start_hw(struct ngbe_hw *hw);
+s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw);
+s32 ngbe_read_pba_string(struct ngbe_hw *hw, u8 *pba_num,
+				  u32 pba_num_size);
+s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr);
+s32 ngbe_get_bus_info(struct ngbe_hw *hw);
+void ngbe_set_pci_config_data(struct ngbe_hw *hw, u16 link_status);
+void ngbe_set_lan_id_multi_port_pcie(struct ngbe_hw *hw);
+s32 ngbe_stop_adapter(struct ngbe_hw *hw);
+
+s32 ngbe_led_on(struct ngbe_hw *hw, u32 index);
+s32 ngbe_led_off(struct ngbe_hw *hw, u32 index);
+
+s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u64 pools,
+			  u32 enable_addr);
+s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index);
+s32 ngbe_init_rx_addrs(struct ngbe_hw *hw);
+s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
+				      u32 mc_addr_count,
+				      ngbe_mc_addr_itr func, bool clear);
+s32 ngbe_update_uc_addr_list(struct ngbe_hw *hw, u8 *addr_list,
+				      u32 addr_count, ngbe_mc_addr_itr func);
+s32 ngbe_enable_mc(struct ngbe_hw *hw);
+s32 ngbe_disable_mc(struct ngbe_hw *hw);
+s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw);
+s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw);
+
+s32 ngbe_fc_enable(struct ngbe_hw *hw);
+void ngbe_fc_autoneg(struct ngbe_hw *hw);
+s32 ngbe_setup_fc(struct ngbe_hw *hw);
+
+s32 ngbe_validate_mac_addr(u8 *mac_addr);
+s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask);
+void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask);
+s32 ngbe_disable_pcie_master(struct ngbe_hw *hw);
+
+s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);
+s32 ngbe_set_vmdq_san_mac(struct ngbe_hw *hw, u32 vmdq);
+s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);
+s32 ngbe_insert_mac_addr(struct ngbe_hw *hw, u8 *addr, u32 vmdq);
+s32 ngbe_init_uta_tables(struct ngbe_hw *hw);
+s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan,
+			 u32 vind, bool vlan_on);
+s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind,
+			   bool vlan_on, bool *vfta_changed);
+s32 ngbe_clear_vfta(struct ngbe_hw *hw);
+s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan);
+
+void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int pf);
+void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf);
+void ngbe_set_ethertype_anti_spoofing(struct ngbe_hw *hw,
+					bool enable, int vf);
+s32 ngbe_get_device_caps(struct ngbe_hw *hw, u16 *device_caps);
+void ngbe_set_rxpba(struct ngbe_hw *hw, int num_pb, u32 headroom,
+			     int strategy);
+s32 ngbe_set_fw_drv_ver(struct ngbe_hw *hw, u8 maj, u8 min,
+				 u8 build, u8 ver);
+s32 ngbe_reset_hostif(struct ngbe_hw *hw);
+u8 ngbe_calculate_checksum(u8 *buffer, u32 length);
+s32 ngbe_host_interface_command(struct ngbe_hw *hw, u32 *buffer,
+				 u32 length, u32 timeout, bool return_data);
+
+void ngbe_clear_tx_pending(struct ngbe_hw *hw);
+void ngbe_stop_mac_link_on_d3(struct ngbe_hw *hw);
+bool ngbe_mng_present(struct ngbe_hw *hw);
+bool ngbe_check_mng_access(struct ngbe_hw *hw);
+
+s32 ngbe_get_thermal_sensor_data(struct ngbe_hw *hw);
+s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw);
+void ngbe_enable_rx(struct ngbe_hw *hw);
+void ngbe_disable_rx(struct ngbe_hw *hw);
+s32 ngbe_setup_mac_link_multispeed_fiber(struct ngbe_hw *hw,
+					  u32 speed,
+					  bool autoneg_wait_to_complete);
+int ngbe_check_flash_load(struct ngbe_hw *hw, u32 check_bit);
+
+/* @ngbe_api.h */
+void ngbe_atr_compute_perfect_hash(union ngbe_atr_input *input,
+					  union ngbe_atr_input *mask);
+u32 ngbe_atr_compute_sig_hash(union ngbe_atr_hash_dword input,
+				     union ngbe_atr_hash_dword common);
+
+s32 ngbe_get_link_capabilities(struct ngbe_hw *hw,
+				      u32 *speed, bool *autoneg);
+enum ngbe_media_type ngbe_get_media_type(struct ngbe_hw *hw);
+void ngbe_disable_tx_laser_multispeed_fiber(struct ngbe_hw *hw);
+void ngbe_enable_tx_laser_multispeed_fiber(struct ngbe_hw *hw);
+void ngbe_flap_tx_laser_multispeed_fiber(struct ngbe_hw *hw);
+void ngbe_set_hard_rate_select_speed(struct ngbe_hw *hw,
+					u32 speed);
+s32 ngbe_setup_mac_link(struct ngbe_hw *hw, u32 speed,
+						bool autoneg_wait_to_complete);
+void ngbe_init_mac_link_ops(struct ngbe_hw *hw);
+s32 ngbe_reset_hw(struct ngbe_hw *hw);
+s32 ngbe_identify_phy(struct ngbe_hw *hw);
+s32 ngbe_init_ops_common(struct ngbe_hw *hw);
+s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval);
+s32 ngbe_init_ops(struct ngbe_hw *hw);
+s32 ngbe_setup_eee(struct ngbe_hw *hw, bool enable_eee);
+
+s32 ngbe_init_flash_params(struct ngbe_hw *hw);
+s32 ngbe_read_flash_buffer(struct ngbe_hw *hw, u32 offset,
+					  u32 dwords, u32 *data);
+s32 ngbe_write_flash_buffer(struct ngbe_hw *hw, u32 offset,
+					  u32 dwords, u32 *data);
+
+s32 ngbe_read_eeprom(struct ngbe_hw *hw,
+				   u16 offset, u16 *data);
+s32 ngbe_read_eeprom_buffer(struct ngbe_hw *hw, u16 offset,
+					  u16 words, u16 *data);
+s32 ngbe_init_eeprom_params(struct ngbe_hw *hw);
+s32 ngbe_update_eeprom_checksum(struct ngbe_hw *hw);
+s32 ngbe_calc_eeprom_checksum(struct ngbe_hw *hw);
+s32 ngbe_validate_eeprom_checksum(struct ngbe_hw *hw,
+					    u16 *checksum_val);
+s32 ngbe_upgrade_flash(struct ngbe_hw *hw, u32 region,
+				const u8 *data, u32 size);
+s32 ngbe_write_ee_hostif_buffer(struct ngbe_hw *hw,
+				u16 offset, u16 words, u16 *data);
+s32 ngbe_write_ee_hostif(struct ngbe_hw *hw, u16 offset,
+				u16 data);
+s32 ngbe_write_ee_hostif32(struct ngbe_hw *hw, u16 offset,
+				u32 data);
+
+s32 ngbe_read_ee_hostif_buffer(struct ngbe_hw *hw,
+				u16 offset, u16 words, u16 *data);
+s32 ngbe_read_ee_hostif(struct ngbe_hw *hw, u16 offset, u16 *data);
+
+s32 ngbe_read_ee_hostif32(struct ngbe_hw *hw, u16 offset, u32 *data);
+
+u32 ngbe_rd32_epcs(struct ngbe_hw *hw, u32 addr);
+void ngbe_wr32_epcs(struct ngbe_hw *hw, u32 addr, u32 data);
+void ngbe_wr32_ephy(struct ngbe_hw *hw, u32 addr, u32 data);
+s32 ngbe_upgrade_flash_hostif(struct ngbe_hw *hw,  u32 region,
+				const u8 *data, u32 size);
+
+s32 ngbe_eepromcheck_cap(struct ngbe_hw *hw, u16 offset,
+							   u32 *data);
+s32 ngbe_phy_signal_set(struct ngbe_hw *hw);
+u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr);
+
+#endif /* _NGBE_HW_H_ */

drivers/net/ethernet/netswift/ngbe/ngbe_mbx.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
+
+#ifndef _NGBE_MBX_H_
+#define _NGBE_MBX_H_
+
+#define NGBE_VXMAILBOX_SIZE    (16)
+
+/**
+ * VF Registers
+ **/
+#define NGBE_VXMAILBOX         0x00600
+#define NGBE_VXMAILBOX_REQ     ((0x1) << 0) /* Request for PF Ready bit */
+#define NGBE_VXMAILBOX_ACK     ((0x1) << 1) /* Ack PF message received */
+#define NGBE_VXMAILBOX_VFU     ((0x1) << 2) /* VF owns the mailbox buffer */
+#define NGBE_VXMAILBOX_PFU     ((0x1) << 3) /* PF owns the mailbox buffer */
+#define NGBE_VXMAILBOX_PFSTS   ((0x1) << 4) /* PF wrote a message in the MB */
+#define NGBE_VXMAILBOX_PFACK   ((0x1) << 5) /* PF ack the previous VF msg */
+#define NGBE_VXMAILBOX_RSTI    ((0x1) << 6) /* PF has reset indication */
+#define NGBE_VXMAILBOX_RSTD    ((0x1) << 7) /* PF has indicated reset done */
+#define NGBE_VXMAILBOX_R2C_BITS (NGBE_VXMAILBOX_RSTD | \
+	    NGBE_VXMAILBOX_PFSTS | NGBE_VXMAILBOX_PFACK)
+
+#define NGBE_VXMBMEM           0x00C00 /* 16*4B */
+
+/**
+ * PF Registers
+ **/
+#define NGBE_PXMAILBOX(i)      (0x00600 + (4 * (i))) /* i=[0,7] */
+#define NGBE_PXMAILBOX_STS     ((0x1) << 0) /* Initiate message send to VF */
+#define NGBE_PXMAILBOX_ACK     ((0x1) << 1) /* Ack message recv'd from VF */
+#define NGBE_PXMAILBOX_VFU     ((0x1) << 2) /* VF owns the mailbox buffer */
+#define NGBE_PXMAILBOX_PFU     ((0x1) << 3) /* PF owns the mailbox buffer */
+#define NGBE_PXMAILBOX_RVFU    ((0x1) << 4) /* Reset VFU - used when VF stuck*/
+
+#define NGBE_PXMBMEM(i)        (0x5000 + (64 * (i))) /* i=[0,7] */
+
+#define NGBE_VFLRP(i)          (0x00490 + (4 * (i))) /* i=[0,1] */
+#define NGBE_VFLRE          0x004A0
+#define NGBE_VFLREC         0x004A8
+
+/* SR-IOV specific macros */
+#define NGBE_MBVFICR             0x00480
+#define NGBE_MBVFICR_INDEX(vf) ((vf) >> 4)
+#define NGBE_MBVFICR_VFREQ_MASK (0x0000FFFF) /* bits for VF messages */
+#define NGBE_MBVFICR_VFREQ_VF1  (0x00000001) /* bit for VF 1 message */
+#define NGBE_MBVFICR_VFACK_MASK (0xFFFF0000) /* bits for VF acks */
+#define NGBE_MBVFICR_VFACK_VF1  (0x00010000) /* bit for VF 1 ack */
+
+/* If it's a NGBE_VF_* msg then it originates in the VF and is sent to the
+ * PF.  The reverse is true if it is NGBE_PF_*.
+ * Message ACK's are the value or'd with 0xF0000000
+ */
+#define NGBE_VT_MSGTYPE_ACK    0x80000000
+#define NGBE_VT_MSGTYPE_NACK   0x40000000
+#define NGBE_VT_MSGTYPE_CTS    0x20000000
+#define NGBE_VT_MSGINFO_SHIFT  16
+/* bits 23:16 are used for extra info for certain messages */
+#define NGBE_VT_MSGINFO_MASK   (0xFF << NGBE_VT_MSGINFO_SHIFT)
+
+/* each element denotes a version of the API; existing numbers may not
+ * change; any additions must go at the end
+ */
+enum ngbe_pfvf_api_rev {
+	ngbe_mbox_api_null,
+	ngbe_mbox_api_10,      /* API version 1.0, linux/freebsd VF driver */
+	ngbe_mbox_api_11,      /* API version 1.1, linux/freebsd VF driver */
+	ngbe_mbox_api_12,      /* API version 1.2, linux/freebsd VF driver */
+	ngbe_mbox_api_13,	/* API version 1.3, linux/freebsd VF driver */
+	ngbe_mbox_api_20,      /* API version 2.0, solaris Phase1 VF driver */
+	ngbe_mbox_api_unknown, /* indicates that API version is not known */
+};
+
+/* mailbox API, legacy requests */
+#define NGBE_VF_RESET          0x01 /* VF requests reset */
+#define NGBE_VF_SET_MAC_ADDR   0x02 /* VF requests PF to set MAC addr */
+#define NGBE_VF_SET_MULTICAST  0x03 /* VF requests PF to set MC addr */
+#define NGBE_VF_SET_VLAN       0x04 /* VF requests PF to set VLAN */
+
+/* mailbox API, version 1.0 VF requests */
+#define NGBE_VF_SET_LPE        0x05 /* VF requests PF to set VMOLR.LPE */
+#define NGBE_VF_SET_MACVLAN    0x06 /* VF requests PF for unicast filter */
+#define NGBE_VF_API_NEGOTIATE  0x08 /* negotiate API version */
+
+/* mailbox API, version 1.1 VF requests */
+#define NGBE_VF_GET_QUEUES     0x09 /* get queue configuration */
+
+/* mailbox API, version 1.2 VF requests */
+#define NGBE_VF_GET_RETA      0x0a    /* VF request for RETA */
+#define NGBE_VF_GET_RSS_KEY	0x0b    /* get RSS key */
+#define NGBE_VF_UPDATE_XCAST_MODE	0x0c
+#define NGBE_VF_BACKUP		0x8001 /* VF requests backup */
+
+#define NGBE_VF_GET_LINK_STATUS	0x20 /* VF get link status from PF */
+
+/* mode choices for IXGBE_VF_UPDATE_XCAST_MODE */
+enum ngbevf_xcast_modes {
+	NGBEVF_XCAST_MODE_NONE = 0,
+	NGBEVF_XCAST_MODE_MULTI,
+	NGBEVF_XCAST_MODE_ALLMULTI,
+	NGBEVF_XCAST_MODE_PROMISC,
+};
+
+/* GET_QUEUES return data indices within the mailbox */
+#define NGBE_VF_TX_QUEUES      1       /* number of Tx queues supported */
+#define NGBE_VF_RX_QUEUES      2       /* number of Rx queues supported */
+#define NGBE_VF_TRANS_VLAN     3       /* Indication of port vlan */
+#define NGBE_VF_DEF_QUEUE      4       /* Default queue offset */
+
+/* length of permanent address message returned from PF */
+#define NGBE_VF_PERMADDR_MSG_LEN       4
+/* word in permanent address message with the current multicast type */
+#define NGBE_VF_MC_TYPE_WORD           3
+
+#define NGBE_PF_CONTROL_MSG            0x0100 /* PF control message */
+
+/* mailbox API, version 2.0 VF requests */
+#define NGBE_VF_API_NEGOTIATE          0x08 /* negotiate API version */
+#define NGBE_VF_GET_QUEUES             0x09 /* get queue configuration */
+#define NGBE_VF_ENABLE_MACADDR         0x0A /* enable MAC address */
+#define NGBE_VF_DISABLE_MACADDR        0x0B /* disable MAC address */
+#define NGBE_VF_GET_MACADDRS           0x0C /* get all configured MAC addrs */
+#define NGBE_VF_SET_MCAST_PROMISC      0x0D /* enable multicast promiscuous */
+#define NGBE_VF_GET_MTU                0x0E /* get bounds on MTU */
+#define NGBE_VF_SET_MTU                0x0F /* set a specific MTU */
+
+/* mailbox API, version 2.0 PF requests */
+#define NGBE_PF_TRANSPARENT_VLAN       0x0101 /* enable transparent vlan */
+
+#define NGBE_VF_MBX_INIT_TIMEOUT       2000 /* number of retries on mailbox */
+#define NGBE_VF_MBX_INIT_DELAY         500  /* microseconds between retries */
+
+int ngbe_read_mbx(struct ngbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
+int ngbe_write_mbx(struct ngbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
+int ngbe_read_posted_mbx(struct ngbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
+int ngbe_write_posted_mbx(struct ngbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
+int ngbe_check_for_msg(struct ngbe_hw *hw, u16 mbx_id);
+int ngbe_check_for_ack(struct ngbe_hw *hw, u16 mbx_id);
+int ngbe_check_for_rst(struct ngbe_hw *hw, u16 mbx_id);
+void ngbe_init_mbx_ops(struct ngbe_hw *hw);
+void ngbe_init_mbx_params_vf(struct ngbe_hw *hw);
+void ngbe_init_mbx_params_pf(struct ngbe_hw *hw);
+
+#endif /* _NGBE_MBX_H_ */

drivers/net/ethernet/netswift/ngbe/ngbe_pcierr.h

+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
+
+#ifndef _NGBE_PCIERR_H_
+#define _NGBE_PCIERR_H_
+
+void ngbe_pcie_do_recovery(struct pci_dev *dev);
+#endif