提交 86f93c93 编写于 作者: A Amit Kucheria 提交者: Andy Gross

arm64: dts: msm8998: efficiency is not valid property

efficiency comes from downstream. The valid upstream property is
capacity-dmips-mhz but until we can come up with those numbers, remove
this property.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>
上级 50325048
...@@ -78,7 +78,6 @@ ...@@ -78,7 +78,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
L2_0: l2-cache { L2_0: l2-cache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -97,7 +96,6 @@ ...@@ -97,7 +96,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
L1_I_1: l1-icache { L1_I_1: l1-icache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -112,7 +110,6 @@ ...@@ -112,7 +110,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
L1_I_2: l1-icache { L1_I_2: l1-icache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -127,7 +124,6 @@ ...@@ -127,7 +124,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
L1_I_3: l1-icache { L1_I_3: l1-icache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -142,7 +138,6 @@ ...@@ -142,7 +138,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
L2_1: l2-cache { L2_1: l2-cache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -161,7 +156,6 @@ ...@@ -161,7 +156,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
L1_I_101: l1-icache { L1_I_101: l1-icache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -176,7 +170,6 @@ ...@@ -176,7 +170,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x102>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
L1_I_102: l1-icache { L1_I_102: l1-icache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
...@@ -191,7 +184,6 @@ ...@@ -191,7 +184,6 @@
compatible = "arm,armv8"; compatible = "arm,armv8";
reg = <0x0 0x103>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
L1_I_103: l1-icache { L1_I_103: l1-icache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册