未验证 提交 866cc5dd 编写于 作者: O openeuler-ci-bot 提交者: Gitee

!842 net: hns3: add support for Hisilicon ptp sync device

Merge Pull Request from: @svishen 
 
This pull Requests support hns3 driver provide ptp driver to get 1588 clock from ethernet.
But only the first PF on main chip can support this, so if getting ptp time from other chip, 
may have some bus latency. The PTP sync device use to eliminate the bus latency.

issue:
https://gitee.com/openeuler/kernel/issues/I78MGV 
 
Link:https://gitee.com/openeuler/kernel/pulls/842 

Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com> 
......@@ -8065,6 +8065,11 @@ S: Maintained
W: http://www.hisilicon.com
F: drivers/spi/spi-hisi-sfc-v3xx.c
HISILICON HNS3 PTP SYNC DRIVER
M: Yonglong Liu <liuyonglong@huawei.com>
S: Supported
F: drivers/ptp/ptp_hisi.c
HMM - Heterogeneous Memory Management
M: Jérôme Glisse <jglisse@redhat.com>
L: linux-mm@kvack.org
......
......@@ -3612,6 +3612,7 @@ CONFIG_DP83640_PHY=m
# CONFIG_PTP_1588_CLOCK_INES is not set
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
CONFIG_PTP_HISI=m
# end of PTP clock support
CONFIG_PINCTRL=y
......
......@@ -154,4 +154,15 @@ config PTP_1588_CLOCK_VMW
To compile this driver as a module, choose M here: the module
will be called ptp_vmw.
config PTP_HISI
tristate "HiSilicon PTP sync platform driver"
help
PTP sync driver work on multichip system, eliminates the bus latency
between multichip, and provide a higher precision clock source. But
the clock source of PTP sync device is from the RTC of HNS3 ethernet
device, so, if you want the PTP sync device works, you must enable
HNS3 driver also.
If unsure, say N.
endmenu
......@@ -15,3 +15,4 @@ ptp-qoriq-$(CONFIG_DEBUG_FS) += ptp_qoriq_debugfs.o
obj-$(CONFIG_PTP_1588_CLOCK_IDTCM) += ptp_clockmatrix.o
obj-$(CONFIG_PTP_1588_CLOCK_IDT82P33) += ptp_idt82p33.o
obj-$(CONFIG_PTP_1588_CLOCK_VMW) += ptp_vmw.o
obj-$(CONFIG_PTP_HISI) += ptp_hisi.o
此差异已折叠。
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