提交 7f8a193d 编写于 作者: M Miquel Raynal 提交者: Zheng Zengkai

mtd: rawnand: arasan: Support NV-DDR interface

stable inclusion
from stable-v5.10.137
commit dc0e4a10b49d0d9569cc5fb5a4edf53e795994ba
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I60PLB

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=dc0e4a10b49d0d9569cc5fb5a4edf53e795994ba

--------------------------------

[ Upstream commit 4edde603 ]

Add support for the NV-DDR interface.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-23-miquel.raynal@bootlin.comSigned-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: NWei Li <liwei391@huawei.com>
上级 74f7bc61
...@@ -885,25 +885,38 @@ static int anfc_setup_interface(struct nand_chip *chip, int target, ...@@ -885,25 +885,38 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
struct arasan_nfc *nfc = to_anfc(chip->controller); struct arasan_nfc *nfc = to_anfc(chip->controller);
struct device_node *np = nfc->dev->of_node; struct device_node *np = nfc->dev->of_node;
const struct nand_sdr_timings *sdr; const struct nand_sdr_timings *sdr;
const struct nand_nvddr_timings *nvddr;
sdr = nand_get_sdr_timings(conf);
if (IS_ERR(sdr)) if (nand_interface_is_nvddr(conf)) {
return PTR_ERR(sdr); nvddr = nand_get_nvddr_timings(conf);
if (IS_ERR(nvddr))
return PTR_ERR(nvddr);
} else {
sdr = nand_get_sdr_timings(conf);
if (IS_ERR(sdr))
return PTR_ERR(sdr);
}
if (target < 0) if (target < 0)
return 0; return 0;
anand->timings = DIFACE_SDR | DIFACE_SDR_MODE(conf->timings.mode); if (nand_interface_is_sdr(conf))
anand->timings = DIFACE_SDR |
DIFACE_SDR_MODE(conf->timings.mode);
else
anand->timings = DIFACE_NVDDR |
DIFACE_DDR_MODE(conf->timings.mode);
anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
/* /*
* Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
* with f > 90MHz (default clock is 100MHz) but signals are unstable * with f > 90MHz (default clock is 100MHz) but signals are unstable
* with higher modes. Hence we decrease a little bit the clock rate to * with higher modes. Hence we decrease a little bit the clock rate to
* 80MHz when using modes 2-5 with this SoC. * 80MHz when using SDR modes 2-5 with this SoC.
*/ */
if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") && if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
conf->timings.mode >= 2) nand_interface_is_sdr(conf) && conf->timings.mode >= 2)
anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK; anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;
return 0; return 0;
......
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