“befe81243a78b37167fd0199f7f150ea1802b0c8”上不存在“...modeling/git@gitcode.net:paddlepaddle/PaddleDetection.git”
提交 7d8e18e4 编写于 作者: A Arend van Spriel 提交者: John W. Linville

brcm80211: smac: replace ai_corereg() function with ai_cc_reg()

The ai_corereg() function is only used in the driver to safely
access the chipcommon core. The function has been renamed to
ai_cc_reg() removing the need to provide a core index parameter.
Reviewed-by: NPieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: NAlwin Beukers <alwin@broadcom.com>
Signed-off-by: NArend van Spriel <arend@broadcom.com>
Signed-off-by: NFranky Lin <frankyl@broadcom.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 ad5db131
...@@ -885,8 +885,8 @@ static struct si_info *ai_doattach(struct si_info *sii, ...@@ -885,8 +885,8 @@ static struct si_info *ai_doattach(struct si_info *sii,
w = getintvar(sih, BRCMS_SROM_LEDDC); w = getintvar(sih, BRCMS_SROM_LEDDC);
if (w == 0) if (w == 0)
w = DEFAULT_GPIOTIMERVAL; w = DEFAULT_GPIOTIMERVAL;
ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, gpiotimerval), ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
~0, w); ~0, w);
if (PCIE(sih)) if (PCIE(sih))
pcicore_attach(sii->pch, SI_DOATTACH); pcicore_attach(sii->pch, SI_DOATTACH);
...@@ -898,10 +898,9 @@ static struct si_info *ai_doattach(struct si_info *sii, ...@@ -898,10 +898,9 @@ static struct si_info *ai_doattach(struct si_info *sii,
*/ */
if (ai_get_chiprev(sih) == 0) { if (ai_get_chiprev(sih) == 0) {
SI_MSG("Applying 43224A0 WARs\n"); SI_MSG("Applying 43224A0 WARs\n");
ai_corereg(sih, SI_CC_IDX, ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol),
offsetof(struct chipcregs, chipcontrol), CCTRL43224_GPIO_TOGGLE,
CCTRL43224_GPIO_TOGGLE, CCTRL43224_GPIO_TOGGLE);
CCTRL43224_GPIO_TOGGLE);
si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE, si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
CCTRL_43224A0_12MA_LED_DRIVE); CCTRL_43224A0_12MA_LED_DRIVE);
} }
...@@ -1104,41 +1103,32 @@ void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val) ...@@ -1104,41 +1103,32 @@ void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val)
* Also, when using pci/pcie, we can optimize away the core switching for pci * Also, when using pci/pcie, we can optimize away the core switching for pci
* registers and (on newer pci cores) chipcommon registers. * registers and (on newer pci cores) chipcommon registers.
*/ */
uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask, uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
uint val)
{ {
struct bcma_device *cc;
uint origidx = 0; uint origidx = 0;
u32 __iomem *r = NULL; u32 w;
uint w;
uint intr_val = 0; uint intr_val = 0;
struct si_info *sii; struct si_info *sii;
sii = (struct si_info *)sih; sii = (struct si_info *)sih;
cc = sii->icbus->drv_cc.core;
if (coreidx >= SI_MAXCORES)
return 0;
INTR_OFF(sii, intr_val); INTR_OFF(sii, intr_val);
/* save current core index */ /* save current core index */
origidx = ai_coreidx(&sii->pub); origidx = ai_coreidx(&sii->pub);
/* switch core */
r = (u32 __iomem *) ((unsigned char __iomem *)
ai_setcoreidx(&sii->pub, coreidx) + regoff);
/* mask and set */ /* mask and set */
if (mask || val) { if (mask || val) {
w = (R_REG(r) & ~mask) | val; bcma_maskset32(cc, regoff, ~mask, val);
W_REG(r, w);
} }
/* readback */ /* readback */
w = R_REG(r); w = bcma_read32(cc, regoff);
/* restore core index */ /* restore core index */
if (origidx != coreidx) ai_setcoreidx(&sii->pub, origidx);
ai_setcoreidx(&sii->pub, origidx);
INTR_RESTORE(sii, intr_val); INTR_RESTORE(sii, intr_val);
...@@ -1664,7 +1654,7 @@ u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority) ...@@ -1664,7 +1654,7 @@ u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
uint regoff; uint regoff;
regoff = offsetof(struct chipcregs, gpiocontrol); regoff = offsetof(struct chipcregs, gpiocontrol);
return ai_corereg(sih, SI_CC_IDX, regoff, mask, val); return ai_cc_reg(sih, regoff, mask, val);
} }
void ai_chipcontrl_epa4331(struct si_pub *sih, bool on) void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
......
...@@ -228,8 +228,6 @@ extern bool ai_iscoreup(struct si_pub *sih); ...@@ -228,8 +228,6 @@ extern bool ai_iscoreup(struct si_pub *sih);
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val); extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val); extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val); extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits); extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(struct si_pub *sih, u32 bits); extern void ai_core_disable(struct si_pub *sih, u32 bits);
extern int ai_numaddrspaces(struct si_pub *sih); extern int ai_numaddrspaces(struct si_pub *sih);
...@@ -242,8 +240,7 @@ extern struct si_pub *ai_attach(struct bcma_bus *pbus); ...@@ -242,8 +240,7 @@ extern struct si_pub *ai_attach(struct bcma_bus *pbus);
extern void ai_detach(struct si_pub *sih); extern void ai_detach(struct si_pub *sih);
extern uint ai_coreid(struct si_pub *sih); extern uint ai_coreid(struct si_pub *sih);
extern uint ai_corerev(struct si_pub *sih); extern uint ai_corerev(struct si_pub *sih);
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask, extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
uint val);
extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val); extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val); extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val); extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
......
...@@ -1709,17 +1709,17 @@ void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw) ...@@ -1709,17 +1709,17 @@ void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
{ {
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
ai_corereg(wlc_hw->sih, SI_CC_IDX, ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
offsetof(struct chipcregs, chipcontrol_addr), ~0, 0); ~0, 0);
udelay(1); udelay(1);
ai_corereg(wlc_hw->sih, SI_CC_IDX, ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
offsetof(struct chipcregs, chipcontrol_data), 0x4, 0); 0x4, 0);
udelay(1); udelay(1);
ai_corereg(wlc_hw->sih, SI_CC_IDX, ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
offsetof(struct chipcregs, chipcontrol_data), 0x4, 4); 0x4, 4);
udelay(1); udelay(1);
ai_corereg(wlc_hw->sih, SI_CC_IDX, ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
offsetof(struct chipcregs, chipcontrol_data), 0x4, 0); 0x4, 0);
udelay(1); udelay(1);
} }
......
...@@ -530,12 +530,12 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state) ...@@ -530,12 +530,12 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
case SI_PCIDOWN: case SI_PCIDOWN:
/* turn on serdes PLL down */ /* turn on serdes PLL down */
if (ai_get_buscorerev(sih) == 6) { if (ai_get_buscorerev(sih) == 6) {
ai_corereg(sih, SI_CC_IDX, ai_cc_reg(sih,
offsetof(struct chipcregs, chipcontrol_addr), offsetof(struct chipcregs, chipcontrol_addr),
~0, 0); ~0, 0);
ai_corereg(sih, SI_CC_IDX, ai_cc_reg(sih,
offsetof(struct chipcregs, chipcontrol_data), offsetof(struct chipcregs, chipcontrol_data),
~0x40, 0); ~0x40, 0);
} else if (pi->pcie_pr42767) { } else if (pi->pcie_pr42767) {
pcie_clkreq(pi, 1, 1); pcie_clkreq(pi, 1, 1);
} }
...@@ -543,12 +543,12 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state) ...@@ -543,12 +543,12 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
case SI_PCIUP: case SI_PCIUP:
/* turn off serdes PLL down */ /* turn off serdes PLL down */
if (ai_get_buscorerev(sih) == 6) { if (ai_get_buscorerev(sih) == 6) {
ai_corereg(sih, SI_CC_IDX, ai_cc_reg(sih,
offsetof(struct chipcregs, chipcontrol_addr), offsetof(struct chipcregs, chipcontrol_addr),
~0, 0); ~0, 0);
ai_corereg(sih, SI_CC_IDX, ai_cc_reg(sih,
offsetof(struct chipcregs, chipcontrol_data), offsetof(struct chipcregs, chipcontrol_data),
~0x40, 0x40); ~0x40, 0x40);
} else if (PCIE_ASPM(sih)) { /* disable clkreq */ } else if (PCIE_ASPM(sih)) { /* disable clkreq */
pcie_clkreq(pi, 1, 0); pcie_clkreq(pi, 1, 0);
} }
...@@ -666,8 +666,8 @@ static void pcie_war_noplldown(struct pcicore_info *pi) ...@@ -666,8 +666,8 @@ static void pcie_war_noplldown(struct pcicore_info *pi)
u16 __iomem *reg16; u16 __iomem *reg16;
/* turn off serdes PLL down */ /* turn off serdes PLL down */
ai_corereg(pi->sih, SI_CC_IDX, offsetof(struct chipcregs, chipcontrol), ai_cc_reg(pi->sih, offsetof(struct chipcregs, chipcontrol),
CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN); CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
/* clear srom shadow backdoor */ /* clear srom shadow backdoor */
reg16 = &pcieregs->sprom[SRSH_BD_OFFSET]; reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
......
...@@ -2905,29 +2905,29 @@ void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode) ...@@ -2905,29 +2905,29 @@ void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2); mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
} }
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, gpiocontrol), offsetof(struct chipcregs, gpiocontrol),
~0x0, 0x0); ~0x0, 0x0);
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, gpioout), 0x40, offsetof(struct chipcregs, gpioout),
0x40); 0x40, 0x40);
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, gpioouten), 0x40, offsetof(struct chipcregs, gpioouten),
0x40); 0x40, 0x40);
} else { } else {
mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2); mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2); mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, gpioout), 0x40, offsetof(struct chipcregs, gpioout),
0x00); 0x40, 0x00);
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, gpioouten), 0x40, offsetof(struct chipcregs, gpioouten),
0x0); 0x40, 0x0);
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, gpiocontrol), offsetof(struct chipcregs, gpiocontrol),
~0x0, 0x40); ~0x0, 0x40);
} }
} }
} }
......
...@@ -19461,9 +19461,9 @@ void wlc_phy_init_nphy(struct brcms_phy *pi) ...@@ -19461,9 +19461,9 @@ void wlc_phy_init_nphy(struct brcms_phy *pi)
(pi->sh->chippkg == BCM4718_PKG_ID))) { (pi->sh->chippkg == BCM4718_PKG_ID))) {
if ((pi->sh->boardflags & BFL_EXTLNA) && if ((pi->sh->boardflags & BFL_EXTLNA) &&
(CHSPEC_IS2G(pi->radio_chanspec))) (CHSPEC_IS2G(pi->radio_chanspec)))
ai_corereg(pi->sh->sih, SI_CC_IDX, ai_cc_reg(pi->sh->sih,
offsetof(struct chipcregs, chipcontrol), offsetof(struct chipcregs, chipcontrol),
0x40, 0x40); 0x40, 0x40);
} }
if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) && if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
......
...@@ -236,38 +236,32 @@ void si_pmu_sprom_enable(struct si_pub *sih, bool enable) ...@@ -236,38 +236,32 @@ void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
/* Read/write a chipcontrol reg */ /* Read/write a chipcontrol reg */
u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val) u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{ {
ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, chipcontrol_addr), ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
~0, reg); return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
return ai_corereg(sih, SI_CC_IDX, mask, val);
offsetof(struct chipcregs, chipcontrol_data), mask,
val);
} }
/* Read/write a regcontrol reg */ /* Read/write a regcontrol reg */
u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val) u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{ {
ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, regcontrol_addr), ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
~0, reg); return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
return ai_corereg(sih, SI_CC_IDX, mask, val);
offsetof(struct chipcregs, regcontrol_data), mask,
val);
} }
/* Read/write a pllcontrol reg */ /* Read/write a pllcontrol reg */
u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val) u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{ {
ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, pllcontrol_addr), ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
~0, reg); return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
return ai_corereg(sih, SI_CC_IDX, mask, val);
offsetof(struct chipcregs, pllcontrol_data), mask,
val);
} }
/* PMU PLL update */ /* PMU PLL update */
void si_pmu_pllupd(struct si_pub *sih) void si_pmu_pllupd(struct si_pub *sih)
{ {
ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, pmucontrol), ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD); PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
} }
/* query alp/xtal clock frequency */ /* query alp/xtal clock frequency */
......
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