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提交 73b07065 编写于 作者: J J.R. Mauro 提交者： Greg Kroah-Hartman
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Staging: sxg: remove typedefs 

Remove typedefs in the sxg driver

Signed-off by: J.R. Mauro <jrm8005@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 1b8ee916
展开全部 隐藏空白更改
内联 并排
Showing with 325 addition and 330 deletion
drivers/staging/sxg/sxg.c
浏览文件 @ 73b07065
此差异已折叠。
drivers/staging/sxg/sxg.h
浏览文件 @ 73b07065
......@@ -45,7 +45,7 @@
#define p_net_device struct net_device *
// SXG_STATS - Probably move these to someplace where
// the slicstat (sxgstat?) program can get them.
typedef struct _SXG_STATS {
struct SXG_STATS {
// Xmt
u32 XmtNBL; // Offload send NBL count
u64 DumbXmtBytes; // Dumbnic send bytes
......@@ -109,7 +109,7 @@ typedef struct _SXG_STATS {
u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC:
u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW:
u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW:
} SXG_STATS, *PSXG_STATS;
};
/****************************************************************************
......@@ -215,12 +215,12 @@ typedef struct _SXG_STATS {
///////////////////////////////////////////////////////////////////////////////
// NOTE - Lock must be held with RCV macros
#define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
PLIST_ENTRY _ple; \
struct LIST_ENTRY *_ple; \
_Hdr = NULL; \
if((_pAdapt)->FreeRcvBufferCount) { \
ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
_ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
(_Hdr) = container_of(_ple, SXG_RCV_DATA_BUFFER_HDR, FreeList); \
(_Hdr) = container_of(_ple, struct SXG_RCV_DATA_BUFFER_HDR, FreeList); \
(_pAdapt)->FreeRcvBufferCount--; \
ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
} \
......@@ -263,12 +263,12 @@ typedef struct _SXG_STATS {
// until after that. We're dealing with round numbers here, so we don't need to,
// and not grabbing it avoids a possible double-trip.
#define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
PLIST_ENTRY _ple; \
struct LIST_ENTRY *_ple; \
if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
(_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
(_pAdapt->AllocationsPending == 0)) { \
sxg_allocate_buffer_memory(_pAdapt, \
(sizeof(SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
(sizeof(struct SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
SXG_BUFFER_TYPE_SGL); \
} \
_Sgl = NULL; \
......@@ -276,7 +276,7 @@ typedef struct _SXG_STATS {
if((_pAdapt)->FreeSglBufferCount) { \
ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
_ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
(_Sgl) = container_of(_ple, SXG_SCATTER_GATHER, FreeList); \
(_Sgl) = container_of(_ple, struct SXG_SCATTER_GATHER, FreeList); \
(_pAdapt)->FreeSglBufferCount--; \
ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
(_Sgl)->State = SXG_BUFFER_BUSY; \
......@@ -289,17 +289,17 @@ typedef struct _SXG_STATS {
// SXG_MULTICAST_ADDRESS
//
// Linked list of multicast addresses.
typedef struct _SXG_MULTICAST_ADDRESS {
struct SXG_MULTICAST_ADDRESS {
unsigned char Address[6];
struct _SXG_MULTICAST_ADDRESS *Next;
} SXG_MULTICAST_ADDRESS, *PSXG_MULTICAST_ADDRESS;
struct SXG_MULTICAST_ADDRESS *Next;
};
// Structure to maintain chimney send and receive buffer queues.
// This structure maintains NET_BUFFER_LIST queues that are
// given to us via the Chimney MiniportTcpOffloadSend and
// MiniportTcpOffloadReceive routines. This structure DOES NOT
// manage our data buffer queue
typedef struct _SXG_BUFFER_QUEUE {
struct SXG_BUFFER_QUEUE {
u32 Type; // Slow or fast - See below
u32 Direction; // Xmt or Rcv
u32 Bytes; // Byte count
......@@ -307,7 +307,7 @@ typedef struct _SXG_BUFFER_QUEUE {
u32 * Tail; // Send queue tail
// PNET_BUFFER_LIST NextNBL; // Short cut - next NBL
// PNET_BUFFER NextNB; // Short cut - next NB
} SXG_BUFFER_QUEUE, *PSXG_BUFFER_QUEUE;
};
#define SXG_SLOW_SEND_BUFFER 0
#define SXG_FAST_SEND_BUFFER 1
......@@ -335,7 +335,7 @@ typedef struct _SXG_BUFFER_QUEUE {
// Adapter states - These states closely match the adapter states
// documented in the DDK (with a few exceptions).
typedef enum _SXG_STATE {
enum SXG_STATE {
SXG_STATE_INITIALIZING, // Initializing
SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode
SXG_STATE_PAUSING, // Pausing
......@@ -347,24 +347,24 @@ typedef enum _SXG_STATE {
SXG_STATE_HALTING, // Halting
SXG_STATE_HALTED, // Down or not-initialized
SXG_STATE_SHUTDOWN // shutdown
} SXG_STATE, *PSXG_STATE;
};
// Link state
typedef enum _SXG_LINK_STATE {
enum SXG_LINK_STATE {
SXG_LINK_DOWN,
SXG_LINK_UP
} SXG_LINK_STATE, *PSXG_LINK_STATE;
};
// Link initialization timeout in 100us units
#define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE!
// Microcode file selection codes
typedef enum _SXG_UCODE_SEL {
enum SXG_UCODE_SEL {
SXG_UCODE_SAHARA, // Sahara ucode
SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode
SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode
} SXG_UCODE_SEL;
};
#define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
......@@ -384,10 +384,10 @@ typedef enum _SXG_UCODE_SEL {
//
// contains information about the sxg driver. There is only
// one of these, and it is defined as a global.
typedef struct _SXG_DRIVER {
struct _adapter_t *Adapters; // Linked list of adapters
struct SXG_DRIVER {
struct adapter_t *Adapters; // Linked list of adapters
ushort AdapterID; // Maintain unique adapter ID
} SXG_DRIVER, *PSXG_DRIVER;
};
#ifdef STATUS_SUCCESS
#undef STATUS_SUCCESS
......@@ -416,11 +416,10 @@ typedef struct _SXG_DRIVER {
#define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
#define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
typedef struct _mcast_address_t
{
struct mcast_address_t {
unsigned char address[6];
struct _mcast_address_t *next;
} mcast_address_t, *p_mcast_address_t;
struct mcast_address_t *next;
};
#define CARD_DOWN 0x00000000
#define CARD_UP 0x00000001
......@@ -472,41 +471,37 @@ typedef struct _mcast_address_t
#define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
typedef struct _ether_header
{
struct ether_header {
unsigned char ether_dhost[6];
unsigned char ether_shost[6];
ushort ether_type;
} ether_header, *p_ether_header;
};
#define NUM_CFG_SPACES 2
#define NUM_CFG_REGS 64
typedef struct _physcard_t
{
struct _adapter_t *adapter[SLIC_MAX_PORTS];
struct _physcard_t *next;
struct physcard_t {
struct adapter_t *adapter[SLIC_MAX_PORTS];
struct physcard_t *next;
unsigned int adapters_allocd;
} physcard_t, *p_physcard_t;
};
typedef struct _sxgbase_driver
{
struct sxgbase_driver_t {
spinlock_t driver_lock;
unsigned long flags; /* irqsave for spinlock */
u32 num_sxg_cards;
u32 num_sxg_ports;
u32 num_sxg_ports_active;
u32 dynamic_intagg;
p_physcard_t phys_card;
} sxgbase_driver_t;
struct physcard_t *phys_card;
};
typedef struct _adapter_t
{
struct adapter_t {
void * ifp;
unsigned int port;
p_physcard_t physcard;
struct physcard_t *physcard;
unsigned int physport;
unsigned int cardindex;
unsigned int card_size;
......@@ -544,7 +539,7 @@ typedef struct _adapter_t
u32 macopts;
ushort devflags_prev;
u64 mcastmask;
p_mcast_address_t mcastaddrs;
struct mcast_address_t *mcastaddrs;
struct timer_list pingtimer;
u32 pingtimerset;
struct timer_list statstimer;
......@@ -580,11 +575,11 @@ typedef struct _adapter_t
u32 intagg_period;
struct net_device_stats stats;
u32 * MiniportHandle; // Our miniport handle
SXG_STATE State; // Adapter state
SXG_LINK_STATE LinkState; // Link state
enum SXG_STATE State; // Adapter state
enum SXG_LINK_STATE LinkState; // Link state
u64 LinkSpeed; // Link Speed
u32 PowerState; // NDIS power state
struct _adapter_t *Next; // Linked list
struct adapter_t *Next; // Linked list
ushort AdapterID; // 1..n
unsigned char MacAddr[6]; // Our permanent HW mac address
unsigned char CurrMacAddr[6]; // Our Current mac address
......@@ -592,16 +587,16 @@ typedef struct _adapter_t
p_net_device next_netdevice;
struct pci_dev * pcidev;
PSXG_MULTICAST_ADDRESS MulticastAddrs; // Multicast list
struct SXG_MULTICAST_ADDRESS *MulticastAddrs; // Multicast list
u64 MulticastMask; // Multicast mask
u32 * InterruptHandle; // Register Interrupt handle
u32 InterruptLevel; // From Resource list
u32 InterruptVector; // From Resource list
spinlock_t AdapterLock; /* Serialize access adapter routines */
spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
PSXG_HW_REGS HwRegs; // Sahara HW Register Memory (BAR0/1)
PSXG_UCODE_REGS UcodeRegs; // Microcode Register Memory (BAR2/3)
PSXG_TCB_REGS TcbRegs; // Same as Ucode regs - See sxghw.h
struct SXG_HW_REGS *HwRegs; // Sahara HW Register Memory (BAR0/1)
struct SXG_UCODE_REGS *UcodeRegs; // Microcode Register Memory (BAR2/3)
struct SXG_TCB_REGS *TcbRegs; // Same as Ucode regs - See sxghw.h
ushort ResetDpcCount; // For timeout
ushort RssDpcCount; // For timeout
ushort VendorID; // Vendor ID
......@@ -613,25 +608,25 @@ typedef struct _adapter_t
u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
u32 MacFilter; // NDIS MAC Filter
ushort IpId; // For slowpath
PSXG_EVENT_RING EventRings; // Host event rings. 1/CPU to 16 max
struct SXG_EVENT_RING *EventRings; // Host event rings. 1/CPU to 16 max
dma_addr_t PEventRings; // Physical address
u32 NextEvent[SXG_MAX_RSS]; // Current location in ring
dma_addr_t PTcbBuffers; // TCB Buffers - physical address
dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr
PSXG_XMT_RING XmtRings; // Transmit rings
struct SXG_XMT_RING *XmtRings; // Transmit rings
dma_addr_t PXmtRings; // Transmit rings - physical address
SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info
struct SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info
spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
u32 * XmtRingZeroIndex; // Shared XMT ring 0 index
dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical
LIST_ENTRY FreeProtocolHeaders;// Free protocol headers
struct LIST_ENTRY FreeProtocolHeaders;// Free protocol headers
u32 FreeProtoHdrCount; // Count
void * ProtocolHeaders; // Block of protocol header
dma_addr_t PProtocolHeaders; // Block of protocol headers - phys
PSXG_RCV_RING RcvRings; // Receive rings
struct SXG_RCV_RING *RcvRings; // Receive rings
dma_addr_t PRcvRings; // Receive rings - physical address
SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info
struct SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info
u32 * Isr; // Interrupt status register
dma_addr_t PIsr; // ISR - physical address
......@@ -645,9 +640,9 @@ typedef struct _adapter_t
u32 HashInformation;
// Receive buffer queues
spinlock_t RcvQLock; /* Receive Queue Lock */
LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue
LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q
LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs
struct LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue
struct LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q
struct LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs
ushort FreeRcvBufferCount; // Number of free rcv data buffers
ushort FreeRcvBlockCount; // # of free rcv descriptor blocks
ushort AllRcvBlockCount; // Number of total receive blocks
......@@ -656,8 +651,8 @@ typedef struct _adapter_t
u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card
// SGL buffers
spinlock_t SglQLock; /* SGL Queue Lock */
LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER
LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER
struct LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER
struct LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER
ushort FreeSglBufferCount; // Number of free SGL buffers
ushort AllSglBufferCount; // Number of total SGL buffers
u32 CurrentTime; // Tick count
......@@ -679,7 +674,7 @@ typedef struct _adapter_t
// Stats
u32 PendingRcvCount; // Outstanding rcv indications
u32 PendingXmtCount; // Outstanding send requests
SXG_STATS Stats; // Statistics
struct SXG_STATS Stats; // Statistics
u32 ReassBufs; // Number of reassembly buffers
// Card Crash Info
ushort CrashLocation; // Microcode crash location
......@@ -708,7 +703,7 @@ typedef struct _adapter_t
// dma_addr_t PDumpBuffer; // Physical address
//#endif // SXG_FAILURE_DUMP
} adapter_t, *p_adapter_t;
};
#if SLIC_DUMP_ENABLED
#define SLIC_DUMP_REQUESTED 1
......@@ -721,10 +716,10 @@ typedef struct _adapter_t
* structure is written out to the card's SRAM when the microcode panic's.
*
****************************************************************************/
typedef struct _slic_crash_info {
struct slic_crash_info {
ushort cpu_id;
ushort crash_pc;
} slic_crash_info, *p_slic_crash_info;
};
#define CRASH_INFO_OFFSET 0x155C
......
drivers/staging/sxg/sxg_os.h
浏览文件 @ 73b07065
......@@ -44,10 +44,10 @@
#define FALSE (0)
#define TRUE (1)
typedef struct _LIST_ENTRY {
struct _LIST_ENTRY *nle_flink;
struct _LIST_ENTRY *nle_blink;
} list_entry, LIST_ENTRY, *PLIST_ENTRY;
struct LIST_ENTRY {
struct LIST_ENTRY *nle_flink;
struct LIST_ENTRY *nle_blink;
};
#define InitializeListHead(l) \
(l)->nle_flink = (l)->nle_blink = (l)
......@@ -68,10 +68,10 @@ typedef struct _LIST_ENTRY {
/* These two have to be inlined since they return things. */
static __inline PLIST_ENTRY RemoveHeadList(list_entry * l)
static __inline struct LIST_ENTRY *RemoveHeadList(struct LIST_ENTRY *l)
{
list_entry *f;
list_entry *e;
struct LIST_ENTRY *f;
struct LIST_ENTRY *e;
e = l->nle_flink;
f = e->nle_flink;
......@@ -81,10 +81,10 @@ static __inline PLIST_ENTRY RemoveHeadList(list_entry * l)
return (e);
}
static __inline PLIST_ENTRY RemoveTailList(list_entry * l)
static __inline struct LIST_ENTRY *RemoveTailList(struct LIST_ENTRY *l)
{
list_entry *b;
list_entry *e;
struct LIST_ENTRY *b;
struct LIST_ENTRY *e;
e = l->nle_blink;
b = e->nle_blink;
......@@ -96,7 +96,7 @@ static __inline PLIST_ENTRY RemoveTailList(list_entry * l)
#define InsertTailList(l, e) \
do { \
list_entry *b; \
struct LIST_ENTRY *b; \
\
b = (l)->nle_blink; \
(e)->nle_flink = (l); \
......@@ -107,7 +107,7 @@ static __inline PLIST_ENTRY RemoveTailList(list_entry * l)
#define InsertHeadList(l, e) \
do { \
list_entry *f; \
struct LIST_ENTRY *f; \
\
f = (l)->nle_flink; \
(e)->nle_flink = f; \
......
drivers/staging/sxg/sxgdbg.h
浏览文件 @ 73b07065
......@@ -86,7 +86,7 @@ extern ulong ATKTimerDiv;
* needs of the trace entry. Typically they are function call
* parameters.
*/
typedef struct _trace_entry_s {
struct trace_entry_t {
char name[8]; /* 8 character name - like 's'i'm'b'a'r'c'v' */
u32 time; /* Current clock tic */
unsigned char cpu; /* Current CPU */
......@@ -97,7 +97,7 @@ typedef struct _trace_entry_s {
u32 arg2; /* Caller arg2 */
u32 arg3; /* Caller arg3 */
u32 arg4; /* Caller arg4 */
} trace_entry_t, *ptrace_entry_t;
};
/*
* Driver types for driver field in trace_entry_t
......@@ -108,14 +108,13 @@ typedef struct _trace_entry_s {
#define TRACE_ENTRIES 1024
typedef struct _sxg_trace_buffer_t
{
struct sxg_trace_buffer_t {
unsigned int size; /* aid for windbg extension */
unsigned int in; /* Where to add */
unsigned int level; /* Current Trace level */
spinlock_t lock; /* For MP tracing */
trace_entry_t entries[TRACE_ENTRIES];/* The circular buffer */
} sxg_trace_buffer_t;
struct trace_entry_t entries[TRACE_ENTRIES];/* The circular buffer */
};
/*
* The trace levels
......@@ -137,7 +136,7 @@ typedef struct _sxg_trace_buffer_t
#if ATK_TRACE_ENABLED
#define SXG_TRACE_INIT(buffer, tlevel) \
{ \
memset((buffer), 0, sizeof(sxg_trace_buffer_t)); \
memset((buffer), 0, sizeof(struct sxg_trace_buffer_t)); \
(buffer)->level = (tlevel); \
(buffer)->size = TRACE_ENTRIES; \
spin_lock_init(&(buffer)->lock); \
......@@ -154,7 +153,7 @@ typedef struct _sxg_trace_buffer_t
if ((buffer) && ((buffer)->level >= (tlevel))) { \
unsigned int trace_irql = 0; /* ?????? FIX THIS */ \
unsigned int trace_len; \
ptrace_entry_t trace_entry; \
struct trace_entry_t *trace_entry; \
struct timeval timev; \
\
spin_lock(&(buffer)->lock); \
......
drivers/staging/sxg/sxghif.h
浏览文件 @ 73b07065
......@@ -12,7 +12,7 @@
/*******************************************************************************
* UCODE Registers
*******************************************************************************/
typedef struct _SXG_UCODE_REGS {
struct SXG_UCODE_REGS {
// Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0
u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control
u32 RsvdReg1; // Code = 1 - TOE -NA
......@@ -127,7 +127,7 @@ typedef struct _SXG_UCODE_REGS {
// base. As extended codes are added, reduce the first array value in
// the following field
u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33)
} SXG_UCODE_REGS, *PSXG_UCODE_REGS;
};
// Interrupt control register (0) values
#define SXG_ICR_DISABLE 0x00000000
......@@ -169,7 +169,7 @@ typedef struct _SXG_UCODE_REGS {
* is happening is that these registers occupy the "PadEx[15]" areas in the
* SXG_UCODE_REGS definition above
*/
typedef struct _SXG_TCB_REGS {
struct SXG_TCB_REGS {
u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */
u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */
u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */
......@@ -180,7 +180,7 @@ typedef struct _SXG_TCB_REGS {
u32 Rsvd4; /* Code = 7 - TOE NA */
u32 Rsvd5; /* Code = 8 - TOE NA */
u32 Pad[7]; /* Codes 8-15 - Not used. */
} SXG_TCB_REGS, *PSXG_TCB_REGS;
};
/***************************************************************************
* ISR Format
......@@ -272,7 +272,7 @@ typedef struct _SXG_TCB_REGS {
*
*/
#pragma pack(push, 1)
typedef struct _SXG_EVENT {
struct SXG_EVENT {
u32 Pad[1]; // not used
u32 SndUna; // SndUna value
u32 Resid; // receive MDL resid
......@@ -294,7 +294,7 @@ typedef struct _SXG_EVENT {
unsigned char Code; // Event code
unsigned char CommandIndex; // New ring index
unsigned char Status; // Event status
} SXG_EVENT, *PSXG_EVENT;
};
#pragma pack(pop)
// Event code definitions
......@@ -321,9 +321,9 @@ typedef struct _SXG_EVENT {
#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time.
#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16)
typedef struct _SXG_EVENT_RING {
SXG_EVENT Ring[EVENT_RING_SIZE];
} SXG_EVENT_RING, *PSXG_EVENT_RING;
struct SXG_EVENT_RING {
struct SXG_EVENT Ring[EVENT_RING_SIZE];
};
/***************************************************************************
*
......@@ -400,12 +400,12 @@ typedef struct _SXG_EVENT_RING {
#define SXG_MAX_ENTRIES 4096
// Structure and macros to manage a ring
typedef struct _SXG_RING_INFO {
struct SXG_RING_INFO {
unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
unsigned char Tail; // Where we pull off completed entries
ushort Size; // Ring size - Must be multiple of 2
void *Context[SXG_MAX_RING_SIZE]; // Shadow ring
} SXG_RING_INFO, *PSXG_RING_INFO;
};
#define SXG_INITIALIZE_RING(_ring, _size) { \
(_ring).Head = 0; \
......@@ -481,7 +481,7 @@ typedef struct _SXG_RING_INFO {
* |_________|_________|_________|_________|28 0x1c
*/
#pragma pack(push, 1)
typedef struct _SXG_CMD {
struct SXG_CMD {
dma_addr_t Sgl; // Physical address of SGL
union {
struct {
......@@ -518,14 +518,14 @@ typedef struct _SXG_CMD {
unsigned char NotUsed;
} Status;
};
} SXG_CMD, *PSXG_CMD;
};
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct _VLAN_HDR {
struct VLAN_HDR {
ushort VlanTci;
ushort VlanTpid;
} VLAN_HDR, *PVLAN_HDR;
};
#pragma pack(pop)
/*
......@@ -564,22 +564,22 @@ typedef struct _VLAN_HDR {
#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP
#define SXG_SLOWCMD_LSO 0x04 // Large segment send
typedef struct _SXG_XMT_RING {
SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
} SXG_XMT_RING, *PSXG_XMT_RING;
struct SXG_XMT_RING {
struct SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
};
typedef struct _SXG_RCV_RING {
SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
} SXG_RCV_RING, *PSXG_RCV_RING;
struct SXG_RCV_RING {
struct SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
};
/***************************************************************************
* Share memory buffer types - Used to identify asynchronous
* shared memory allocation
***************************************************************************/
typedef enum {
enum SXG_BUFFER_TYPE {
SXG_BUFFER_TYPE_RCV, // Receive buffer
SXG_BUFFER_TYPE_SGL // SGL buffer
} SXG_BUFFER_TYPE;
};
// State for SXG buffers
#define SXG_BUFFER_FREE 0x01
......@@ -670,19 +670,19 @@ typedef enum {
#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers
// Receive buffer header
typedef struct _SXG_RCV_DATA_BUFFER_HDR {
struct SXG_RCV_DATA_BUFFER_HDR {
dma_addr_t PhysicalAddress; // Buffer physical address
// Note - DO NOT USE the VirtualAddress field to locate data.
// Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
void *VirtualAddress; // Start of buffer
LIST_ENTRY FreeList; // Free queue of buffers
struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
struct LIST_ENTRY FreeList; // Free queue of buffers
struct SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
u32 Size; // Buffer size
u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
unsigned char State; // See SXG_BUFFER state above
unsigned char Status; // Event status (to log PUSH)
struct sk_buff *skb; // Double mapped (nbl and pkt)
} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
};
// SxgSlowReceive uses the PACKET (skb) contained
// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
......@@ -693,42 +693,43 @@ typedef struct _SXG_RCV_DATA_BUFFER_HDR {
#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR
// Receive data descriptor
typedef struct _SXG_RCV_DATA_DESCRIPTOR {
struct SXG_RCV_DATA_DESCRIPTOR {
union {
struct sk_buff *VirtualAddress; // Host handle
u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
};
dma_addr_t PhysicalAddress;
} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR;
};
// Receive descriptor block
#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check
typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK;
struct SXG_RCV_DESCRIPTOR_BLOCK {
struct SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
};
// Receive descriptor block header
typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
struct SXG_RCV_DESCRIPTOR_BLOCK_HDR {
void *VirtualAddress; // Start of 2k buffer
dma_addr_t PhysicalAddress; // ..and it's physical address
LIST_ENTRY FreeList; // Free queue of descriptor blocks
struct LIST_ENTRY FreeList; // Free queue of descriptor blocks
unsigned char State; // See SXG_BUFFER state above
} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR;
};
// Receive block header
typedef struct _SXG_RCV_BLOCK_HDR {
struct SXG_RCV_BLOCK_HDR {
void *VirtualAddress; // Start of virtual memory
dma_addr_t PhysicalAddress; // ..and it's physical address
LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
struct LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
};
// Macros to determine data structure offsets into receive block
#define SXG_RCV_BLOCK_SIZE(_Buffersize) \
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK)) + \
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)) + \
(sizeof(SXG_RCV_BLOCK_HDR)))
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK)) + \
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK_HDR)) + \
(sizeof(struct SXG_RCV_BLOCK_HDR)))
#define SXG_RCV_BUFFER_DATA_SIZE(_Buffersize) \
((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
#define SXG_RCV_DATA_BUFFER_HDR_OFFSET(_Buffersize) \
......@@ -737,18 +738,18 @@ typedef struct _SXG_RCV_BLOCK_HDR {
((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK)
#define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize) \
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK)))
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK)))
#define SXG_RCV_BLOCK_HDR_OFFSET(_Buffersize) \
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK)) + \
(sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)))
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK)) + \
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK_HDR)))
// Use the miniport reserved portion of the NBL to locate
// our SXG_RCV_DATA_BUFFER_HDR structure.
typedef struct _SXG_RCV_NBL_RESERVED {
PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
struct SXG_RCV_NBL_RESERVED {
struct SXG_RCV_DATA_BUFFER_HDR *RcvDataBufferHdr;
void *Available;
} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
};
#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
......@@ -760,11 +761,11 @@ typedef struct _SXG_RCV_NBL_RESERVED {
#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
// Self identifying structure type
typedef enum _SXG_SGL_TYPE {
enum SXG_SGL_TYPE {
SXG_SGL_DUMB, // Dumb NIC SGL
SXG_SGL_SLOW, // Slowpath protocol header - see below
SXG_SGL_CHIMNEY // Chimney offload SGL
} SXG_SGL_TYPE, PSXG_SGL_TYPE;
};
// Note - the description below is Microsoft specific
//
......@@ -798,41 +799,41 @@ typedef enum _SXG_SGL_TYPE {
// to the card directly. For x86 systems we must reconstruct
// the SGL. The following structure defines an x64
// formatted SGL entry
typedef struct _SXG_X64_SGE {
struct SXG_X64_SGE {
dma64_addr_t Address; // same as wdm.h
u32 Length; // same as wdm.h
u32 CompilerPad; // The compiler pads to 8-bytes
u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
} SXG_X64_SGE, *PSXG_X64_SGE;
};
typedef struct _SCATTER_GATHER_ELEMENT {
struct SCATTER_GATHER_ELEMENT {
dma64_addr_t Address; // same as wdm.h
u32 Length; // same as wdm.h
u32 CompilerPad; // The compiler pads to 8-bytes
u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
};
typedef struct _SCATTER_GATHER_LIST {
struct SCATTER_GATHER_LIST {
u32 NumberOfElements;
u32 *Reserved;
SCATTER_GATHER_ELEMENT Elements[];
} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
struct SCATTER_GATHER_ELEMENT Elements[];
};
// The card doesn't care about anything except elements, so
// we can leave the u32 * reserved field alone in the following
// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so
// we can specify SXG_X64_SGE and define a fixed number of elements
typedef struct _SXG_X64_SGL {
struct SXG_X64_SGL {
u32 NumberOfElements;
u32 *Reserved;
SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
} SXG_X64_SGL, *PSXG_X64_SGL;
struct SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
};
typedef struct _SXG_SCATTER_GATHER {
SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
struct SXG_SCATTER_GATHER {
enum SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
void *adapter; // Back pointer to adapter
LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
struct LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
struct LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
dma_addr_t PhysicalAddress; // physical address
unsigned char State; // See SXG_BUFFER state above
unsigned char CmdIndex; // Command ring index
......@@ -840,14 +841,14 @@ typedef struct _SXG_SCATTER_GATHER {
u32 Direction; // For asynchronous completions
u32 CurOffset; // Current SGL offset
u32 SglRef; // SGL reference count
VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl
SXG_X64_SGL Sgl; // SGL handed to card
} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER;
struct VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
struct SCATTER_GATHER_LIST *pSgl; // SGL Addr. Possibly &Sgl
struct SXG_X64_SGL Sgl; // SGL handed to card
};
#if defined(CONFIG_X86_64)
#define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
#define SXG_SGL_BUF_SIZE sizeof(SXG_X64_SGL)
#define SXG_SGL_BUF_SIZE sizeof(struct SXG_X64_SGL)
#elif defined(CONFIG_X86)
// Force NDIS to give us it's own buffer so we can reformat to our own
#define SXG_SGL_BUFFER(_SxgSgl) NULL
......
drivers/staging/sxg/sxghw.h
浏览文件 @ 73b07065
......@@ -48,7 +48,7 @@
#define SXG_HWREG_MEMSIZE 0x4000 // 16k
#pragma pack(push, 1)
typedef struct _SXG_HW_REGS {
struct SXG_HW_REGS {
u32 Reset; // Write 0xdead to invoke soft reset
u32 Pad1; // No register defined at offset 4
u32 InterruptMask0; // Deassert legacy interrupt on function 0
......@@ -113,7 +113,7 @@ typedef struct _SXG_HW_REGS {
u32 Software[1920]; // 0x200 - 0x2000 - Software defined (not used)
u32 MsixTable[1024]; // 0x2000 - 0x3000 - MSIX Table
u32 MsixBitArray[1024]; // 0x3000 - 0x4000 - MSIX Pending Bit Array
} SXG_HW_REGS, *PSXG_HW_REGS;
};
#pragma pack(pop)
// Microcode Address Flags
......@@ -519,10 +519,10 @@ typedef struct _SXG_HW_REGS {
#define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned
// PHY Microcode download data structure
typedef struct _PHY_UCODE {
struct PHY_UCODE {
ushort Addr;
ushort Data;
} PHY_UCODE, *PPHY_UCODE;
};
/*****************************************************************************
......@@ -537,7 +537,7 @@ typedef struct _PHY_UCODE {
// all commands - see the Sahara spec for details. Note that this structure is
// only valid when compiled on a little endian machine.
#pragma pack(push, 1)
typedef struct _XMT_DESC {
struct XMT_DESC {
ushort XmtLen; // word 0, bits [15:0] - transmit length
unsigned char XmtCtl; // word 0, bits [23:16] - transmit control byte
unsigned char Cmd; // word 0, bits [31:24] - transmit command plus misc.
......@@ -551,7 +551,7 @@ typedef struct _XMT_DESC {
u32 Rsvd3; // word 5, bits [31:0] - PAD
u32 Rsvd4; // word 6, bits [31:0] - PAD
u32 Rsvd5; // word 7, bits [31:0] - PAD
} XMT_DESC, *PXMT_DESC;
};
#pragma pack(pop)
// XMT_DESC Cmd byte definitions
......@@ -600,7 +600,7 @@ typedef struct _XMT_DESC {
// Format of the 18 byte Receive Buffer returned by the
// Receive Sequencer for received packets
#pragma pack(push, 1)
typedef struct _RCV_BUF_HDR {
struct RCV_BUF_HDR {
u32 Status; // Status word from Rcv Seq Parser
ushort Length; // Rcv packet byte count
union {
......@@ -615,7 +615,7 @@ typedef struct _RCV_BUF_HDR {
unsigned char IpHdrOffset; // IP header offset into packet
u32 TpzHash; // Toeplitz hash
ushort Reserved; // Reserved
} RCV_BUF_HDR, *PRCV_BUF_HDR;
};
#pragma pack(pop)
......@@ -665,28 +665,28 @@ typedef struct _RCV_BUF_HDR {
#pragma pack(push, 1)
/* */
typedef struct _HW_CFG_DATA {
struct HW_CFG_DATA {
ushort Addr;
union {
ushort Data;
ushort Checksum;
};
} HW_CFG_DATA, *PHW_CFG_DATA;
};
/* */
#define NUM_HW_CFG_ENTRIES ((128/sizeof(HW_CFG_DATA)) - 4)
#define NUM_HW_CFG_ENTRIES ((128/sizeof(struct HW_CFG_DATA)) - 4)
/* MAC address */
typedef struct _SXG_CONFIG_MAC {
struct SXG_CONFIG_MAC {
unsigned char MacAddr[6]; /* MAC Address */
} SXG_CONFIG_MAC, *PSXG_CONFIG_MAC;
};
/* */
typedef struct _ATK_FRU {
struct ATK_FRU {
unsigned char PartNum[6];
unsigned char Revision[2];
unsigned char Serial[14];
} ATK_FRU, *PATK_FRU;
};
/* OEM FRU Format types */
#define ATK_FRU_FORMAT 0x0000
......@@ -698,24 +698,24 @@ typedef struct _ATK_FRU {
#define NO_FRU_FORMAT 0xFFFF
/* EEPROM/Flash Format */
typedef struct _SXG_CONFIG {
struct SXG_CONFIG {
/* */
/* Section 1 (128 bytes) */
/* */
ushort MagicWord; /* EEPROM/FLASH Magic code 'A5A5' */
ushort SpiClks; /* SPI bus clock dividers */
HW_CFG_DATA HwCfg[NUM_HW_CFG_ENTRIES];
struct HW_CFG_DATA HwCfg[NUM_HW_CFG_ENTRIES];
/* */
/* */
/* */
ushort Version; /* EEPROM format version */
SXG_CONFIG_MAC MacAddr[4]; /* space for 4 MAC addresses */
ATK_FRU AtkFru; /* FRU information */
struct SXG_CONFIG_MAC MacAddr[4]; /* space for 4 MAC addresses */
struct ATK_FRU AtkFru; /* FRU information */
ushort OemFruFormat; /* OEM FRU format type */
unsigned char OemFru[76]; /* OEM FRU information (optional) */
ushort Checksum; /* Checksum of section 2 */
/* CS info XXXTODO */
} SXG_CONFIG, *PSXG_CONFIG;
};
#pragma pack(pop)
/*****************************************************************************
......
drivers/staging/sxg/sxgphycode.h
浏览文件 @ 73b07065
......@@ -18,7 +18,7 @@
/*
* Download for AEL2005C PHY with SR/LR transceiver (10GBASE-SR or 10GBASE-LR)
*/
static PHY_UCODE PhyUcode[] = {
static struct PHY_UCODE PhyUcode[] = {
/*
* NOTE: An address of 0 is a special case. When the download routine
* sees an address of 0, it does not write to the PHY. Instead, it
......
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