perf/x86/intel/uncore: Add Sapphire Rapids server PCU support

mainline inclusion
from mainline-v5.15-rc1
commit 0654dfdc
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO

Intel-SIG: commit 0654dfdc perf/x86/intel/uncore: Add Sapphire
Rapids server PCU support
This commit is backported for SPR PMU uncore support.

-------------------------------------

The PCU is the primary power controller for the Sapphire Rapids.

Except the name, all the information can be retrieved from the discovery
tables.
Signed-off-by: NKan Liang <kan.liang@linux.intel.com>
Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: NAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-7-git-send-email-kan.liang@linux.intel.comSigned-off-by: NYunying Sun <yunying.sun@intel.com>
Signed-off-by: NAichun Shi <aichun.shi@intel.com>

arch/x86/events/intel/uncore_snbep.c

@@ -5487,6 +5487,10 @@ static struct intel_uncore_type spr_uncore_m2pcie = {
 	.name			= "m2pcie",
 };
 
+static struct intel_uncore_type spr_uncore_pcu = {
+	.name			= "pcu",
+};
+
 #define UNCORE_SPR_NUM_UNCORE_TYPES		12
 
 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5494,7 +5498,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
 	&spr_uncore_iio,
 	&spr_uncore_irp,
 	&spr_uncore_m2pcie,
-	NULL,
+	&spr_uncore_pcu,
 	NULL,
 	NULL,
 	NULL,