提交 7249b79f 编写于 作者: C Catalin Marinas

arm64: Do not flush the D-cache for anonymous pages

The D-cache on AArch64 is VIPT non-aliasing, so there is no need to
flush it for anonymous pages.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Reported-by: NWill Deacon <will.deacon@arm.com>
Acked-by: NWill Deacon <will.deacon@arm.com>
上级 b5b6c9e9
...@@ -77,14 +77,12 @@ void __flush_dcache_page(struct page *page) ...@@ -77,14 +77,12 @@ void __flush_dcache_page(struct page *page)
void __sync_icache_dcache(pte_t pte, unsigned long addr) void __sync_icache_dcache(pte_t pte, unsigned long addr)
{ {
unsigned long pfn; struct page *page = pte_page(pte);
struct page *page;
pfn = pte_pfn(pte); /* no flushing needed for anonymous pages */
if (!pfn_valid(pfn)) if (!page_mapping(page))
return; return;
page = pfn_to_page(pfn);
if (!test_and_set_bit(PG_dcache_clean, &page->flags)) { if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
__flush_dcache_page(page); __flush_dcache_page(page);
__flush_icache_all(); __flush_icache_all();
......
...@@ -339,7 +339,6 @@ void __init paging_init(void) ...@@ -339,7 +339,6 @@ void __init paging_init(void)
bootmem_init(); bootmem_init();
empty_zero_page = virt_to_page(zero_page); empty_zero_page = virt_to_page(zero_page);
__flush_dcache_page(empty_zero_page);
/* /*
* TTBR0 is only used for the identity mapping at this stage. Make it * TTBR0 is only used for the identity mapping at this stage. Make it
......
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