drm/i915/tgl: Use refclk/2 as bypass frequency

Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2.  The 50MHz croclk/2 is only used by hardware
during some power state transitions.

Bspec: 49201
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190905181337.23727-1-matthew.d.roper@intel.comReviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>

drivers/gpu/drm/i915/display/intel_cdclk.c

@@ -1855,8 +1855,6 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
 	u32 val;
 	int div;
 
-	cdclk_state->bypass = 50000;
-
 	val = I915_READ(SKL_DSSM);
 	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
 	default:
@@ -1873,6 +1871,11 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
 		break;
 	}
 
+	if (INTEL_GEN(dev_priv) >= 12)
+		cdclk_state->bypass = cdclk_state->ref / 2;
+	else
+		cdclk_state->bypass = 50000;
+
 	val = I915_READ(BXT_DE_PLL_ENABLE);
 	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
 	    (val & BXT_DE_PLL_LOCK) == 0) {