提交 7110fe47 编写于 作者: D David S. Miller

Merge branch 'aquantia'

David VomLehn says:

====================
net: ethernet: aquantia: Add AQtion 2.5/5 GB NIC driver

This series introduces the AQtion NIC driver for the aQuantia
AQC107/AQC108 network devices.

v1: Initial version
v2: o Make necessary drivers/net/ethernet changes to integrate software
    o Drop intermediate atlantic directory
    o Remove Makefile things only appropriate to out of tree module
      building
v3: o Move changes to drivers/net/ethernet/{Kconfig,Makefile} to the last
      patch to ensure clean bisection.
    o Removed inline attribute aq_hw_write_req() as it was defined in
      only one .c file.
    o #included pci.h in aq_common.h to get struct pci definition.
    o Modified code to unlock based execution flow rather than using a
      flag.
    o Made a number of functions that were only used in a single file
      static.
    o Cleaned up error and return code handling in various places.
    o Remove AQ_CFG_IP_ALIGN definition.
    o Other minor code clean up.
v4: o Using do_div for 64 bit division.
    o Modified NIC statistics code.
    o Using build_skb instead netdev_alloc_skb for single fragment packets.
    o Removed extra aq_nic.o from Makefile
v5: o Removed extra newline at the end of the files.
v6: o Removed unnecessary cast from void*.
    o Reworked strings array for ethtool statistics.
    o Added stringset == ETH_SS_STATS checking.
    o AQ_OBJ_HEADER replaced to aq_obj_header_s struct.
    o AQ_OBJ_SET/TST/CLR macroses replaced to inline functions.
    o Driver sources placed in to atlantic directory.
    o Fixed compilation warnings (Make W=1)
    o Added firmware version checking.
    o Code cleaning.
v7  o Removed unnecessary cast from memory allocation function (aq_ring.c).
v8  o Switched to using kcalloc instead kzalloc.
    o Now provide bus_info for ethtool
    o Used div() to avoid __bad_udelay build error.
Signed-off-by: NAlexander Loktionov <Alexander.Loktionov@aquantia.com>
Signed-off-by: NDmitrii Tarakanov <Dmitrii.Tarakanov@aquantia.com>
Signed-off-by: NPavel Belous <Pavel.Belous@aquantia.com>
Signed-off-by: NDavid M. VomLehn <vomlehn@texas.net>
====================
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
......@@ -29,6 +29,7 @@ source "drivers/net/ethernet/amazon/Kconfig"
source "drivers/net/ethernet/amd/Kconfig"
source "drivers/net/ethernet/apm/Kconfig"
source "drivers/net/ethernet/apple/Kconfig"
source "drivers/net/ethernet/aquantia/Kconfig"
source "drivers/net/ethernet/arc/Kconfig"
source "drivers/net/ethernet/atheros/Kconfig"
source "drivers/net/ethernet/aurora/Kconfig"
......
......@@ -15,6 +15,7 @@ obj-$(CONFIG_NET_VENDOR_AMAZON) += amazon/
obj-$(CONFIG_NET_VENDOR_AMD) += amd/
obj-$(CONFIG_NET_XGENE) += apm/
obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
obj-$(CONFIG_NET_VENDOR_AQUANTIA) += aquantia/
obj-$(CONFIG_NET_VENDOR_ARC) += arc/
obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
obj-$(CONFIG_NET_VENDOR_AURORA) += aurora/
......
#
# aQuantia device configuration
#
config NET_VENDOR_AQUANTIA
bool "aQuantia devices"
default y
---help---
Set this to y if you have an Ethernet network cards that uses the aQuantia
AQC107/AQC108 chipset.
This option does not build any drivers; it casues the aQuantia
drivers that can be built to appear in the list of Ethernet drivers.
if NET_VENDOR_AQUANTIA
config AQTION
tristate "aQuantia AQtion(tm) Support"
depends on PCI && X86_64
---help---
This enables the support for the aQuantia AQtion(tm) Ethernet card.
endif # NET_VENDOR_AQUANTIA
#
# Makefile for the aQuantia device drivers.
#
obj-$(CONFIG_AQTION) += atlantic/
################################################################################
#
# aQuantia Ethernet Controller AQtion Linux Driver
# Copyright(c) 2014-2017 aQuantia Corporation.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along
# with this program. If not, see <http://www.gnu.org/licenses/>.
#
# The full GNU General Public License is included in this distribution in
# the file called "COPYING".
#
# Contact Information: <rdc-drv@aquantia.com>
# aQuantia Corporation, 105 E. Tasman Dr. San Jose, CA 95134, USA
#
################################################################################
#
# Makefile for the AQtion(tm) Ethernet driver
#
obj-$(CONFIG_AQTION) += atlantic.o
atlantic-objs := aq_main.o \
aq_nic.o \
aq_pci_func.o \
aq_vec.o \
aq_ring.o \
aq_hw_utils.o \
aq_ethtool.o \
hw_atl/hw_atl_a0.o \
hw_atl/hw_atl_b0.o \
hw_atl/hw_atl_utils.o \
hw_atl/hw_atl_llh.o
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_cfg.h: Definition of configuration parameters and constants. */
#ifndef AQ_CFG_H
#define AQ_CFG_H
#define AQ_CFG_VECS_DEF 4U
#define AQ_CFG_TCS_DEF 1U
#define AQ_CFG_TXDS_DEF 4096U
#define AQ_CFG_RXDS_DEF 1024U
#define AQ_CFG_IS_POLLING_DEF 0U
#define AQ_CFG_FORCE_LEGACY_INT 0U
#define AQ_CFG_IS_INTERRUPT_MODERATION_DEF 1U
#define AQ_CFG_INTERRUPT_MODERATION_RATE_DEF 0xFFFFU
#define AQ_CFG_IRQ_MASK 0x1FFU
#define AQ_CFG_VECS_MAX 8U
#define AQ_CFG_TCS_MAX 8U
#define AQ_CFG_TX_FRAME_MAX (16U * 1024U)
#define AQ_CFG_RX_FRAME_MAX (4U * 1024U)
/* LRO */
#define AQ_CFG_IS_LRO_DEF 1U
/* RSS */
#define AQ_CFG_RSS_INDIRECTION_TABLE_MAX 128U
#define AQ_CFG_RSS_HASHKEY_SIZE 320U
#define AQ_CFG_IS_RSS_DEF 1U
#define AQ_CFG_NUM_RSS_QUEUES_DEF AQ_CFG_VECS_DEF
#define AQ_CFG_RSS_BASE_CPU_NUM_DEF 0U
#define AQ_CFG_PCI_FUNC_MSIX_IRQS 9U
#define AQ_CFG_PCI_FUNC_PORTS 2U
#define AQ_CFG_SERVICE_TIMER_INTERVAL (2 * HZ)
#define AQ_CFG_POLLING_TIMER_INTERVAL ((unsigned int)(2 * HZ))
#define AQ_CFG_SKB_FRAGS_MAX 32U
#define AQ_CFG_NAPI_WEIGHT 64U
#define AQ_CFG_MULTICAST_ADDRESS_MAX 32U
/*#define AQ_CFG_MAC_ADDR_PERMANENT {0x30, 0x0E, 0xE3, 0x12, 0x34, 0x56}*/
#define AQ_CFG_FC_MODE 3U
#define AQ_CFG_SPEED_MSK 0xFFFFU /* 0xFFFFU==auto_neg */
#define AQ_CFG_IS_AUTONEG_DEF 1U
#define AQ_CFG_MTU_DEF 1514U
#define AQ_CFG_LOCK_TRYS 100U
#define AQ_CFG_DRV_AUTHOR "aQuantia"
#define AQ_CFG_DRV_DESC "aQuantia Corporation(R) Network Driver"
#define AQ_CFG_DRV_NAME "aquantia"
#define AQ_CFG_DRV_VERSION __stringify(NIC_MAJOR_DRIVER_VERSION)"."\
__stringify(NIC_MINOR_DRIVER_VERSION)"."\
__stringify(NIC_BUILD_DRIVER_VERSION)"."\
__stringify(NIC_REVISION_DRIVER_VERSION)
#endif /* AQ_CFG_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_common.h: Basic includes for all files in project. */
#ifndef AQ_COMMON_H
#define AQ_COMMON_H
#include <linux/etherdevice.h>
#include <linux/pci.h>
#include "ver.h"
#include "aq_nic.h"
#include "aq_cfg.h"
#include "aq_utils.h"
#endif /* AQ_COMMON_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_ethtool.c: Definition of ethertool related functions. */
#include "aq_ethtool.h"
#include "aq_nic.h"
static void aq_ethtool_get_regs(struct net_device *ndev,
struct ethtool_regs *regs, void *p)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
u32 regs_count = aq_nic_get_regs_count(aq_nic);
memset(p, 0, regs_count * sizeof(u32));
aq_nic_get_regs(aq_nic, regs, p);
}
static int aq_ethtool_get_regs_len(struct net_device *ndev)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
u32 regs_count = aq_nic_get_regs_count(aq_nic);
return regs_count * sizeof(u32);
}
static u32 aq_ethtool_get_link(struct net_device *ndev)
{
return ethtool_op_get_link(ndev);
}
static int aq_ethtool_get_settings(struct net_device *ndev,
struct ethtool_cmd *cmd)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
aq_nic_get_link_settings(aq_nic, cmd);
ethtool_cmd_speed_set(cmd, netif_carrier_ok(ndev) ?
aq_nic_get_link_speed(aq_nic) : 0U);
return 0;
}
static int aq_ethtool_set_settings(struct net_device *ndev,
struct ethtool_cmd *cmd)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
return aq_nic_set_link_settings(aq_nic, cmd);
}
/* there "5U" is number of queue[#] stats lines (InPackets+...+InErrors) */
static const unsigned int aq_ethtool_stat_queue_lines = 5U;
static const unsigned int aq_ethtool_stat_queue_chars =
5U * ETH_GSTRING_LEN;
static const char aq_ethtool_stat_names[][ETH_GSTRING_LEN] = {
"InPackets",
"InUCast",
"InMCast",
"InBCast",
"InErrors",
"OutPackets",
"OutUCast",
"OutMCast",
"OutBCast",
"InUCastOctects",
"OutUCastOctects",
"InMCastOctects",
"OutMCastOctects",
"InBCastOctects",
"OutBCastOctects",
"InOctects",
"OutOctects",
"InPacketsDma",
"OutPacketsDma",
"InOctetsDma",
"OutOctetsDma",
"InDroppedDma",
"Queue[0] InPackets",
"Queue[0] OutPackets",
"Queue[0] InJumboPackets",
"Queue[0] InLroPackets",
"Queue[0] InErrors",
"Queue[1] InPackets",
"Queue[1] OutPackets",
"Queue[1] InJumboPackets",
"Queue[1] InLroPackets",
"Queue[1] InErrors",
"Queue[2] InPackets",
"Queue[2] OutPackets",
"Queue[2] InJumboPackets",
"Queue[2] InLroPackets",
"Queue[2] InErrors",
"Queue[3] InPackets",
"Queue[3] OutPackets",
"Queue[3] InJumboPackets",
"Queue[3] InLroPackets",
"Queue[3] InErrors",
"Queue[4] InPackets",
"Queue[4] OutPackets",
"Queue[4] InJumboPackets",
"Queue[4] InLroPackets",
"Queue[4] InErrors",
"Queue[5] InPackets",
"Queue[5] OutPackets",
"Queue[5] InJumboPackets",
"Queue[5] InLroPackets",
"Queue[5] InErrors",
"Queue[6] InPackets",
"Queue[6] OutPackets",
"Queue[6] InJumboPackets",
"Queue[6] InLroPackets",
"Queue[6] InErrors",
"Queue[7] InPackets",
"Queue[7] OutPackets",
"Queue[7] InJumboPackets",
"Queue[7] InLroPackets",
"Queue[7] InErrors",
};
static void aq_ethtool_stats(struct net_device *ndev,
struct ethtool_stats *stats, u64 *data)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
/* ASSERT: Need add lines to aq_ethtool_stat_names if AQ_CFG_VECS_MAX > 8 */
BUILD_BUG_ON(AQ_CFG_VECS_MAX > 8);
memset(data, 0, ARRAY_SIZE(aq_ethtool_stat_names) * sizeof(u64));
aq_nic_get_stats(aq_nic, data);
}
static void aq_ethtool_get_drvinfo(struct net_device *ndev,
struct ethtool_drvinfo *drvinfo)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
struct pci_dev *pdev = to_pci_dev(ndev->dev.parent);
u32 firmware_version = aq_nic_get_fw_version(aq_nic);
u32 regs_count = aq_nic_get_regs_count(aq_nic);
strlcat(drvinfo->driver, AQ_CFG_DRV_NAME, sizeof(drvinfo->driver));
strlcat(drvinfo->version, AQ_CFG_DRV_VERSION, sizeof(drvinfo->version));
snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
"%u.%u.%u", firmware_version >> 24,
(firmware_version >> 16) & 0xFFU, firmware_version & 0xFFFFU);
strlcpy(drvinfo->bus_info, pdev ? pci_name(pdev) : "",
sizeof(drvinfo->bus_info));
drvinfo->n_stats = ARRAY_SIZE(aq_ethtool_stat_names) -
(AQ_CFG_VECS_MAX - cfg->vecs) * aq_ethtool_stat_queue_lines;
drvinfo->testinfo_len = 0;
drvinfo->regdump_len = regs_count;
drvinfo->eedump_len = 0;
}
static void aq_ethtool_get_strings(struct net_device *ndev,
u32 stringset, u8 *data)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
if (stringset == ETH_SS_STATS)
memcpy(data, *aq_ethtool_stat_names,
sizeof(aq_ethtool_stat_names) -
(AQ_CFG_VECS_MAX - cfg->vecs) *
aq_ethtool_stat_queue_chars);
}
static int aq_ethtool_get_sset_count(struct net_device *ndev, int stringset)
{
int ret = 0;
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
switch (stringset) {
case ETH_SS_STATS:
ret = ARRAY_SIZE(aq_ethtool_stat_names) -
(AQ_CFG_VECS_MAX - cfg->vecs) *
aq_ethtool_stat_queue_lines;
break;
default:
ret = -EOPNOTSUPP;
}
return ret;
}
static u32 aq_ethtool_get_rss_indir_size(struct net_device *ndev)
{
return AQ_CFG_RSS_INDIRECTION_TABLE_MAX;
}
static u32 aq_ethtool_get_rss_key_size(struct net_device *ndev)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
return sizeof(cfg->aq_rss.hash_secret_key);
}
static int aq_ethtool_get_rss(struct net_device *ndev, u32 *indir, u8 *key,
u8 *hfunc)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
unsigned int i = 0U;
if (hfunc)
*hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */
if (indir) {
for (i = 0; i < AQ_CFG_RSS_INDIRECTION_TABLE_MAX; i++)
indir[i] = cfg->aq_rss.indirection_table[i];
}
if (key)
memcpy(key, cfg->aq_rss.hash_secret_key,
sizeof(cfg->aq_rss.hash_secret_key));
return 0;
}
static int aq_ethtool_get_rxnfc(struct net_device *ndev,
struct ethtool_rxnfc *cmd,
u32 *rule_locs)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
int err = 0;
switch (cmd->cmd) {
case ETHTOOL_GRXRINGS:
cmd->data = cfg->vecs;
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
const struct ethtool_ops aq_ethtool_ops = {
.get_link = aq_ethtool_get_link,
.get_regs_len = aq_ethtool_get_regs_len,
.get_regs = aq_ethtool_get_regs,
.get_settings = aq_ethtool_get_settings,
.set_settings = aq_ethtool_set_settings,
.get_drvinfo = aq_ethtool_get_drvinfo,
.get_strings = aq_ethtool_get_strings,
.get_rxfh_indir_size = aq_ethtool_get_rss_indir_size,
.get_rxfh_key_size = aq_ethtool_get_rss_key_size,
.get_rxfh = aq_ethtool_get_rss,
.get_rxnfc = aq_ethtool_get_rxnfc,
.get_sset_count = aq_ethtool_get_sset_count,
.get_ethtool_stats = aq_ethtool_stats
};
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_ethtool.h: Declaration of ethertool related functions. */
#ifndef AQ_ETHTOOL_H
#define AQ_ETHTOOL_H
#include "aq_common.h"
extern const struct ethtool_ops aq_ethtool_ops;
#endif /* AQ_ETHTOOL_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_hw.h: Declaraion of abstract interface for NIC hardware specific
* functions.
*/
#ifndef AQ_HW_H
#define AQ_HW_H
#include "aq_common.h"
/* NIC H/W capabilities */
struct aq_hw_caps_s {
u64 hw_features;
u64 link_speed_msk;
unsigned int hw_priv_flags;
u32 rxds;
u32 txds;
u32 txhwb_alignment;
u32 irq_mask;
u32 vecs;
u32 mtu;
u32 mac_regs_count;
u8 ports;
u8 msix_irqs;
u8 tcs;
u8 rxd_alignment;
u8 rxd_size;
u8 txd_alignment;
u8 txd_size;
u8 tx_rings;
u8 rx_rings;
bool flow_control;
bool is_64_dma;
u32 fw_ver_expected;
};
struct aq_hw_link_status_s {
unsigned int mbps;
};
#define AQ_HW_IRQ_INVALID 0U
#define AQ_HW_IRQ_LEGACY 1U
#define AQ_HW_IRQ_MSI 2U
#define AQ_HW_IRQ_MSIX 3U
#define AQ_HW_POWER_STATE_D0 0U
#define AQ_HW_POWER_STATE_D3 3U
#define AQ_HW_FLAG_STARTED 0x00000004U
#define AQ_HW_FLAG_STOPPING 0x00000008U
#define AQ_HW_FLAG_RESETTING 0x00000010U
#define AQ_HW_FLAG_CLOSING 0x00000020U
#define AQ_HW_LINK_DOWN 0x04000000U
#define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U
#define AQ_HW_FLAG_ERR_HW 0x80000000U
#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)
struct aq_hw_s {
struct aq_obj_s header;
struct aq_nic_cfg_s *aq_nic_cfg;
struct aq_pci_func_s *aq_pci_func;
void __iomem *mmio;
unsigned int not_ff_addr;
struct aq_hw_link_status_s aq_link_status;
};
struct aq_ring_s;
struct aq_ring_param_s;
struct aq_nic_cfg_s;
struct sk_buff;
struct aq_hw_ops {
struct aq_hw_s *(*create)(struct aq_pci_func_s *aq_pci_func,
unsigned int port, struct aq_hw_ops *ops);
void (*destroy)(struct aq_hw_s *self);
int (*get_hw_caps)(struct aq_hw_s *self,
struct aq_hw_caps_s *aq_hw_caps);
int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
unsigned int frags);
int (*hw_ring_rx_receive)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring);
int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
unsigned int sw_tail_old);
int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring);
int (*hw_get_mac_permanent)(struct aq_hw_s *self,
struct aq_hw_caps_s *aq_hw_caps,
u8 *mac);
int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);
int (*hw_get_link_status)(struct aq_hw_s *self,
struct aq_hw_link_status_s *link_status);
int (*hw_set_link_speed)(struct aq_hw_s *self, u32 speed);
int (*hw_reset)(struct aq_hw_s *self);
int (*hw_init)(struct aq_hw_s *self, struct aq_nic_cfg_s *aq_nic_cfg,
u8 *mac_addr);
int (*hw_start)(struct aq_hw_s *self);
int (*hw_stop)(struct aq_hw_s *self);
int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
struct aq_ring_param_s *aq_ring_param);
int (*hw_ring_tx_start)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring);
int (*hw_ring_tx_stop)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring);
int (*hw_ring_rx_init)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring,
struct aq_ring_param_s *aq_ring_param);
int (*hw_ring_rx_start)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring);
int (*hw_ring_rx_stop)(struct aq_hw_s *self,
struct aq_ring_s *aq_ring);
int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);
int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);
int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);
int (*hw_packet_filter_set)(struct aq_hw_s *self,
unsigned int packet_filter);
int (*hw_multicast_list_set)(struct aq_hw_s *self,
u8 ar_mac[AQ_CFG_MULTICAST_ADDRESS_MAX]
[ETH_ALEN],
u32 count);
int (*hw_interrupt_moderation_set)(struct aq_hw_s *self,
bool itr_enabled);
int (*hw_rss_set)(struct aq_hw_s *self,
struct aq_rss_parameters *rss_params);
int (*hw_rss_hash_set)(struct aq_hw_s *self,
struct aq_rss_parameters *rss_params);
int (*hw_get_regs)(struct aq_hw_s *self,
struct aq_hw_caps_s *aq_hw_caps, u32 *regs_buff);
int (*hw_get_hw_stats)(struct aq_hw_s *self, u64 *data,
unsigned int *p_count);
int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version);
int (*hw_deinit)(struct aq_hw_s *self);
int (*hw_set_power)(struct aq_hw_s *self, unsigned int power_state);
};
#endif /* AQ_HW_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_hw_utils.c: Definitions of helper functions used across
* hardware layer.
*/
#include "aq_hw_utils.h"
#include "aq_hw.h"
void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
u32 shift, u32 val)
{
if (msk ^ ~0) {
u32 reg_old, reg_new;
reg_old = aq_hw_read_reg(aq_hw, addr);
reg_new = (reg_old & (~msk)) | (val << shift);
if (reg_old != reg_new)
aq_hw_write_reg(aq_hw, addr, reg_new);
} else {
aq_hw_write_reg(aq_hw, addr, val);
}
}
u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift)
{
return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift);
}
u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)
{
u32 value = readl(hw->mmio + reg);
if ((~0U) == value && (~0U) == readl(hw->mmio + hw->not_ff_addr))
aq_utils_obj_set(&hw->header.flags, AQ_HW_FLAG_ERR_UNPLUG);
return value;
}
void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)
{
writel(value, hw->mmio + reg);
}
int aq_hw_err_from_flags(struct aq_hw_s *hw)
{
int err = 0;
if (aq_utils_obj_test(&hw->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
err = -ENXIO;
goto err_exit;
}
if (aq_utils_obj_test(&hw->header.flags, AQ_HW_FLAG_ERR_HW)) {
err = -EIO;
goto err_exit;
}
err_exit:
return err;
}
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_hw_utils.h: Declaration of helper functions used across hardware
* layer.
*/
#ifndef AQ_HW_UTILS_H
#define AQ_HW_UTILS_H
#include "aq_common.h"
#ifndef HIDWORD
#define LODWORD(_qw) ((u32)(_qw))
#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff))
#endif
#define AQ_HW_SLEEP(_US_) mdelay(_US_)
#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \
do { \
unsigned int AQ_HW_WAIT_FOR_i; \
for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\
--AQ_HW_WAIT_FOR_i) {\
udelay(_US_); \
} \
if (!AQ_HW_WAIT_FOR_i) {\
err = ETIME; \
} \
} while (0)
struct aq_hw_s;
void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
u32 shift, u32 val);
u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift);
u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);
void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);
int aq_hw_err_from_flags(struct aq_hw_s *hw);
#endif /* AQ_HW_UTILS_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_main.c: Main file for aQuantia Linux driver. */
#include "aq_main.h"
#include "aq_nic.h"
#include "aq_pci_func.h"
#include "aq_ethtool.h"
#include "hw_atl/hw_atl_a0.h"
#include "hw_atl/hw_atl_b0.h"
#include <linux/netdevice.h>
#include <linux/module.h>
static const struct pci_device_id aq_pci_tbl[] = {
{ PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_0001), },
{ PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D100), },
{ PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D107), },
{ PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D108), },
{ PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D109), },
{}
};
MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
MODULE_LICENSE("GPL v2");
MODULE_VERSION(AQ_CFG_DRV_VERSION);
MODULE_AUTHOR(AQ_CFG_DRV_AUTHOR);
MODULE_DESCRIPTION(AQ_CFG_DRV_DESC);
static struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev)
{
struct aq_hw_ops *ops = NULL;
ops = hw_atl_a0_get_ops_by_id(pdev);
if (!ops)
ops = hw_atl_b0_get_ops_by_id(pdev);
return ops;
}
static int aq_ndev_open(struct net_device *ndev)
{
struct aq_nic_s *aq_nic = NULL;
int err = 0;
aq_nic = aq_nic_alloc_hot(ndev);
if (!aq_nic) {
err = -ENOMEM;
goto err_exit;
}
err = aq_nic_init(aq_nic);
if (err < 0)
goto err_exit;
err = aq_nic_start(aq_nic);
if (err < 0)
goto err_exit;
err_exit:
if (err < 0)
aq_nic_deinit(aq_nic);
return err;
}
static int aq_ndev_close(struct net_device *ndev)
{
int err = 0;
struct aq_nic_s *aq_nic = netdev_priv(ndev);
err = aq_nic_stop(aq_nic);
if (err < 0)
goto err_exit;
aq_nic_deinit(aq_nic);
aq_nic_free_hot_resources(aq_nic);
err_exit:
return err;
}
static int aq_ndev_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
int err = 0;
err = aq_nic_xmit(aq_nic, skb);
if (err < 0)
goto err_exit;
err_exit:
return err;
}
static int aq_ndev_change_mtu(struct net_device *ndev, int new_mtu)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
int err = 0;
if (new_mtu == ndev->mtu) {
err = 0;
goto err_exit;
}
if (new_mtu < 68) {
err = -EINVAL;
goto err_exit;
}
err = aq_nic_set_mtu(aq_nic, new_mtu + ETH_HLEN);
if (err < 0)
goto err_exit;
ndev->mtu = new_mtu;
if (netif_running(ndev)) {
aq_ndev_close(ndev);
aq_ndev_open(ndev);
}
err_exit:
return err;
}
static int aq_ndev_set_features(struct net_device *ndev,
netdev_features_t features)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
struct aq_nic_cfg_s *aq_cfg = aq_nic_get_cfg(aq_nic);
bool is_lro = false;
if (aq_cfg->hw_features & NETIF_F_LRO) {
is_lro = features & NETIF_F_LRO;
if (aq_cfg->is_lro != is_lro) {
aq_cfg->is_lro = is_lro;
if (netif_running(ndev)) {
aq_ndev_close(ndev);
aq_ndev_open(ndev);
}
}
}
return 0;
}
static int aq_ndev_set_mac_address(struct net_device *ndev, void *addr)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
int err = 0;
err = eth_mac_addr(ndev, addr);
if (err < 0)
goto err_exit;
err = aq_nic_set_mac(aq_nic, ndev);
if (err < 0)
goto err_exit;
err_exit:
return err;
}
static void aq_ndev_set_multicast_settings(struct net_device *ndev)
{
struct aq_nic_s *aq_nic = netdev_priv(ndev);
int err = 0;
err = aq_nic_set_packet_filter(aq_nic, ndev->flags);
if (err < 0)
goto err_exit;
if (netdev_mc_count(ndev)) {
err = aq_nic_set_multicast_list(aq_nic, ndev);
if (err < 0)
goto err_exit;
}
err_exit:;
}
static const struct net_device_ops aq_ndev_ops = {
.ndo_open = aq_ndev_open,
.ndo_stop = aq_ndev_close,
.ndo_start_xmit = aq_ndev_start_xmit,
.ndo_set_rx_mode = aq_ndev_set_multicast_settings,
.ndo_change_mtu = aq_ndev_change_mtu,
.ndo_set_mac_address = aq_ndev_set_mac_address,
.ndo_set_features = aq_ndev_set_features
};
static int aq_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
struct aq_hw_ops *aq_hw_ops = NULL;
struct aq_pci_func_s *aq_pci_func = NULL;
int err = 0;
err = pci_enable_device(pdev);
if (err < 0)
goto err_exit;
aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev,
&aq_ndev_ops, &aq_ethtool_ops);
if (!aq_pci_func) {
err = -ENOMEM;
goto err_exit;
}
err = aq_pci_func_init(aq_pci_func);
if (err < 0)
goto err_exit;
err_exit:
if (err < 0) {
if (aq_pci_func)
aq_pci_func_free(aq_pci_func);
}
return err;
}
static void aq_pci_remove(struct pci_dev *pdev)
{
struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
aq_pci_func_deinit(aq_pci_func);
aq_pci_func_free(aq_pci_func);
}
static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
{
struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
}
static int aq_pci_resume(struct pci_dev *pdev)
{
struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
pm_message_t pm_msg = PMSG_RESTORE;
return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
}
static struct pci_driver aq_pci_ops = {
.name = AQ_CFG_DRV_NAME,
.id_table = aq_pci_tbl,
.probe = aq_pci_probe,
.remove = aq_pci_remove,
.suspend = aq_pci_suspend,
.resume = aq_pci_resume,
};
static int __init aq_module_init(void)
{
int err = 0;
err = pci_register_driver(&aq_pci_ops);
if (err < 0)
goto err_exit;
err_exit:
return err;
}
static void __exit aq_module_exit(void)
{
pci_unregister_driver(&aq_pci_ops);
}
module_init(aq_module_init);
module_exit(aq_module_exit);
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_main.h: Main file for aQuantia Linux driver. */
#ifndef AQ_MAIN_H
#define AQ_MAIN_H
#include "aq_common.h"
#endif /* AQ_MAIN_H */
此差异已折叠。
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_nic.h: Declaration of common code for NIC. */
#ifndef AQ_NIC_H
#define AQ_NIC_H
#include "aq_common.h"
#include "aq_rss.h"
struct aq_ring_s;
struct aq_pci_func_s;
struct aq_hw_ops;
#define AQ_NIC_FC_OFF 0U
#define AQ_NIC_FC_TX 1U
#define AQ_NIC_FC_RX 2U
#define AQ_NIC_FC_FULL 3U
#define AQ_NIC_FC_AUTO 4U
#define AQ_NIC_RATE_10G BIT(0)
#define AQ_NIC_RATE_5G BIT(1)
#define AQ_NIC_RATE_5GSR BIT(2)
#define AQ_NIC_RATE_2GS BIT(3)
#define AQ_NIC_RATE_1G BIT(4)
#define AQ_NIC_RATE_100M BIT(5)
struct aq_nic_cfg_s {
struct aq_hw_caps_s *aq_hw_caps;
u64 hw_features;
u32 rxds; /* rx ring size, descriptors # */
u32 txds; /* tx ring size, descriptors # */
u32 vecs; /* vecs==allocated irqs */
u32 irq_type;
u32 itr;
u32 num_rss_queues;
u32 mtu;
u32 ucp_0x364;
u32 flow_control;
u32 link_speed_msk;
u32 vlan_id;
u16 is_mc_list_enabled;
u16 mc_list_count;
bool is_autoneg;
bool is_interrupt_moderation;
bool is_polling;
bool is_rss;
bool is_lro;
u8 tcs;
struct aq_rss_parameters aq_rss;
};
#define AQ_NIC_FLAG_STARTED 0x00000004U
#define AQ_NIC_FLAG_STOPPING 0x00000008U
#define AQ_NIC_FLAG_RESETTING 0x00000010U
#define AQ_NIC_FLAG_CLOSING 0x00000020U
#define AQ_NIC_LINK_DOWN 0x04000000U
#define AQ_NIC_FLAG_ERR_UNPLUG 0x40000000U
#define AQ_NIC_FLAG_ERR_HW 0x80000000U
#define AQ_NIC_TCVEC2RING(_NIC_, _TC_, _VEC_) \
((_TC_) * AQ_CFG_TCS_MAX + (_VEC_))
struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
const struct ethtool_ops *et_ops,
struct device *dev,
struct aq_pci_func_s *aq_pci_func,
unsigned int port,
const struct aq_hw_ops *aq_hw_ops);
int aq_nic_ndev_init(struct aq_nic_s *self);
struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
struct aq_ring_s *ring);
struct device *aq_nic_get_dev(struct aq_nic_s *self);
struct net_device *aq_nic_get_ndev(struct aq_nic_s *self);
int aq_nic_init(struct aq_nic_s *self);
int aq_nic_cfg_start(struct aq_nic_s *self);
int aq_nic_ndev_register(struct aq_nic_s *self);
void aq_nic_ndev_queue_start(struct aq_nic_s *self, unsigned int idx);
void aq_nic_ndev_queue_stop(struct aq_nic_s *self, unsigned int idx);
void aq_nic_ndev_free(struct aq_nic_s *self);
int aq_nic_start(struct aq_nic_s *self);
int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb);
int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p);
int aq_nic_get_regs_count(struct aq_nic_s *self);
void aq_nic_get_stats(struct aq_nic_s *self, u64 *data);
int aq_nic_stop(struct aq_nic_s *self);
void aq_nic_deinit(struct aq_nic_s *self);
void aq_nic_free_hot_resources(struct aq_nic_s *self);
int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu);
int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev);
int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags);
int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev);
unsigned int aq_nic_get_link_speed(struct aq_nic_s *self);
void aq_nic_get_link_settings(struct aq_nic_s *self, struct ethtool_cmd *cmd);
int aq_nic_set_link_settings(struct aq_nic_s *self, struct ethtool_cmd *cmd);
struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self);
u32 aq_nic_get_fw_version(struct aq_nic_s *self);
int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg);
#endif /* AQ_NIC_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_nic_internal.h: Definition of private object structure. */
#ifndef AQ_NIC_INTERNAL_H
#define AQ_NIC_INTERNAL_H
struct aq_nic_s {
struct aq_obj_s header;
struct aq_vec_s *aq_vec[AQ_CFG_VECS_MAX];
struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX];
struct aq_hw_s *aq_hw;
struct net_device *ndev;
struct aq_pci_func_s *aq_pci_func;
unsigned int aq_vecs;
unsigned int packet_filter;
unsigned int power_state;
bool is_ndev_registered;
u8 port;
struct aq_hw_ops aq_hw_ops;
struct aq_hw_caps_s aq_hw_caps;
struct aq_nic_cfg_s aq_nic_cfg;
struct timer_list service_timer;
struct timer_list polling_timer;
struct aq_hw_link_status_s link_status;
struct {
u32 count;
u8 ar[AQ_CFG_MULTICAST_ADDRESS_MAX][ETH_ALEN];
} mc_list;
};
#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
AQ_NIC_LINK_DOWN)
#endif /* AQ_NIC_INTERNAL_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_pci_func.c: Definition of PCI functions. */
#include "aq_pci_func.h"
#include "aq_nic.h"
#include "aq_vec.h"
#include "aq_hw.h"
#include <linux/interrupt.h>
struct aq_pci_func_s {
struct pci_dev *pdev;
struct aq_nic_s *port[AQ_CFG_PCI_FUNC_PORTS];
void __iomem *mmio;
void *aq_vec[AQ_CFG_PCI_FUNC_MSIX_IRQS];
resource_size_t mmio_pa;
unsigned int msix_entry_mask;
unsigned int irq_type;
unsigned int ports;
bool is_pci_enabled;
bool is_regions;
bool is_pci_using_dac;
struct aq_hw_caps_s aq_hw_caps;
struct msix_entry msix_entry[AQ_CFG_PCI_FUNC_MSIX_IRQS];
};
struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops,
struct pci_dev *pdev,
const struct net_device_ops *ndev_ops,
const struct ethtool_ops *eth_ops)
{
struct aq_pci_func_s *self = NULL;
int err = 0;
unsigned int port = 0U;
if (!aq_hw_ops) {
err = -EFAULT;
goto err_exit;
}
self = kzalloc(sizeof(*self), GFP_KERNEL);
if (!self) {
err = -ENOMEM;
goto err_exit;
}
pci_set_drvdata(pdev, self);
self->pdev = pdev;
err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps);
if (err < 0)
goto err_exit;
self->ports = self->aq_hw_caps.ports;
for (port = 0; port < self->ports; ++port) {
struct aq_nic_s *aq_nic = aq_nic_alloc_cold(ndev_ops, eth_ops,
&pdev->dev, self,
port, aq_hw_ops);
if (!aq_nic) {
err = -ENOMEM;
goto err_exit;
}
self->port[port] = aq_nic;
}
err_exit:
if (err < 0) {
if (self)
aq_pci_func_free(self);
self = NULL;
}
(void)err;
return self;
}
int aq_pci_func_init(struct aq_pci_func_s *self)
{
int err = 0;
unsigned int bar = 0U;
unsigned int port = 0U;
unsigned int i = 0U;
err = pci_enable_device(self->pdev);
if (err < 0)
goto err_exit;
self->is_pci_enabled = true;
err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(64));
if (!err) {
err = pci_set_consistent_dma_mask(self->pdev, DMA_BIT_MASK(64));
self->is_pci_using_dac = 1;
}
if (err) {
err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(32));
if (!err)
err = pci_set_consistent_dma_mask(self->pdev,
DMA_BIT_MASK(32));
self->is_pci_using_dac = 0;
}
if (err != 0) {
err = -ENOSR;
goto err_exit;
}
err = pci_request_regions(self->pdev, AQ_CFG_DRV_NAME "_mmio");
if (err < 0)
goto err_exit;
self->is_regions = true;
pci_set_master(self->pdev);
for (bar = 0; bar < 4; ++bar) {
if (IORESOURCE_MEM & pci_resource_flags(self->pdev, bar)) {
resource_size_t reg_sz;
self->mmio_pa = pci_resource_start(self->pdev, bar);
if (self->mmio_pa == 0U) {
err = -EIO;
goto err_exit;
}
reg_sz = pci_resource_len(self->pdev, bar);
if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
err = -EIO;
goto err_exit;
}
self->mmio = ioremap_nocache(self->mmio_pa, reg_sz);
if (!self->mmio) {
err = -EIO;
goto err_exit;
}
break;
}
}
if (err < 0)
goto err_exit;
for (i = 0; i < self->aq_hw_caps.msix_irqs; i++)
self->msix_entry[i].entry = i;
/*enable interrupts */
#if AQ_CFG_FORCE_LEGACY_INT
self->irq_type = AQ_HW_IRQ_LEGACY;
#else
err = pci_enable_msix(self->pdev, self->msix_entry,
self->aq_hw_caps.msix_irqs);
if (err >= 0) {
self->irq_type = AQ_HW_IRQ_MSIX;
} else {
err = pci_enable_msi(self->pdev);
if (err >= 0) {
self->irq_type = AQ_HW_IRQ_MSI;
} else {
self->irq_type = AQ_HW_IRQ_LEGACY;
err = 0;
}
}
#endif
/* net device init */
for (port = 0; port < self->ports; ++port) {
if (!self->port[port])
continue;
err = aq_nic_cfg_start(self->port[port]);
if (err < 0)
goto err_exit;
err = aq_nic_ndev_init(self->port[port]);
if (err < 0)
goto err_exit;
err = aq_nic_ndev_register(self->port[port]);
if (err < 0)
goto err_exit;
}
err_exit:
if (err < 0)
aq_pci_func_deinit(self);
return err;
}
int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
char *name, void *aq_vec, cpumask_t *affinity_mask)
{
int err = 0;
switch (self->irq_type) {
case AQ_HW_IRQ_MSIX:
err = request_irq(self->msix_entry[i].vector, aq_vec_isr, 0,
name, aq_vec);
break;
case AQ_HW_IRQ_MSI:
err = request_irq(self->pdev->irq, aq_vec_isr, 0, name, aq_vec);
break;
case AQ_HW_IRQ_LEGACY:
err = request_irq(self->pdev->irq, aq_vec_isr_legacy,
IRQF_SHARED, name, aq_vec);
break;
default:
err = -EFAULT;
break;
}
if (err >= 0) {
self->msix_entry_mask |= (1 << i);
self->aq_vec[i] = aq_vec;
if (self->irq_type == AQ_HW_IRQ_MSIX)
irq_set_affinity_hint(self->msix_entry[i].vector,
affinity_mask);
}
return err;
}
void aq_pci_func_free_irqs(struct aq_pci_func_s *self)
{
unsigned int i = 0U;
for (i = 32U; i--;) {
if (!((1U << i) & self->msix_entry_mask))
continue;
switch (self->irq_type) {
case AQ_HW_IRQ_MSIX:
irq_set_affinity_hint(self->msix_entry[i].vector, NULL);
free_irq(self->msix_entry[i].vector, self->aq_vec[i]);
break;
case AQ_HW_IRQ_MSI:
free_irq(self->pdev->irq, self->aq_vec[i]);
break;
case AQ_HW_IRQ_LEGACY:
free_irq(self->pdev->irq, self->aq_vec[i]);
break;
default:
break;
}
self->msix_entry_mask &= ~(1U << i);
}
}
void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self)
{
return self->mmio;
}
unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self)
{
return self->irq_type;
}
void aq_pci_func_deinit(struct aq_pci_func_s *self)
{
if (!self)
goto err_exit;
aq_pci_func_free_irqs(self);
switch (self->irq_type) {
case AQ_HW_IRQ_MSI:
pci_disable_msi(self->pdev);
break;
case AQ_HW_IRQ_MSIX:
pci_disable_msix(self->pdev);
break;
case AQ_HW_IRQ_LEGACY:
break;
default:
break;
}
if (self->is_regions)
pci_release_regions(self->pdev);
if (self->is_pci_enabled)
pci_disable_device(self->pdev);
err_exit:;
}
void aq_pci_func_free(struct aq_pci_func_s *self)
{
unsigned int port = 0U;
if (!self)
goto err_exit;
for (port = 0; port < self->ports; ++port) {
if (!self->port[port])
continue;
aq_nic_ndev_free(self->port[port]);
}
kfree(self);
err_exit:;
}
int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
pm_message_t *pm_msg)
{
int err = 0;
unsigned int port = 0U;
if (!self) {
err = -EFAULT;
goto err_exit;
}
for (port = 0; port < self->ports; ++port) {
if (!self->port[port])
continue;
(void)aq_nic_change_pm_state(self->port[port], pm_msg);
}
err_exit:
return err;
}
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_pci_func.h: Declaration of PCI functions. */
#ifndef AQ_PCI_FUNC_H
#define AQ_PCI_FUNC_H
#include "aq_common.h"
struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *hw_ops,
struct pci_dev *pdev,
const struct net_device_ops *ndev_ops,
const struct ethtool_ops *eth_ops);
int aq_pci_func_init(struct aq_pci_func_s *self);
int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
char *name, void *aq_vec,
cpumask_t *affinity_mask);
void aq_pci_func_free_irqs(struct aq_pci_func_s *self);
int aq_pci_func_start(struct aq_pci_func_s *self);
void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self);
unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self);
void aq_pci_func_deinit(struct aq_pci_func_s *self);
void aq_pci_func_free(struct aq_pci_func_s *self);
int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
pm_message_t *pm_msg);
#endif /* AQ_PCI_FUNC_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_ring.c: Definition of functions for Rx/Tx rings. */
#include "aq_ring.h"
#include "aq_nic.h"
#include "aq_hw.h"
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
static struct aq_ring_s *aq_ring_alloc(struct aq_ring_s *self,
struct aq_nic_s *aq_nic)
{
int err = 0;
self->buff_ring =
kcalloc(self->size, sizeof(struct aq_ring_buff_s), GFP_KERNEL);
if (!self->buff_ring) {
err = -ENOMEM;
goto err_exit;
}
self->dx_ring = dma_alloc_coherent(aq_nic_get_dev(aq_nic),
self->size * self->dx_size,
&self->dx_ring_pa, GFP_KERNEL);
if (!self->dx_ring) {
err = -ENOMEM;
goto err_exit;
}
err_exit:
if (err < 0) {
aq_ring_free(self);
self = NULL;
}
return self;
}
struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,
struct aq_nic_s *aq_nic,
unsigned int idx,
struct aq_nic_cfg_s *aq_nic_cfg)
{
int err = 0;
self->aq_nic = aq_nic;
self->idx = idx;
self->size = aq_nic_cfg->txds;
self->dx_size = aq_nic_cfg->aq_hw_caps->txd_size;
self = aq_ring_alloc(self, aq_nic);
if (!self) {
err = -ENOMEM;
goto err_exit;
}
err_exit:
if (err < 0) {
aq_ring_free(self);
self = NULL;
}
return self;
}
struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,
struct aq_nic_s *aq_nic,
unsigned int idx,
struct aq_nic_cfg_s *aq_nic_cfg)
{
int err = 0;
self->aq_nic = aq_nic;
self->idx = idx;
self->size = aq_nic_cfg->rxds;
self->dx_size = aq_nic_cfg->aq_hw_caps->rxd_size;
self = aq_ring_alloc(self, aq_nic);
if (!self) {
err = -ENOMEM;
goto err_exit;
}
err_exit:
if (err < 0) {
aq_ring_free(self);
self = NULL;
}
return self;
}
int aq_ring_init(struct aq_ring_s *self)
{
self->hw_head = 0;
self->sw_head = 0;
self->sw_tail = 0;
return 0;
}
void aq_ring_tx_append_buffs(struct aq_ring_s *self,
struct aq_ring_buff_s *buffer,
unsigned int buffers)
{
if (likely(self->sw_tail + buffers < self->size)) {
memcpy(&self->buff_ring[self->sw_tail], buffer,
sizeof(buffer[0]) * buffers);
} else {
unsigned int first_part = self->size - self->sw_tail;
unsigned int second_part = buffers - first_part;
memcpy(&self->buff_ring[self->sw_tail], buffer,
sizeof(buffer[0]) * first_part);
memcpy(&self->buff_ring[0], &buffer[first_part],
sizeof(buffer[0]) * second_part);
}
}
int aq_ring_tx_clean(struct aq_ring_s *self)
{
struct device *dev = aq_nic_get_dev(self->aq_nic);
for (; self->sw_head != self->hw_head;
self->sw_head = aq_ring_next_dx(self, self->sw_head)) {
struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
if (likely(buff->is_mapped)) {
if (unlikely(buff->is_sop))
dma_unmap_single(dev, buff->pa, buff->len,
DMA_TO_DEVICE);
else
dma_unmap_page(dev, buff->pa, buff->len,
DMA_TO_DEVICE);
}
if (unlikely(buff->is_eop))
dev_kfree_skb_any(buff->skb);
}
if (aq_ring_avail_dx(self) > AQ_CFG_SKB_FRAGS_MAX)
aq_nic_ndev_queue_start(self->aq_nic, self->idx);
return 0;
}
static inline unsigned int aq_ring_dx_in_range(unsigned int h, unsigned int i,
unsigned int t)
{
return (h < t) ? ((h < i) && (i < t)) : ((h < i) || (i < t));
}
#define AQ_SKB_ALIGN SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
int aq_ring_rx_clean(struct aq_ring_s *self, int *work_done, int budget)
{
struct net_device *ndev = aq_nic_get_ndev(self->aq_nic);
int err = 0;
bool is_rsc_completed = true;
for (; (self->sw_head != self->hw_head) && budget;
self->sw_head = aq_ring_next_dx(self, self->sw_head),
--budget, ++(*work_done)) {
struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
struct sk_buff *skb = NULL;
unsigned int next_ = 0U;
unsigned int i = 0U;
struct aq_ring_buff_s *buff_ = NULL;
if (buff->is_error) {
__free_pages(buff->page, 0);
continue;
}
if (buff->is_cleaned)
continue;
if (!buff->is_eop) {
for (next_ = buff->next,
buff_ = &self->buff_ring[next_]; true;
next_ = buff_->next,
buff_ = &self->buff_ring[next_]) {
is_rsc_completed =
aq_ring_dx_in_range(self->sw_head,
next_,
self->hw_head);
if (unlikely(!is_rsc_completed)) {
is_rsc_completed = false;
break;
}
if (buff_->is_eop)
break;
}
if (!is_rsc_completed) {
err = 0;
goto err_exit;
}
}
/* for single fragment packets use build_skb() */
if (buff->is_eop) {
skb = build_skb(page_address(buff->page),
buff->len + AQ_SKB_ALIGN);
if (unlikely(!skb)) {
err = -ENOMEM;
goto err_exit;
}
skb->dev = ndev;
skb_put(skb, buff->len);
} else {
skb = netdev_alloc_skb(ndev, ETH_HLEN);
if (unlikely(!skb)) {
err = -ENOMEM;
goto err_exit;
}
skb_put(skb, ETH_HLEN);
memcpy(skb->data, page_address(buff->page), ETH_HLEN);
skb_add_rx_frag(skb, 0, buff->page, ETH_HLEN,
buff->len - ETH_HLEN,
SKB_TRUESIZE(buff->len - ETH_HLEN));
for (i = 1U, next_ = buff->next,
buff_ = &self->buff_ring[next_]; true;
next_ = buff_->next,
buff_ = &self->buff_ring[next_], ++i) {
skb_add_rx_frag(skb, i, buff_->page, 0,
buff_->len,
SKB_TRUESIZE(buff->len -
ETH_HLEN));
buff_->is_cleaned = 1;
if (buff_->is_eop)
break;
}
}
skb->protocol = eth_type_trans(skb, ndev);
if (unlikely(buff->is_cso_err)) {
++self->stats.rx.errors;
__skb_mark_checksum_bad(skb);
} else {
if (buff->is_ip_cso) {
__skb_incr_checksum_unnecessary(skb);
if (buff->is_udp_cso || buff->is_tcp_cso)
__skb_incr_checksum_unnecessary(skb);
} else {
skb->ip_summed = CHECKSUM_NONE;
}
}
skb_set_hash(skb, buff->rss_hash,
buff->is_hash_l4 ? PKT_HASH_TYPE_L4 :
PKT_HASH_TYPE_NONE);
skb_record_rx_queue(skb, self->idx);
netif_receive_skb(skb);
++self->stats.rx.packets;
self->stats.rx.bytes += skb->len;
}
err_exit:
return err;
}
int aq_ring_rx_fill(struct aq_ring_s *self)
{
struct aq_ring_buff_s *buff = NULL;
int err = 0;
int i = 0;
for (i = aq_ring_avail_dx(self); i--;
self->sw_tail = aq_ring_next_dx(self, self->sw_tail)) {
buff = &self->buff_ring[self->sw_tail];
buff->flags = 0U;
buff->len = AQ_CFG_RX_FRAME_MAX;
buff->page = alloc_pages(GFP_ATOMIC | __GFP_COLD |
__GFP_COMP, 0);
if (!buff->page) {
err = -ENOMEM;
goto err_exit;
}
buff->pa = dma_map_page(aq_nic_get_dev(self->aq_nic),
buff->page, 0,
AQ_CFG_RX_FRAME_MAX, DMA_FROM_DEVICE);
err = dma_mapping_error(aq_nic_get_dev(self->aq_nic), buff->pa);
if (err < 0)
goto err_exit;
buff = NULL;
}
if (err < 0)
goto err_exit;
err_exit:
if (err < 0) {
if (buff && buff->page)
__free_pages(buff->page, 0);
}
return err;
}
void aq_ring_rx_deinit(struct aq_ring_s *self)
{
if (!self)
goto err_exit;
for (; self->sw_head != self->sw_tail;
self->sw_head = aq_ring_next_dx(self, self->sw_head)) {
struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
dma_unmap_page(aq_nic_get_dev(self->aq_nic), buff->pa,
AQ_CFG_RX_FRAME_MAX, DMA_FROM_DEVICE);
__free_pages(buff->page, 0);
}
err_exit:;
}
void aq_ring_tx_deinit(struct aq_ring_s *self)
{
if (!self)
goto err_exit;
for (; self->sw_head != self->sw_tail;
self->sw_head = aq_ring_next_dx(self, self->sw_head)) {
struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
struct device *ndev = aq_nic_get_dev(self->aq_nic);
if (likely(buff->is_mapped)) {
if (unlikely(buff->is_sop)) {
dma_unmap_single(ndev, buff->pa, buff->len,
DMA_TO_DEVICE);
} else {
dma_unmap_page(ndev, buff->pa, buff->len,
DMA_TO_DEVICE);
}
}
if (unlikely(buff->is_eop))
dev_kfree_skb_any(buff->skb);
}
err_exit:;
}
void aq_ring_free(struct aq_ring_s *self)
{
if (!self)
goto err_exit;
kfree(self->buff_ring);
if (self->dx_ring)
dma_free_coherent(aq_nic_get_dev(self->aq_nic),
self->size * self->dx_size, self->dx_ring,
self->dx_ring_pa);
err_exit:;
}
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_ring.h: Declaration of functions for Rx/Tx rings. */
#ifndef AQ_RING_H
#define AQ_RING_H
#include "aq_common.h"
struct page;
/* TxC SOP DX EOP
* +----------+----------+----------+-----------
* 8bytes|len l3,l4 | pa | pa | pa
* +----------+----------+----------+-----------
* 4/8bytes|len pkt |len pkt | | skb
* +----------+----------+----------+-----------
* 4/8bytes|is_txc |len,flags |len |len,is_eop
* +----------+----------+----------+-----------
*
* This aq_ring_buff_s doesn't have endianness dependency.
* It is __packed for cache line optimizations.
*/
struct __packed aq_ring_buff_s {
union {
/* RX */
struct {
u32 rss_hash;
u16 next;
u8 is_hash_l4;
u8 rsvd1;
struct page *page;
};
/* EOP */
struct {
dma_addr_t pa_eop;
struct sk_buff *skb;
};
/* DX */
struct {
dma_addr_t pa;
};
/* SOP */
struct {
dma_addr_t pa_sop;
u32 len_pkt_sop;
};
/* TxC */
struct {
u32 mss;
u8 len_l2;
u8 len_l3;
u8 len_l4;
u8 rsvd2;
u32 len_pkt;
};
};
union {
struct {
u32 len:16;
u32 is_ip_cso:1;
u32 is_udp_cso:1;
u32 is_tcp_cso:1;
u32 is_cso_err:1;
u32 is_sop:1;
u32 is_eop:1;
u32 is_txc:1;
u32 is_mapped:1;
u32 is_cleaned:1;
u32 is_error:1;
u32 rsvd3:6;
};
u32 flags;
};
};
struct aq_ring_stats_rx_s {
u64 errors;
u64 packets;
u64 bytes;
u64 lro_packets;
u64 jumbo_packets;
};
struct aq_ring_stats_tx_s {
u64 errors;
u64 packets;
u64 bytes;
};
union aq_ring_stats_s {
struct aq_ring_stats_rx_s rx;
struct aq_ring_stats_tx_s tx;
};
struct aq_ring_s {
struct aq_obj_s header;
struct aq_ring_buff_s *buff_ring;
u8 *dx_ring; /* descriptors ring, dma shared mem */
struct aq_nic_s *aq_nic;
unsigned int idx; /* for HW layer registers operations */
unsigned int hw_head;
unsigned int sw_head;
unsigned int sw_tail;
unsigned int size; /* descriptors number */
unsigned int dx_size; /* TX or RX descriptor size, */
/* stored here for fater math */
union aq_ring_stats_s stats;
dma_addr_t dx_ring_pa;
};
struct aq_ring_param_s {
unsigned int vec_idx;
unsigned int cpu;
cpumask_t affinity_mask;
};
static inline unsigned int aq_ring_next_dx(struct aq_ring_s *self,
unsigned int dx)
{
return (++dx >= self->size) ? 0U : dx;
}
static inline unsigned int aq_ring_avail_dx(struct aq_ring_s *self)
{
return (((self->sw_tail >= self->sw_head)) ?
(self->size - 1) - self->sw_tail + self->sw_head :
self->sw_head - self->sw_tail - 1);
}
struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,
struct aq_nic_s *aq_nic,
unsigned int idx,
struct aq_nic_cfg_s *aq_nic_cfg);
struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,
struct aq_nic_s *aq_nic,
unsigned int idx,
struct aq_nic_cfg_s *aq_nic_cfg);
int aq_ring_init(struct aq_ring_s *self);
void aq_ring_tx_deinit(struct aq_ring_s *self);
void aq_ring_rx_deinit(struct aq_ring_s *self);
void aq_ring_free(struct aq_ring_s *self);
void aq_ring_tx_append_buffs(struct aq_ring_s *ring,
struct aq_ring_buff_s *buffer,
unsigned int buffers);
int aq_ring_tx_clean(struct aq_ring_s *self);
int aq_ring_rx_clean(struct aq_ring_s *self, int *work_done, int budget);
int aq_ring_rx_fill(struct aq_ring_s *self);
#endif /* AQ_RING_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_rss.h: Receive Side Scaling definitions. */
#ifndef AQ_RSS_H
#define AQ_RSS_H
#include "aq_common.h"
#include "aq_cfg.h"
struct aq_rss_parameters {
u16 base_cpu_number;
u16 indirection_table_size;
u16 hash_secret_key_size;
u32 hash_secret_key[AQ_CFG_RSS_HASHKEY_SIZE / sizeof(u32)];
u8 indirection_table[AQ_CFG_RSS_INDIRECTION_TABLE_MAX];
};
#endif /* AQ_RSS_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_utils.h: Useful macro and structures used in all layers of driver. */
#ifndef AQ_UTILS_H
#define AQ_UTILS_H
#include "aq_common.h"
#define AQ_DIMOF(_ARY_) ARRAY_SIZE(_ARY_)
struct aq_obj_s {
spinlock_t lock; /* spinlock for nic/rings processing */
atomic_t flags;
atomic_t busy_count;
};
static inline void aq_utils_obj_set(atomic_t *flags, u32 mask)
{
unsigned long flags_old, flags_new;
do {
flags_old = atomic_read(flags);
flags_new = flags_old | (mask);
} while (atomic_cmpxchg(flags, flags_old, flags_new) != flags_old);
}
static inline void aq_utils_obj_clear(atomic_t *flags, u32 mask)
{
unsigned long flags_old, flags_new;
do {
flags_old = atomic_read(flags);
flags_new = flags_old & ~(mask);
} while (atomic_cmpxchg(flags, flags_old, flags_new) != flags_old);
}
static inline bool aq_utils_obj_test(atomic_t *flags, u32 mask)
{
return atomic_read(flags) & mask;
}
#endif /* AQ_UTILS_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_vec.c: Definition of common structure for vector of Rx and Tx rings.
* Definition of functions for Rx and Tx rings. Friendly module for aq_nic.
*/
#include "aq_vec.h"
#include "aq_nic.h"
#include "aq_ring.h"
#include "aq_hw.h"
#include <linux/netdevice.h>
struct aq_vec_s {
struct aq_obj_s header;
struct aq_hw_ops *aq_hw_ops;
struct aq_hw_s *aq_hw;
struct aq_nic_s *aq_nic;
unsigned int tx_rings;
unsigned int rx_rings;
struct aq_ring_param_s aq_ring_param;
struct napi_struct napi;
struct aq_ring_s ring[AQ_CFG_TCS_MAX][2];
};
#define AQ_VEC_TX_ID 0
#define AQ_VEC_RX_ID 1
static int aq_vec_poll(struct napi_struct *napi, int budget)
__releases(&self->lock)
__acquires(&self->lock)
{
struct aq_vec_s *self = container_of(napi, struct aq_vec_s, napi);
struct aq_ring_s *ring = NULL;
int work_done = 0;
int err = 0;
unsigned int i = 0U;
unsigned int sw_tail_old = 0U;
bool was_tx_cleaned = false;
if (!self) {
err = -EINVAL;
} else if (spin_trylock(&self->header.lock)) {
for (i = 0U, ring = self->ring[0];
self->tx_rings > i; ++i, ring = self->ring[i]) {
if (self->aq_hw_ops->hw_ring_tx_head_update) {
err = self->aq_hw_ops->hw_ring_tx_head_update(
self->aq_hw,
&ring[AQ_VEC_TX_ID]);
if (err < 0)
goto err_exit;
}
if (ring[AQ_VEC_TX_ID].sw_head !=
ring[AQ_VEC_TX_ID].hw_head) {
err = aq_ring_tx_clean(&ring[AQ_VEC_TX_ID]);
if (err < 0)
goto err_exit;
was_tx_cleaned = true;
}
err = self->aq_hw_ops->hw_ring_rx_receive(self->aq_hw,
&ring[AQ_VEC_RX_ID]);
if (err < 0)
goto err_exit;
if (ring[AQ_VEC_RX_ID].sw_head !=
ring[AQ_VEC_RX_ID].hw_head) {
err = aq_ring_rx_clean(&ring[AQ_VEC_RX_ID],
&work_done,
budget - work_done);
if (err < 0)
goto err_exit;
sw_tail_old = ring[AQ_VEC_RX_ID].sw_tail;
err = aq_ring_rx_fill(&ring[AQ_VEC_RX_ID]);
if (err < 0)
goto err_exit;
err = self->aq_hw_ops->hw_ring_rx_fill(
self->aq_hw,
&ring[AQ_VEC_RX_ID], sw_tail_old);
if (err < 0)
goto err_exit;
}
}
if (was_tx_cleaned)
work_done = budget;
if (work_done < budget) {
napi_complete(napi);
self->aq_hw_ops->hw_irq_enable(self->aq_hw,
1U << self->aq_ring_param.vec_idx);
}
err_exit:
spin_unlock(&self->header.lock);
}
return work_done;
}
struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx,
struct aq_nic_cfg_s *aq_nic_cfg)
{
struct aq_vec_s *self = NULL;
struct aq_ring_s *ring = NULL;
unsigned int i = 0U;
int err = 0;
self = kzalloc(sizeof(*self), GFP_KERNEL);
if (!self) {
err = -ENOMEM;
goto err_exit;
}
self->aq_nic = aq_nic;
self->aq_ring_param.vec_idx = idx;
self->aq_ring_param.cpu =
idx + aq_nic_cfg->aq_rss.base_cpu_number;
cpumask_set_cpu(self->aq_ring_param.cpu,
&self->aq_ring_param.affinity_mask);
self->tx_rings = 0;
self->rx_rings = 0;
netif_napi_add(aq_nic_get_ndev(aq_nic), &self->napi,
aq_vec_poll, AQ_CFG_NAPI_WEIGHT);
for (i = 0; i < aq_nic_cfg->tcs; ++i) {
unsigned int idx_ring = AQ_NIC_TCVEC2RING(self->nic,
self->tx_rings,
self->aq_ring_param.vec_idx);
ring = aq_ring_tx_alloc(&self->ring[i][AQ_VEC_TX_ID], aq_nic,
idx_ring, aq_nic_cfg);
if (!ring) {
err = -ENOMEM;
goto err_exit;
}
++self->tx_rings;
aq_nic_set_tx_ring(aq_nic, idx_ring, ring);
ring = aq_ring_rx_alloc(&self->ring[i][AQ_VEC_RX_ID], aq_nic,
idx_ring, aq_nic_cfg);
if (!ring) {
err = -ENOMEM;
goto err_exit;
}
++self->rx_rings;
}
err_exit:
if (err < 0) {
aq_vec_free(self);
self = NULL;
}
return self;
}
int aq_vec_init(struct aq_vec_s *self, struct aq_hw_ops *aq_hw_ops,
struct aq_hw_s *aq_hw)
{
struct aq_ring_s *ring = NULL;
unsigned int i = 0U;
int err = 0;
self->aq_hw_ops = aq_hw_ops;
self->aq_hw = aq_hw;
spin_lock_init(&self->header.lock);
for (i = 0U, ring = self->ring[0];
self->tx_rings > i; ++i, ring = self->ring[i]) {
err = aq_ring_init(&ring[AQ_VEC_TX_ID]);
if (err < 0)
goto err_exit;
err = self->aq_hw_ops->hw_ring_tx_init(self->aq_hw,
&ring[AQ_VEC_TX_ID],
&self->aq_ring_param);
if (err < 0)
goto err_exit;
err = aq_ring_init(&ring[AQ_VEC_RX_ID]);
if (err < 0)
goto err_exit;
err = self->aq_hw_ops->hw_ring_rx_init(self->aq_hw,
&ring[AQ_VEC_RX_ID],
&self->aq_ring_param);
if (err < 0)
goto err_exit;
err = aq_ring_rx_fill(&ring[AQ_VEC_RX_ID]);
if (err < 0)
goto err_exit;
err = self->aq_hw_ops->hw_ring_rx_fill(self->aq_hw,
&ring[AQ_VEC_RX_ID], 0U);
if (err < 0)
goto err_exit;
}
err_exit:
return err;
}
int aq_vec_start(struct aq_vec_s *self)
{
struct aq_ring_s *ring = NULL;
unsigned int i = 0U;
int err = 0;
for (i = 0U, ring = self->ring[0];
self->tx_rings > i; ++i, ring = self->ring[i]) {
err = self->aq_hw_ops->hw_ring_tx_start(self->aq_hw,
&ring[AQ_VEC_TX_ID]);
if (err < 0)
goto err_exit;
err = self->aq_hw_ops->hw_ring_rx_start(self->aq_hw,
&ring[AQ_VEC_RX_ID]);
if (err < 0)
goto err_exit;
}
napi_enable(&self->napi);
err_exit:
return err;
}
void aq_vec_stop(struct aq_vec_s *self)
{
struct aq_ring_s *ring = NULL;
unsigned int i = 0U;
for (i = 0U, ring = self->ring[0];
self->tx_rings > i; ++i, ring = self->ring[i]) {
self->aq_hw_ops->hw_ring_tx_stop(self->aq_hw,
&ring[AQ_VEC_TX_ID]);
self->aq_hw_ops->hw_ring_rx_stop(self->aq_hw,
&ring[AQ_VEC_RX_ID]);
}
napi_disable(&self->napi);
}
void aq_vec_deinit(struct aq_vec_s *self)
{
struct aq_ring_s *ring = NULL;
unsigned int i = 0U;
if (!self)
goto err_exit;
for (i = 0U, ring = self->ring[0];
self->tx_rings > i; ++i, ring = self->ring[i]) {
aq_ring_tx_deinit(&ring[AQ_VEC_TX_ID]);
aq_ring_rx_deinit(&ring[AQ_VEC_RX_ID]);
}
err_exit:;
}
void aq_vec_free(struct aq_vec_s *self)
{
struct aq_ring_s *ring = NULL;
unsigned int i = 0U;
if (!self)
goto err_exit;
for (i = 0U, ring = self->ring[0];
self->tx_rings > i; ++i, ring = self->ring[i]) {
aq_ring_free(&ring[AQ_VEC_TX_ID]);
aq_ring_free(&ring[AQ_VEC_RX_ID]);
}
netif_napi_del(&self->napi);
kfree(self);
err_exit:;
}
irqreturn_t aq_vec_isr(int irq, void *private)
{
struct aq_vec_s *self = private;
int err = 0;
if (!self) {
err = -EINVAL;
goto err_exit;
}
napi_schedule(&self->napi);
err_exit:
return err >= 0 ? IRQ_HANDLED : IRQ_NONE;
}
irqreturn_t aq_vec_isr_legacy(int irq, void *private)
{
struct aq_vec_s *self = private;
u64 irq_mask = 0U;
irqreturn_t err = 0;
if (!self) {
err = -EINVAL;
goto err_exit;
}
err = self->aq_hw_ops->hw_irq_read(self->aq_hw, &irq_mask);
if (err < 0)
goto err_exit;
if (irq_mask) {
self->aq_hw_ops->hw_irq_disable(self->aq_hw,
1U << self->aq_ring_param.vec_idx);
napi_schedule(&self->napi);
} else {
self->aq_hw_ops->hw_irq_enable(self->aq_hw, 1U);
err = IRQ_NONE;
}
err_exit:
return err >= 0 ? IRQ_HANDLED : IRQ_NONE;
}
cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self)
{
return &self->aq_ring_param.affinity_mask;
}
void aq_vec_add_stats(struct aq_vec_s *self,
struct aq_ring_stats_rx_s *stats_rx,
struct aq_ring_stats_tx_s *stats_tx)
{
struct aq_ring_s *ring = NULL;
unsigned int r = 0U;
for (r = 0U, ring = self->ring[0];
self->tx_rings > r; ++r, ring = self->ring[r]) {
struct aq_ring_stats_tx_s *tx = &ring[AQ_VEC_TX_ID].stats.tx;
struct aq_ring_stats_rx_s *rx = &ring[AQ_VEC_RX_ID].stats.rx;
stats_rx->packets += rx->packets;
stats_rx->bytes += rx->bytes;
stats_rx->errors += rx->errors;
stats_rx->jumbo_packets += rx->jumbo_packets;
stats_rx->lro_packets += rx->lro_packets;
stats_tx->packets += tx->packets;
stats_tx->bytes += tx->bytes;
stats_tx->errors += tx->errors;
}
}
int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data, unsigned int *p_count)
{
unsigned int count = 0U;
struct aq_ring_stats_rx_s stats_rx;
struct aq_ring_stats_tx_s stats_tx;
memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s));
memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s));
aq_vec_add_stats(self, &stats_rx, &stats_tx);
data[count] += stats_rx.packets;
data[++count] += stats_tx.packets;
data[++count] += stats_rx.jumbo_packets;
data[++count] += stats_rx.lro_packets;
data[++count] += stats_rx.errors;
if (p_count)
*p_count = ++count;
return 0;
}
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File aq_vec.h: Definition of common structures for vector of Rx and Tx rings.
* Declaration of functions for Rx and Tx rings.
*/
#ifndef AQ_VEC_H
#define AQ_VEC_H
#include "aq_common.h"
#include <linux/irqreturn.h>
struct aq_hw_s;
struct aq_hw_ops;
struct aq_ring_stats_rx_s;
struct aq_ring_stats_tx_s;
irqreturn_t aq_vec_isr(int irq, void *private);
irqreturn_t aq_vec_isr_legacy(int irq, void *private);
struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx,
struct aq_nic_cfg_s *aq_nic_cfg);
int aq_vec_init(struct aq_vec_s *self, struct aq_hw_ops *aq_hw_ops,
struct aq_hw_s *aq_hw);
void aq_vec_deinit(struct aq_vec_s *self);
void aq_vec_free(struct aq_vec_s *self);
int aq_vec_start(struct aq_vec_s *self);
void aq_vec_stop(struct aq_vec_s *self);
cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self);
int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data,
unsigned int *p_count);
void aq_vec_add_stats(struct aq_vec_s *self,
struct aq_ring_stats_rx_s *stats_rx,
struct aq_ring_stats_tx_s *stats_tx);
#endif /* AQ_VEC_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File hw_atl_a0.h: Declaration of abstract interface for Atlantic hardware
* specific functions.
*/
#ifndef HW_ATL_A0_H
#define HW_ATL_A0_H
#include "../aq_common.h"
#ifndef PCI_VENDOR_ID_AQUANTIA
#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
#define HW_ATL_DEVICE_ID_0001 0x0001
#define HW_ATL_DEVICE_ID_D100 0xD100
#define HW_ATL_DEVICE_ID_D107 0xD107
#define HW_ATL_DEVICE_ID_D108 0xD108
#define HW_ATL_DEVICE_ID_D109 0xD109
#define HW_ATL_NIC_NAME "aQuantia AQtion 5Gbit Network Adapter"
#endif
struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev);
#endif /* HW_ATL_A0_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File hw_atl_a0_internal.h: Definition of Atlantic A0 chip specific
* constants.
*/
#ifndef HW_ATL_A0_INTERNAL_H
#define HW_ATL_A0_INTERNAL_H
#include "../aq_common.h"
#define HW_ATL_A0_MTU_JUMBO 9014U
#define HW_ATL_A0_TX_RINGS 4U
#define HW_ATL_A0_RX_RINGS 4U
#define HW_ATL_A0_RINGS_MAX 32U
#define HW_ATL_A0_TXD_SIZE 16U
#define HW_ATL_A0_RXD_SIZE 16U
#define HW_ATL_A0_MAC 0U
#define HW_ATL_A0_MAC_MIN 1U
#define HW_ATL_A0_MAC_MAX 33U
/* interrupts */
#define HW_ATL_A0_ERR_INT 8U
#define HW_ATL_A0_INT_MASK 0xFFFFFFFFU
#define HW_ATL_A0_TXD_CTL2_LEN 0xFFFFC000U
#define HW_ATL_A0_TXD_CTL2_CTX_EN 0x00002000U
#define HW_ATL_A0_TXD_CTL2_CTX_IDX 0x00001000U
#define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD 0x00000001U
#define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC 0x00000002U
#define HW_ATL_A0_TXD_CTL_BLEN 0x000FFFF0U
#define HW_ATL_A0_TXD_CTL_DD 0x00100000U
#define HW_ATL_A0_TXD_CTL_EOP 0x00200000U
#define HW_ATL_A0_TXD_CTL_CMD_X 0x3FC00000U
#define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22)
#define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23)
#define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24)
#define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25)
#define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26)
#define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27)
#define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28)
#define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21)
#define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22)
#define HW_ATL_A0_MPI_CONTROL_ADR 0x0368U
#define HW_ATL_A0_MPI_STATE_ADR 0x036CU
#define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU
#define HW_ATL_A0_MPI_SPEED_SHIFT 16U
#define HW_ATL_A0_RATE_10G BIT(0)
#define HW_ATL_A0_RATE_5G BIT(1)
#define HW_ATL_A0_RATE_2G5 BIT(3)
#define HW_ATL_A0_RATE_1G BIT(4)
#define HW_ATL_A0_RATE_100M BIT(5)
#define HW_ATL_A0_TXBUF_MAX 160U
#define HW_ATL_A0_RXBUF_MAX 320U
#define HW_ATL_A0_RSS_REDIRECTION_MAX 64U
#define HW_ATL_A0_RSS_REDIRECTION_BITS 3U
#define HW_ATL_A0_TC_MAX 1U
#define HW_ATL_A0_RSS_MAX 8U
#define HW_ATL_A0_FW_SEMA_RAM 0x2U
#define HW_ATL_A0_RXD_DD 0x1U
#define HW_ATL_A0_RXD_NCEA0 0x1U
#define HW_ATL_A0_RXD_WB_STAT2_EOP 0x0002U
#define HW_ATL_A0_UCP_0X370_REG 0x370U
#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
/* Hardware tx descriptor */
struct __packed hw_atl_txd_s {
u64 buf_addr;
u32 ctl;
u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
};
/* Hardware tx context descriptor */
struct __packed hw_atl_txc_s {
u32 rsvd;
u32 len;
u32 ctl;
u32 len2;
};
/* Hardware rx descriptor */
struct __packed hw_atl_rxd_s {
u64 buf_addr;
u64 hdr_addr;
};
/* Hardware rx descriptor writeback */
struct __packed hw_atl_rxd_wb_s {
u32 type;
u32 rss_hash;
u16 status;
u16 pkt_len;
u16 next_desc_ptr;
u16 vlan;
};
/* HW layer capabilities */
static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = {
.ports = 1U,
.is_64_dma = true,
.msix_irqs = 4U,
.irq_mask = ~0U,
.vecs = HW_ATL_A0_RSS_MAX,
.tcs = HW_ATL_A0_TC_MAX,
.rxd_alignment = 1U,
.rxd_size = HW_ATL_A0_RXD_SIZE,
.rxds = 248U,
.txd_alignment = 1U,
.txd_size = HW_ATL_A0_TXD_SIZE,
.txds = 8U * 1024U,
.txhwb_alignment = 4096U,
.tx_rings = HW_ATL_A0_TX_RINGS,
.rx_rings = HW_ATL_A0_RX_RINGS,
.hw_features = NETIF_F_HW_CSUM |
NETIF_F_RXHASH |
NETIF_F_SG |
NETIF_F_TSO,
.hw_priv_flags = IFF_UNICAST_FLT,
.link_speed_msk = (HW_ATL_A0_RATE_10G |
HW_ATL_A0_RATE_5G |
HW_ATL_A0_RATE_2G5 |
HW_ATL_A0_RATE_1G |
HW_ATL_A0_RATE_100M),
.flow_control = true,
.mtu = HW_ATL_A0_MTU_JUMBO,
.mac_regs_count = 88,
.fw_ver_expected = HW_ATL_A0_FW_VER_EXPECTED,
};
#endif /* HW_ATL_A0_INTERNAL_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware
* specific functions.
*/
#ifndef HW_ATL_B0_H
#define HW_ATL_B0_H
#include "../aq_common.h"
#ifndef PCI_VENDOR_ID_AQUANTIA
#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
#define HW_ATL_DEVICE_ID_0001 0x0001
#define HW_ATL_DEVICE_ID_D100 0xD100
#define HW_ATL_DEVICE_ID_D107 0xD107
#define HW_ATL_DEVICE_ID_D108 0xD108
#define HW_ATL_DEVICE_ID_D109 0xD109
#define HW_ATL_NIC_NAME "aQuantia AQtion 5Gbit Network Adapter"
#endif
struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev);
#endif /* HW_ATL_B0_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific
* constants.
*/
#ifndef HW_ATL_B0_INTERNAL_H
#define HW_ATL_B0_INTERNAL_H
#include "../aq_common.h"
#define HW_ATL_B0_MTU_JUMBO (16000U)
#define HW_ATL_B0_MTU 1514U
#define HW_ATL_B0_TX_RINGS 4U
#define HW_ATL_B0_RX_RINGS 4U
#define HW_ATL_B0_RINGS_MAX 32U
#define HW_ATL_B0_TXD_SIZE (16U)
#define HW_ATL_B0_RXD_SIZE (16U)
#define HW_ATL_B0_MAC 0U
#define HW_ATL_B0_MAC_MIN 1U
#define HW_ATL_B0_MAC_MAX 33U
/* UCAST/MCAST filters */
#define HW_ATL_B0_UCAST_FILTERS_MAX 38
#define HW_ATL_B0_MCAST_FILTERS_MAX 8
/* interrupts */
#define HW_ATL_B0_ERR_INT 8U
#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
#define HW_ATL_B0_TXD_CTL_DD (0x00100000)
#define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)
#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U
#define HW_ATL_B0_MPI_STATE_ADR 0x036CU
#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
#define HW_ATL_B0_MPI_SPEED_SHIFT 16U
#define HW_ATL_B0_RATE_10G BIT(0)
#define HW_ATL_B0_RATE_5G BIT(1)
#define HW_ATL_B0_RATE_2G5 BIT(3)
#define HW_ATL_B0_RATE_1G BIT(4)
#define HW_ATL_B0_RATE_100M BIT(5)
#define HW_ATL_B0_TXBUF_MAX 160U
#define HW_ATL_B0_RXBUF_MAX 320U
#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U
#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U
#define HW_ATL_B0_RSS_HASHKEY_BITS 320U
#define HW_ATL_B0_TCRSS_4_8 1
#define HW_ATL_B0_TC_MAX 1U
#define HW_ATL_B0_RSS_MAX 8U
#define HW_ATL_B0_LRO_RXD_MAX 2U
#define HW_ATL_B0_RS_SLIP_ENABLED 0U
/* (256k -1(max pay_len) - 54(header)) */
#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U
/* (256k -1(max pay_len) - 74(header)) */
#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U
#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U
#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU
#define HW_ATL_B0_FW_SEMA_RAM 0x2U
#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)
#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)
#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)
#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)
#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)
#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)
#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)
#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */
#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */
#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)
#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)
#define HW_ATL_B0_RXD_DD (0x1)
#define HW_ATL_B0_RXD_NCEA0 (0x1)
#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)
#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)
#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)
#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)
#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)
#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)
#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)
#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)
#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)
#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)
#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)
#define L2_FILTER_ACTION_DISCARD (0x0)
#define L2_FILTER_ACTION_HOST (0x1)
#define HW_ATL_B0_UCP_0X370_REG (0x370)
#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)
#define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U
/* Hardware tx descriptor */
struct __packed hw_atl_txd_s {
u64 buf_addr;
u32 ctl;
u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
};
/* Hardware tx context descriptor */
struct __packed hw_atl_txc_s {
u32 rsvd;
u32 len;
u32 ctl;
u32 len2;
};
/* Hardware rx descriptor */
struct __packed hw_atl_rxd_s {
u64 buf_addr;
u64 hdr_addr;
};
/* Hardware rx descriptor writeback */
struct __packed hw_atl_rxd_wb_s {
u32 type;
u32 rss_hash;
u16 status;
u16 pkt_len;
u16 next_desc_ptr;
u16 vlan;
};
/* HW layer capabilities */
static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
.ports = 1U,
.is_64_dma = true,
.msix_irqs = 4U,
.irq_mask = ~0U,
.vecs = HW_ATL_B0_RSS_MAX,
.tcs = HW_ATL_B0_TC_MAX,
.rxd_alignment = 1U,
.rxd_size = HW_ATL_B0_RXD_SIZE,
.rxds = 8U * 1024U,
.txd_alignment = 1U,
.txd_size = HW_ATL_B0_TXD_SIZE,
.txds = 8U * 1024U,
.txhwb_alignment = 4096U,
.tx_rings = HW_ATL_B0_TX_RINGS,
.rx_rings = HW_ATL_B0_RX_RINGS,
.hw_features = NETIF_F_HW_CSUM |
NETIF_F_RXHASH |
NETIF_F_SG |
NETIF_F_TSO |
NETIF_F_LRO,
.hw_priv_flags = IFF_UNICAST_FLT,
.link_speed_msk = (HW_ATL_B0_RATE_10G |
HW_ATL_B0_RATE_5G |
HW_ATL_B0_RATE_2G5 |
HW_ATL_B0_RATE_1G |
HW_ATL_B0_RATE_100M),
.flow_control = true,
.mtu = HW_ATL_B0_MTU_JUMBO,
.mac_regs_count = 88,
.fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED,
};
#endif /* HW_ATL_B0_INTERNAL_H */
/*
* aQuantia Corporation Network Driver
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#ifndef VER_H
#define VER_H
#define NIC_MAJOR_DRIVER_VERSION 1
#define NIC_MINOR_DRIVER_VERSION 5
#define NIC_BUILD_DRIVER_VERSION 345
#define NIC_REVISION_DRIVER_VERSION 0
#endif /* VER_H */
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