RISC-V: Disable preemption before enabling interrupts
Currently, irq is enabled before preemption disabling happens. If the scheduler fired right here and cpu is scheduled then it may blow up. Signed-off-by: NPalmer Dabbelt <palmer@sifive.com> [Atish: Commit text and code comment formatting update] Signed-off-by: NAtish Patra <atish.patra@wdc.com> Reviewed-by: NChristoph Hellwig <hch@lst.de> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Showing
想要评论请 注册 或 登录